CN110737615A - data access method and device - Google Patents
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- CN110737615A CN110737615A CN201810796301.8A CN201810796301A CN110737615A CN 110737615 A CN110737615 A CN 110737615A CN 201810796301 A CN201810796301 A CN 201810796301A CN 110737615 A CN110737615 A CN 110737615A
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- 238000000034 method Methods 0.000 title claims abstract description 18
- 238000013500 data storage Methods 0.000 claims abstract description 17
- 230000005540 biological transmission Effects 0.000 claims description 11
- 125000004122 cyclic group Chemical group 0.000 claims description 10
- 230000015654 memory Effects 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 2
- 238000012935 Averaging Methods 0.000 claims 1
- 241001522296 Erithacus rubecula Species 0.000 claims 1
- 238000005259 measurement Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009432 framing Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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Abstract
The invention provides an data access method and device, wherein a computing unit is responsible for collecting input original state data and computing the number m of required registers, a data writing unit is responsible for writing the data into a data storage unit according to a sequential circulation method, the data storage unit comprises m registers with the same length as the stored data and is numbered in sequence, and a data output unit is responsible for outputting the data according to the sequential circulation method.
Description
Technical Field
The invention relates to the technical field of data transmission, in particular to the technical field of remote measurement and control and information transmission.
Background
In the unmanned aerial vehicle measurement and control system, ground or airborne measurement and control equipment needs to receive ground remote control instructions or airborne telemetering information through data interfaces (serial ports, network ports and the like). As the data receiving time and the data sending time of the measurement and control equipment cannot be completely aligned, generally adopts a cache mode, a register receives and stores external data, and the data is extracted from the register at the time of sending the data to perform framing sending, in order to reduce the frame loss situation of important data, the conventional measurement and control equipment manufacturer generally adopts a repeated sending mode, but the repeated data can occupy larger bandwidth and reduce the information transmission efficiency.
To ensure the reliability of information transmission, -type measurement and control is requiredTransmission period T for transmitting data by equipmentoutShould be slightly less than the period T of sending external data to the measurement and control equipmentin。
But in practical application, due to ToutAnd TinIf the time of T is not , the read time and the storage time of the register will slip relatively, when T is equal tooutAnd TinWhen the time of the data is coincident, the register is simultaneously subjected to writing operation and reading operation, and the measurement and control equipment reads incomplete or wrong data, so that the data of the frame is invalid.
In another aspect of , TinFor average values, there is relatively large fluctuation in the actual transmission time of data, which may occur in transmission periods ToutThe internal register needs to store the state of two packet data, if the size of the register is data frames long, frame loss will inevitably occur, and if a single register is too large, hardware resources will be wasted for the system.
Disclosure of Invention
The invention provides an data access method and device, which can solve the technical problems of frame loss and hardware resource waste in the existing data access technology.
The invention provides an data access method, which comprises the following steps:
, confirming the input characteristics including data length L and average period TinMaximum transmission error of data Δ tin。
The second step is that: calculating the number m of the opened registers: calculating positive integers
The number m of the opened registers is n + 2.
The third step: opening up m registers C with length Lm......C2、C1。
The fourth step: when receiving input data, detecting the storage state (including data state and non-data state) of the register, circularly storing the data in m registers according to the sequence, and setting the stored register state as data.
The fifth step: and at the data output moment, detecting the storage state of the register, reading the data in the register in sequence and circulation, and setting the read register state as no data.
The maximum transmission error refers to the actual input time T of a certain packet datai'nAccording to the period TinMaximum deviation of theoretical input time obtained by subtraction.
The output period T of the dataoutSlightly less than input period TinPreferably ToutAnd TinThe difference is not more than 1% Tin。
The positive integer n is required to satisfy (n-1) Tout<Δtin≤nTout，That is, in output periods, at most n +1 frame data is input.
The sequential cyclic storage refers to the storage from C1Starting to sequentially detect data, and if no data exists in the m memories, storing the data in C1Performing the following steps; if CkWherein (k ═ 1,2, 3 … … m-1) has data, Ck+1If there is no data, store the data in Ck+1K is the minimum value which meets the condition; if CmIf there is data, store the data in C1In (1).
The sequential cyclic reading refers to reading from C1Starting to sequentially detect data, and if no data exists in the m memories, outputting a null frame; if Ck-1Medium (k 2, 3, … … m) no data, CkIf there is data, C is extractedkThe data of (1); if CmIf there is no data, C is extracted1The data of (1).
The invention provides data access devices, which comprises a computing unit, a data writing unit, a data storage unit and a data output unit, wherein the computing unit is responsible for collecting input original state data and computing the number m of required registers, the data writing unit is responsible for writing the data into the data storage unit according to a sequential cyclic writing method, the data storage unit comprises m registers which are as long as the stored data and are numbered in sequence, and the data output unit is responsible for outputting the data according to the sequential cyclic output method.
By applying the technical scheme of the invention, the beneficial effects are as follows:
1. the data access method and the data access device determine the number of the registers according to the data input characteristics, so that even though data terminals continuously receive data to be sent in multiple frames in a sending period, the data can be registered first to wait for sending of the next frames, and frame loss caused by data coverage is avoided.
2. The data access method and the data access device determine the minimum number of the registers according to the data input characteristics, so that the system can obtain the effect of no frame loss by using the minimum hardware resources.
3. The access logic can ensure that registers are not accessed simultaneously even if the reading and fetching times are coincident, thereby avoiding the condition of unsuccessful input and output.
Drawings
The accompanying drawings, which are included to provide a further understanding of embodiments of the invention , constitute a portion of this specification and are included to illustrate embodiments of the invention and together with the description to explain the principles of the invention.
FIG. 1 shows a timing diagram of access data; where nT (n ═ 0,1,2 … … 6) represents the actual time of data reading, and tn (n ═ 0,1,2 … … 6) represents the actual time of data input.
Fig. 2 shows a schematic diagram of a data access arrangement.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, but not all embodiments, the following description of at least exemplary embodiments is merely illustrative in nature and is in no way intended to limit the present invention and its application or use.
The devices are connected as shown in FIG. 2, and the external data is in accordance with the average period TinSending data to the measurement and control equipment, and outputting the data in a period Tout，Tout＝0.999Tin，ΔtinIs the maximum input error, and 0<Δtin≤ToutThe data frame length is l (bits).
The specific embodiment is as follows:
, calculating the number m of registers needed to be opened by the calculation unit according to the state of data input, calculating the positive integer
Then, in output cycles, 2 frames of data are input at most, and the number m of registers to be opened up is n +2 is 3.
The second step is that: three registers a, b, c of length L are opened up in the data storage unit.
And thirdly, using data _ ram [2:0] to represent the states of three registers of c, b and a, wherein data is 1, and no data is 0, according to the principle of sequential cyclic data storage, a data writing unit stores received data frames into three registers of a, b and c of a data storage unit in sequence, and updates data _ ram [2:0] after data storage, namely setting bits in data _ ram [2:0] corresponding to the registers with data to be 1, setting a truth table of storage logic as table 1, wherein tables 1 and 3 show that when the registers input two frames of data in periods, accurate reading can be completed, 3 frames of data are input in periods, the three registers are in a numbered state, the output sequence is disordered, registers need to be added to solve the problem, and the minimum number of registers needed is m + 2.
The fourth step: at the time of fetching, the data reading unit reads the data in the corresponding register according to the state of the data _ ram [2:0] and the principle of sequential cycle reading, after reading the data, the state position of the corresponding register is set to 0, the state of the data _ ram [2:0] is updated, and the fetching logic truth table is as shown in table 2.
Table 1 number-stored logic truth table
| Serial number | Data _ ram [2:0] before data storage] | Number stored in register | Data _ ram [2:0] after data storage] |
| 1 | 000 | a | 001 |
| 2 | 001 | b | 011 |
| 3 | 010 | c | 110 |
| 4 | 100 | a | 101 |
TABLE 2 access logic truth table
As shown in fig. 1, a further step is illustrated as follows:
at time t0, the computing unit receives external data, and according to the rule of sequential circular writing, the data writing unit stores the data in the register a, the data _ ram [2:0] state is updated to 001, at time 0, the data _ ram [2:0] state is inquired, the data output unit takes out the data in the register a, and the data _ ram [2:0] state is updated to 000.
At time T1, the computing unit receives external data, the data writing unit stores the data in register a, the data _ ram [2:0] state is updated to 001, at time T, the data _ ram [2:0] state is queried, the data output unit fetches the data in register a, and the data _ ram [2:0] state is updated to 000.
At the time of 2T, the data _ ram [2:0] state is inquired to be 000, the data output unit does not read any data from the register, an empty frame is sent, and the data _ ram [2:0] state is kept to be 000.
At time t2, the computing unit receives the external data, the data writing unit stores the data in the register a, the state of the data _ ram [2:0] is updated to 001, at time t3, the computing unit receives the next frames of external data, the data writing unit stores the external data in the register b according to the rule of sequential cyclic writing, and the data _ ram [2:0] is updated to 011.
At the time of 3T, no data is input, the data _ ram [2:0] state (011) is inquired, the data output unit takes out the data in the register a, and the data _ ram [2:0] state is updated to 010.
At time T4, the computing unit receives external data, and according to the rule of sequential cyclic writing, the data writing unit stores the data into the register c, the data _ ram [2:0] is updated to 110, and at time 4T, the data output unit reads the data in the register b according to the principle of sequential cyclic reading, and the data _ ram [2:0] is updated to 100.
At time 5T, the data output unit reads the data in the register c according to the state of the data _ ram [2:0], and transmits the data, and the data _ ram [2:0] is updated to 000 again.
Since the output period of the data is slightly less than the input period, the state machine can always restore the data _ ram [2:0] of the register to be in the state of 000 for a long enough time, thereby avoiding the situation that the output is blocked (i.e. the data _ ram [2:0] is always kept at 111).
In contrast, in the conventional data access method, data is stored in a register but cannot be read out in the order of the number of the data stored therein without optimization of the register, or the register is insufficient and cannot store data, thereby causing frame loss. As in the case shown in table 3.
TABLE 3 active number logic truth table
| Serial number | Data _ ram [2:0] before data storage] | Number stored in register | Data _ ram [2:0] after data storage] |
| 1 | 011 | c | 111 |
| 2 | 101 | b | 111 |
| 3 | 110 | a | 111 |
| 4 | 111 | a | 111 |
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1, kinds of data access method, characterized by that, including the following steps:
, confirming the data input characteristics including data length L and data input average period TinThe maximum transmission error of the sum data is Δ tin;
the second step is that: determining the number m of registers, wherein m is n +2, n is a positive integer
The third step: opening up m registers C with length Lm......C2、C1；
The fourth step: detecting register when receiving input dataThe storage state of the device is that data are circularly stored in m registers in sequence, and the stored register state is set as data; the sequential cyclic storage refers to the storage from C1Starting to sequentially detect data, and if no data exists in the m memories, storing the data in C1In, if CkIn which there is data, Ck+1If there is no data, store the data in Ck+1K is the minimum value which meets the condition; if CmIf there is data, store the data in C1Wherein k is 1,2, 3 … … m-1;
the fifth step: when outputting data, detecting the storage state of the register, reading the data in the register in sequence and circulation, and setting the read register state as no data. The sequential cyclic reading refers to reading from C1Starting to detect data sequentially, if no data exists in m memories, outputting a null frame, and if Cj-1Medium without data, CjIf there is data, C is extractedjThe data of (1); if CmIf there is no data, C is extracted1Wherein j is 2, 3, … … m.
2. The data access method of claim 1, wherein the maximum transmission error is a packet data actual input time Ti'nAnd average period T according to data inputinMaximum deviation of theoretical input time obtained by subtraction.
3. The data access method of claim 1, wherein the Δ t isinSatisfies (n-1) Tout<Δtin≤nToutT in the formulaoutFor data output period, ToutLess than the input period Tin。
4. The data access method of claim 3, wherein T isoutSatisfy ToutAnd TinThe difference is not more than 1% Tin。
The data access device is characterized by comprising a computing unit, a data writing unit, a data storage unit and a data output unit, wherein the computing unit is responsible for collecting input original state data and computing the number m of required registers, the data writing unit is responsible for writing the data into the data storage unit according to a sequential circulation data storage method, the data storage unit comprises m registers which are as long as the stored data and are numbered in sequence, and the data output unit is responsible for outputting the data according to the sequential circulation data output method.
6. The data access device of claim 5, wherein the computing unit computes the number m of registers by changing m to n +2, where n is a positive integer and
7. the data access device of claim 5, wherein the sequentially circulating write data of the data write unit is from C1Starting to sequentially detect data, and if no data exists in the m memories, storing the data in C1In, if CkIn which there is data, Ck+1If there is no data, store the data in Ck+1K is the minimum value which meets the condition; if CmIf there is data, store the data in C1Wherein k is 1,2, 3 … … m-1.
8. The data access device of claim 5, wherein the sequential round robin reading is from C1Starting to detect data sequentially, if no data exists in m memories, outputting a null frame, and if Cj-1Medium without data, CjIf there is data, C is extractedjThe data of (1); if CmIf there is no data, C is extracted1Wherein j is 2, 3, … … m.
9. The apparatus for data access according to claim 5, wherein the raw state data collected by the computing unit includes a data length L, a data input averaging period TinThe maximum transmission error of the data is Δ tin.
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