CN110736919A

CN110736919A - Method and test circuit for improving test coverage rate in SoC design

Info

Publication number: CN110736919A
Application number: CN201911022790.2A
Authority: CN
Inventors: 王宏伟; 张鹏; 段霆; 李湘锦
Original assignee: Shenzhen Union Memory Information System Co Ltd
Current assignee: Shenzhen Union Memory Information System Co Ltd
Priority date: 2019-10-25
Filing date: 2019-10-25
Publication date: 2020-01-31

Abstract

The application relates to a method for improving test coverage in SoC design and a test circuit, wherein the test circuit comprises a simulation module, a plurality of drain type logic modules, an XOR module, a DFF circuit, a plurality of MUX circuits, a plurality of source type logic modules and a plurality of source type logic modules, wherein the output ends of the drain type logic modules are electrically connected with the input end of the simulation module, the XOR module is electrically connected with the output ends of the drain type logic modules, the input end of the DFF circuit is electrically connected with the output end of the XOR module, the B ends of the MUX circuits are electrically connected with the output end of the DFF circuit, the A ends of the MUX circuits are electrically connected with the output end of the simulation module, and the source type logic modules are electrically connected with the output ends of the MUX circuits.

Description

Method and test circuit for improving test coverage rate in SoC design

Technical Field

The invention relates to the technical field of integrated circuit design, in particular to methods for improving test coverage in SoC design and a test circuit.

Background

At present, during SoC DFT design, an analog circuit module is usually treated as a black box, and specifically, a related digital control logic "sink" signal is input to the analog module; or the output signals of the analog module, which are the "source" signals from the analog module, to subsequent digital logic.

In the conventional technology, the phenomenon generates two problems of test coverage rate reduction, namely test coverage rate reduction caused by the fact that the relevant control logic change of a sink signal cannot be conducted to an output pad, test coverage rate reduction caused by the fact that the logic quantity of subsequent logic which cannot be tested is increased due to the fact that a source signal output to the subsequent logic is in an unstable state 'x', and if a test coverage rate target is set, the test vector quantity is increased, the test time length is prolonged, and the chip cost is increased.

Disclosure of Invention

In view of the above, it is necessary to provide methods and test circuits for improving test coverage in SoC design.

A test circuit for improving test coverage in a SoC design, the test circuit comprising:

a simulation module comprising a plurality of inputs and a plurality of outputs;

the output ends of the plurality of drain type logic modules are electrically connected with the input end of the analog module;

the exclusive OR module is respectively electrically connected with the output ends of the plurality of drain type logic modules and is used for carrying out exclusive OR processing on the output signals of the plurality of drain type logic modules;

a DFF circuit having an input electrically connected to an output of the XOR module for breaking a potential long-sequence path;

the B ends of the MUX circuits are respectively and electrically connected with the output end of the DFF circuit, and the A ends of the MUX circuits are respectively and electrically connected with the output end of the analog module;

and the source type logic modules are respectively and electrically connected with the output ends of the MUX circuits.

In embodiments, the S terminals of the MUX circuits respectively input an SCEN signal, wherein the SCEN signal is high only in the SCAN mode and low in other modes.

In embodiments, the drain logic modules include a drain logic module, a second drain logic module, a third drain logic module, and a fourth drain logic module, and are electrically connected to the in1, in2, in3, and in4 inputs of the analog module, respectively.

In embodiments, the XOR module comprises a XOR 0, a second XOR 1, and a third XOR , the XOR is electrically connected to the drain logic module and the second drain logic module output, respectively, the second XOR is electrically connected to the third drain logic module and the fourth drain logic module output, and the third XOR is electrically connected to the second XOR and the second XOR output, respectively.

In embodiments, the xor is used to xor the signals output by the th drain logic block and the second drain logic block, and the second xor is used to xor the signals output by the third drain logic block and the fourth drain logic block.

In of these embodiments, the output of the third exception or is electrically connected to the input of the DFF circuit.

In embodiments, the plurality of MUX circuits includes a MUX circuit and a second MUX circuit, wherein the A terminals of the MUX circuit and the second MUX circuit are electrically connected with the out1 and out2 outputs of the analog module, respectively.

In embodiments, the terminals B of the MUX circuit and the second MUX circuit are electrically connected with the output terminal of the DFF circuit respectively.

A method for improving test coverage in a SoC design, the method applied to the test circuit for improving test coverage in a SoC design described in any of above, the method comprising:

adding related redundant logic in the process of generating the DFT netlist;

generating a test vector after the relevant redundant logic is added;

judging whether the test coverage rate reaches the standard or not;

and if the test coverage rate reaches the standard, carrying out simulation verification, and if the test coverage rate does not reach the standard, re-executing the step of generating the DFT netlist.

In embodiments, the step of adding relevant redundancy logic in the process of generating the DFT netlist further comprises:

after the output signal of the leakage type logic module is subjected to exclusive OR processing, a potential long time sequence path is broken through a DFF circuit;

bypassing the output signal of the analog module through the MUX circuit;

the output signal from the DFF is received through the B terminal of the MUX circuit.

According to the method and the test circuit for improving the test coverage in the SoC design, the test coverage is improved by adding a small amount of test logic through a hardware circuit. In the subsequent test vector generation process, the comparison shows that: after the relevant redundant logic is added, the test coverage rate is greatly improved compared with the prior art, and the test vectors required for reaching the same coverage rate target are reduced. The invention realizes the purposes of improving the test coverage rate and the test efficiency, reducing the cost of mass production of chips and improving the market competitiveness of products.

Drawings

FIG. 1 is a circuit diagram of control logic of an analog module according to the prior art;

FIG. 2 is a circuit diagram of test circuitry for improving test coverage in SoC designs in embodiments;

FIG. 3 is a flow chart illustrating a method for improving test coverage in SoC designs in embodiments;

fig. 4 is a flow chart illustrating a method for improving test coverage in SoC design in another embodiments.

Detailed Description

For purposes of making the present application more readily apparent, the technical solutions and advantages thereof, reference is now made to the following detailed description taken in conjunction with the accompanying drawings and examples, it being understood that the specific examples described herein are for purposes of illustration only and are not intended to limit the application.

During SoC DFT design, the analog circuit module will be treated as a black box: the input of the relevant digital control logic sink to the analog module; or the output signals of the analog module, which are the "source" signals from the analog module, to subsequent digital logic.

The phenomenon causes two problems of test coverage rate reduction, namely test coverage rate reduction caused by the fact that the relevant control logic change of a sink signal cannot be conducted to an output pad, test coverage rate reduction caused by the fact that the logic quantity of follow-up logic which is not testable is increased due to the fact that the source signal output to the follow-up logic is in an unstable state x, and if a test coverage rate target is set, the test direction quantity is increased, the test time length is prolonged, and the chip cost is increased.

In the prior art, the original functional connections are usually kept unprocessed, and the negative influence of the logic on the test vectors is ignored. The original circuit structure is shown in figure 1: the method of no processing on the circuit can cause that the change of the SinkLogic 1-4 can not be transmitted to the chip pins, and the test coverage rate is reduced; the inputs of sources 1-2 are derived from the output signals of the analog modules, and the black box considers these outputs to be "x" states, and the tool should try to filter these "x" states in the subsequent logic when generating vectors, so that the number of test vectors increases.

Based on the defects in the prior art, the invention provides design methods of SoC DFT, which are methods for improving test coverage and optimizing circuit time sequence by adding related redundant logic.

In embodiments, test circuits for improving test coverage in a SoC design are provided, the test circuits comprising:

the simulation module comprises a plurality of input ends and a plurality of output ends;

the input end of the DFF circuit is electrically connected with the output end of the XOR module and is used for breaking a potential long-time sequence path;

A circuit diagram of a test circuit for improving test coverage in an SoC design is shown in conjunction with fig. 2. In the present embodiment, the stress and workload of the subsequent layout and wiring are optimized in consideration of making the logic, which is not testable, become testable while shortening the long timing path. Structure of circuit implementation referring to fig. 2, non-testable logic is made testable by adding redundant test logic.

Specifically, a design strategy of adding test logic is realized through the circuit, after signals in 1-in 4 from a sink to a module are subjected to exclusive OR processing, DFF is added to break a potential long-time-sequence path, and therefore time sequence optimization pressure of back-end design can be relieved. The output signal of the analog module is bypassed by using a MUX circuit, and the output signal from the sink DFF is received by a MUX B terminal.

In this embodiment, test coverage is improved by adding a small amount of test logic. In the subsequent test vector generation process, the comparison shows that: after the relevant redundant logic is added, the test coverage rate is greatly improved compared with the prior art, and the test vectors required for reaching the same coverage rate target are reduced. The invention realizes the purposes of improving the test coverage rate and the test efficiency, reducing the cost of mass production of chips and improving the market competitiveness of products.

In embodiments, the S terminals of the MUX circuits respectively input the SCEN signal, wherein the SCEN signal is high only in SCAN mode and low in other modes.

In particular, referring to the circuit diagram shown in fig. 2, the select terminal S of the MUX is from scan enable, which is a high level only in scan mode, and selects the data stream of the lower B terminal, thereby increasing the test coverage of the logic. And low in other modes, the data stream comes from the A end of the MUX. Analysis shows that the design method does not have any influence on the logic in the functional mode.

In the embodiment, under the scan mode, the original untestable analog module control logic can ideally participate in the generation of the test vectors, and under the constraint condition of the test coverage determined by , the target is reached by using less test vectors, so that the test efficiency is improved.

In embodiments, the XOR block includes a th XOR 0, a second XOR 1 and a third XOR , the th XOR is electrically connected to the th drain logic block and the second drain logic block output, respectively, the second XOR is electrically connected to the third drain logic block and the fourth drain logic block output, and the third XOR is electrically connected to the second XOR and the second XOR output, respectively.

In embodiments, the output of the third exception or is electrically connected to the input of the DFF circuit.

In embodiments, the plurality of MUX circuits includes a MUX circuit and a second MUX circuit, wherein the a terminals of the MUX circuit and the second MUX circuit are electrically connected to the out1 and out2 outputs of the analog block, respectively.

In embodiments, the terminals B of the MUX circuit and the second MUX circuit are electrically connected to the output terminal of the DFF circuit, respectively.

The specific circuit connection relationship can be seen in fig. 2, and in the above embodiment, the technical effects achieved at least include:

1. the pure hardware scheme is high in speed, and the test coverage rate and the test efficiency are improved.

2. The final ATE test vectors of the chip are reduced, the test time is shortened, and the cost is saved.

3. And meanwhile, logic sink and logic source are considered, and the implementation logic of the circuit is reduced.

4. The timing problem in the back-end layout and wiring process is not influenced and even improved.

5. The circuit is low in implementation difficulty and easy to implement.

In embodiments, as shown in fig. 3, methods for improving test coverage in SoC design are provided, and the methods are applied to a test circuit for improving test coverage in SoC design in any embodiments, including:

step 302, adding related redundancy logic in the process of generating the DFT netlist;

step 304, generating a test vector after the relevant redundant logic is added;

step 306, judging whether the test coverage rate reaches the standard;

and 308, if the test coverage rate reaches the standard, performing simulation verification, and if the test coverage rate does not reach the standard, re-executing the step of generating the DFT netlist.

In the present embodiment, methods for improving test coverage in SoC design are provided, which may be applied to the circuit shown in fig. 2, and specific circuit descriptions refer to the above embodiments.

For example, specific designs, 1100+ test vectors are required for the original design to reach the 98% test coverage target, and after the redundant test logic is added by the method proposed in this embodiment, about 860 test vectors are required for the original set 98% test coverage target, and the test time is optimized to in fifths.

In embodiments, as shown in fig. 4, methods for improving test coverage in SoC designs are provided, in which the step of adding relevant redundancy logic in the process of generating DFT netlist further includes:

step 402, after the output signal of the drain type logic module is subjected to exclusive OR processing, a potential long time sequence path is broken through a DFF circuit;

step 404, bypassing the output signal of the analog module through the MUX circuit;

at step 406, the output signal from the DFF is received through the B terminal of the MUX circuit.

It should be understood that although the various steps in the flow charts of fig. 3-4 are shown in sequence as indicated by the arrows, the steps are not necessarily performed in the order indicated by the arrows, unless explicitly stated herein, the steps may be performed in other sequences without strict order limitations, and further, at least the portion of the step of in fig. 3-4 may include multiple sub-steps or stages that are not necessarily performed at the same time , but may be performed at different times, the order of performance of the sub-steps or stages may not necessarily be performed in sequence, but may be rotated or alternated with at least portions of other steps or sub-steps or stages of other steps.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1, A test circuit for improving test coverage in an SoC design, the test circuit comprising:

2. The test circuit for improving test coverage in an SoC design according to claim 1, wherein S terminals of the plurality of MUX circuits respectively input a SCEN signal, wherein the SCEN signal is high only in SCAN mode and low in other modes.

3. The test circuit of claim 2, wherein the plurality of drain logic blocks comprises th drain logic block, a second drain logic block, a third drain logic block, and a fourth drain logic block, and is electrically connected to the in1, in2, in3, and in4 inputs of the simulation block, respectively.

4. The test circuit of claim 3, wherein the XOR modules comprise XOR , a second XOR 0, and a third XOR , wherein the XOR is electrically connected to the drain logic module and the second drain logic module output respectively, the second XOR is electrically connected to the third drain logic module and the fourth drain logic module output respectively, and the third XOR is electrically connected to the second XOR and the second XOR output respectively.

5. The test circuit of claim 4, wherein the XOR is configured to XOR signals output by the th drain logic block and the second drain logic block, and XOR signals output by the second XOR the third drain logic block and the fourth drain logic block.

6. The test circuit for improving test coverage in an SoC design of claim 5, wherein an output of the third exception is electrically connected to an input of the DFF circuit.

7. The test circuit of claim 6, wherein the plurality of MUX circuits includes -th MUX circuit and a second MUX circuit, wherein A terminals of the -th MUX circuit and the second MUX circuit are electrically connected to out1 and out2 outputs of the analog block, respectively.

8. The test circuit of claim 7, wherein the terminals B of the MUX circuit and the second MUX circuit are electrically connected to the output terminal of the DFF circuit respectively.

A method of for improving test coverage in SoC designs, wherein the method is applied to the test circuit of any of claims 1-8 through for improving test coverage in SoC designs, the method comprising:

adding related redundant logic in the process of generating the DFT netlist;

generating a test vector after the relevant redundant logic is added;

judging whether the test coverage rate reaches the standard or not;

10. The method for improving test coverage in an SoC design of claim 9, wherein the step of adding relevant redundancy logic in generating the DFT netlist further comprises:

bypassing the output signal of the analog module through the MUX circuit;