CN110729998A - Wideband Injection Locked Frequency Divider Based on Distributed Injection and Transformer - Google Patents

Abstract

The invention discloses a broadband injection locking frequency divider based on distributed injection and transformer: No. 1 cross-coupling pipe, No. 2 cross-coupling pipe, No. 1 nMOS injection pipe, No. 1 pMOS injection pipe, No. 2 nMOS injection pipe, No. 2 pMOS injection tube, current source tube, pMOS output tube, No. 1 transmission line, No. 2 transmission line, No. 3 transmission line, No. 4 transmission line, No. 1 output buffer, No. 2 output buffer, No. 1 transformer and No. 2 transformer, No. 1 transformer includes No. 1 primary coil, No. 1 secondary coil, No. 1 tertiary coil, No. 1 transformer capacitor, No. 2 transformer includes No. 2 primary coil, No. 2 secondary coil, No. 2 tertiary coil, No. 2 transformer capacitors. The invention can realize a wider locking range, and achieves better overall performance in terms of phase noise, power consumption, output power, etc., and has a better application prospect.

Description

Wideband Injection Locked Frequency Divider Based on Distributed Injection and Transformer

technical field

The invention relates to the field of microwave engineering, and more particularly, to a broadband injection-locked frequency divider based on distributed injection and transformer.

Background technique

As one of the key modules in the phase-locked loop system, the frequency divider will directly affect the quality of the signal source and the overall performance of the transceiver system. While realizing the frequency division function, we must comprehensively consider the performance indicators such as the locking range, power consumption, phase noise, output power and chip area of the frequency divider. Frequency dividers can be divided into static frequency dividers, regenerative frequency dividers and injection-locked frequency dividers. Among them, injection-locked dividers have received continuous attention due to their high operating frequency and low power consumption. In a phase-locked loop system, the locking range of the injection-locked divider needs to cover the output frequency range of the VCO. In order to avoid the influence caused by process deviation and ensure the good performance of the phase-locked loop system, achieving a wide locking range has become the main challenge in designing an injection-locked frequency divider.

Currently, a variety of techniques that can extend the locking range have been used in the design of injection-locked dividers. In 2013, Yue Chao and Howard C. Luong proposed a frequency tracking method, which can increase the injection efficiency of the injection tube and improve the locking range [1]. In 2016, Sheng Lyang Jang et al. used a third-order resonator to reduce the quality factor of the divider resonator, thereby improving the locking range [2]. In 2017, Alireza Imani and Hossein Hashemi proposed a distributed injection method, which uses the energy injected by multiple nodes to make the frequency divider complete the frequency division function at more resonance points and improve the bandwidth [3]. However, the existing methods above have a limited effect on improving the locking range, and fail to achieve an optimal compromise between various indicators, and cannot meet the system's strict requirements for an injection-locked frequency divider.

Therefore, how to better expand the locking range has become a key issue in the design of injection-locked dividers.

【references】

[1] Y.Chao and H.C.Luong, "Analysis and Design of a 2.9-mW 53.4–79.4-GHz Frequency-Tracking Injection-Locked Frequency Divider in 65-nm CMOS," IEEEJ.Solid-State Circuits,vol.48, no.10, pp.2403–2418, Oct.2013.

[2] S.L.Jang et al. "Triple-Resonance RLC-Tank Divide-By-2Injection-Locked Frequency Divider", Electronics Letters, vol.52, no.8, pp.624-626, April 2016.

[3] Alireza Imani and Hossein Hashemi, "Distributed Injection-LockedFrequency Dividers", IEEE J.Solid-State Circuits.vol.52.no.8.pp.2083-2093.August 2017.

SUMMARY OF THE INVENTION

Based on the above requirements, the present invention proposes a broadband injection-locked frequency divider based on distributed injection and transformer, which can achieve a wider locking range and achieve a better overall performance in terms of phase noise, power consumption, and output power. performance, has a good application prospect.

The object of the present invention is achieved through the following technical solutions.

The invention is based on a broadband injection-locked frequency divider based on distributed injection and transformer, and includes a No. 1 transformer and a No. 2 transformer. One end of the No. 1 primary coil of the No. 1 transformer is grounded, and the other end is connected to the input end of the No. 1 output buffer; One end of the No. 1 secondary coil of the No. 1 transformer is connected to the voltage source, and the other end is connected to the No. 1 tertiary coil, and is respectively connected to the drains of the No. 2 nMOS injection tube and the No. 2 pMOS injection tube; the No. 1 One end of the No. 1 tertiary coil of the transformer is connected to the No. 1 secondary coil, and the other end is connected to the drain of the No. 1 cross-coupling tube, the gate of the No. 2 cross-coupling tube, the drain of the No. 1 nMOS injection tube, and the No. 1 pMOS injection tube. drain;

One end of the No. 2 primary coil of the No. 2 transformer is grounded, and the other end is connected to the input end of the No. 2 output buffer; one end of the No. 2 secondary coil of the No. 2 transformer is connected to the voltage source, and the other end is connected to the No. 2 third stage The coils are connected and connected respectively to the sources of the No. 2 nMOS injection tube and the No. 2 pMOS injection tube; one end of the No. 2 tertiary coil of the No. 2 transformer is connected to the No. 2 secondary coil, and the other end is respectively connected to the No. 1 crossover The gate of the coupling tube, the drain of the No. 2 cross-coupling tube, the source of the No. 1 nMOS injection tube, and the source of the No. 1 pMOS injection tube;

The source of the No. 1 cross-coupling tube and the source of the No. 2 cross-coupling tube are both connected to the drain of the current source tube, the source of the current source tube is grounded, and the gate of the current source tube is input with a control voltage; the No. 1 nMOS The gate of the injection tube is connected to the negative terminal of the input signal through the No. 3 transmission line; the gate of the No. 2 nMOS injection tube is connected to the negative terminal of the input signal through the No. 4 transmission line and the No. 3 transmission line in turn; the gate of the No. 1 pMOS injection tube The positive terminal of the input signal is connected through the No. 1 transmission line; the gate of the No. 2 pMOS injection tube is connected to the positive terminal of the input signal through the No. 2 transmission line and the No. 1 transmission line in turn.

The circuit structures of the No. 1 output buffer and No. 2 output buffer are the same, and both include a pMOS output tube. The source of the pMOS output tube is grounded, the gate is used as the input end of the output buffer, and the drain is connected to the inductance and harmonics respectively. Short-circuit capacitor and output capacitor; one end of the inductor is connected to the drain of the pMOS output tube, the other end is respectively connected to the bypass capacitor and the voltage source, one end of the bypass capacitor is connected to the inductor, and the other end is grounded; one end of the harmonic short-circuit capacitor is connected to the pMOS The drain of the output tube is connected to the drain of the output tube, and the other end is grounded; one end of the output capacitor is connected to the drain of the pMOS output tube, and the other end is used as the output end of the output buffer.

Compared with the prior art, the beneficial effects brought by the technical solution of the present invention are:

(1) The topology of the present invention utilizes distributed injection to generate multi-segment locking ranges intersecting with each other at multiple resonance points to form an overall wide locking range effect. In addition, the adopted fourth-order resonator further extends the locking range.

(2) The topology of the present invention adopts the peaking inductance technology, which increases the impedance peak value of the resonant cavity at the resonance point and reduces the power consumption of the circuit. And by optimizing the parameters of components such as transformers, injection tubes, and cross-coupling tubes, better overall performance can be achieved in terms of power consumption and output power.

(3) The topological structure of the present invention is simple, and the integration is convenient.

Description of drawings

1 is a schematic diagram of a broadband injection-locked frequency divider based on distributed injection and a transformer of the present invention;

Figure 2 is a schematic diagram of the output buffer;

FIG. 3 is a schematic diagram of the simulation result of the output sensitivity curve.

Reference signs: M ₁ No. 1 cross-coupling pipe, M ₂ No. 2 cross-coupling pipe, M ₃ No. 1 nMOS injection pipe, M ₄ No. 1 pMOS injection pipe, M ₅ No. 2 nMOS injection pipe, M ₆ No. 2 pMOS injection pipe tube, M ₇ current source tube, M ₈ pMOS output tube, TL ₁ No. 1 transmission line, TL ₂ No. 2 transmission line, TL ₃ No. 3 transmission line, TL ₄ No. 4 transmission line, L ₁ No. 1 primary coil, L ₂ No. 1 time Primary coil, L ₃ No. 1 tertiary coil, L ₄ No. 2 primary coil, L ₅ No. 2 secondary coil, L ₆ No. 2 tertiary coil, C _t1 No. 1 transformer capacitor, C _t2 No. 2 transformer capacitor, Buffer1 No. 1 output buffer, Buffer2 No. 2 output buffer, L _b inductor, C ₁ bypass capacitor, C ₂ harmonic short-circuit capacitor, C _out output capacitor.

Detailed ways

In order to illustrate the technical solutions of the present invention more clearly, the present invention is further described below with reference to the accompanying drawings.

The invention proposes a broadband injection-locked frequency divider based on distributed injection and transformer. This topology consists of cross-coupled tubes, transformers and output buffers. This topology adopts the distributed differential injection method to enhance the injection current and injection efficiency, and uses a high-order transformer as a resonant cavity, which effectively increases the locking of the frequency divider without using a variable capacitor tube for tuning. range, and reduces the number of control voltages, simplifying operation. At the same time, the design of the high-order transformer incorporates peaking inductance technology to reduce the power consumption of the circuit. In addition, the structure of the traditional buffer has been improved to enhance the harmonic suppression capability and maintain a wide locking range.

The injection locking frequency divider of LC structure can use the formula (1) to express the relation between its locking range and circuit parameters.

Among them, Q is the quality factor of the resonant cavity, f _center is the self-resonant frequency of the frequency divider, η is the injection efficiency of the injection tube, I _inj is the injection current, and I _osc is the DC current of the frequency divider circuit. It can be seen that in order to expand the locking range of the frequency divider, it is necessary to increase the injection efficiency η and reduce the quality factor Q of the resonator. However, in order to ensure the gain condition of the frequency divider and make it work stably, the Q value needs to be large enough, otherwise the power consumption of the circuit will increase significantly. The topology proposed by the invention can effectively improve the injection efficiency η of the injection pipe, and by selecting an appropriate quality factor Q of the resonant cavity, a better overall performance of the frequency divider can be achieved.

As shown in FIG. 1 , the present invention is a broadband injection-locked frequency divider based on distributed injection and transformer, including a No. 1 transformer and a No. 2 transformer. The No. 1 transformer includes a No. 1 primary coil L ₁ and a No. 1 secondary coil L _2. No. 1 tertiary coil L ₃ , No. 1 transformer capacitor C _t1 , both ends of the No. 1 transformer capacitor C _t1 are respectively connected to both ends of No. 1 primary coil L ₁ ; the No. 2 transformer includes No. 2 primary coil L ₄ , No. 2 secondary coil L ₅ , No. 2 tertiary coil L ₆ , No. 2 transformer capacitor C _t2 , both ends of No. 2 transformer capacitor C _t2 are respectively connected to both ends of No. 2 primary coil L ₄ .

One end of the No. 1 primary coil L1 of the No. ₁ transformer is grounded, and the other end is connected to the input end of the No. 1 output buffer Buffer1; one end of the No. 1 secondary coil L2 of the No. ₁ transformer is connected to the voltage source V _DD , and the other end is connected to the voltage source V DD. One end is connected to the No. ₁ tertiary coil L3, and is respectively connected to the drains of the No. 2 nMOS injection tube _M5 and the No. 2 pMOS injection tube _M6 ; one end of the No. 1 tertiary coil L3 of the No. ₁ transformer is connected to No. 1 secondary coil L ₂ is connected, and the other end is respectively connected to the drain of No. 1 cross-coupling transistor M ₁ , the gate of No. 2 cross-coupling transistor M ₂ , the drain of No. 1 nMOS injection tube M ₃ , and the No. 1 pMOS injection tube M ₄ drain.

One end of the No. 2 primary coil L4 of the No. 2 transformer is grounded, and the other end is connected to the input end of the No. ₂ output buffer Buffer2. One end of the No. 2 secondary coil L5 of the No. 2 transformer is connected to the voltage source V _DD , and the other end is connected to the No. _{2 tertiary coil connection L 6 ,} and is respectively connected to the No. 2 nMOS injection tube M ₅ and the No. 2 pMOS injection tube. source of tube _M6 . One end of the No. 2 tertiary coil L3 of the No. 2 transformer is connected to the No. _{2 secondary coil L 5 ,} and the other end is respectively connected to the grid of the No. ₁ cross-coupling tube M1, the drain of the No. ₂ cross-coupling tube M2, and the No. ₁ nMOS injection pipe M3 source, No. ₁ pMOS injection pipe M4 source.

The source of the No. ₁ cross-coupling transistor M1 and the source of the No. ₂ cross _- coupling transistor M2 are both connected to the drain of the current source tube M7, the source of the current source tube _M7 is grounded, and the gate of the current source tube _M7 The control voltage V _B outside the chip is input to the pole. The gate of the No. 1 nMOS injection tube M ₃ is connected to the negative terminal V _inj − of the input signal through the No. 3 transmission line connected to TL ₃ . The gate of the No. 2 nMOS injection tube M ₅ is sequentially connected to the negative terminal V _inj − of the input signal through the No. 4 transmission line TL ₄ and the No. 3 transmission line TL ₃ . _The gate of the No. 1 pMOS injection tube M4 is connected to the forward terminal V _inj + of the input signal through the No. 1 transmission line TL ₁ . The gate of the No. 2 pMOS injection tube M ₆ is sequentially connected to the forward terminal V _inj + of the input signal through the No. 2 transmission line TL ₂ and the No. 1 transmission line TL ₁ .

As shown in FIG. 2 , the No. 1 output buffer Buffer1 and No. 2 output buffer Buffer2 have the same circuit structure, including a pMOS output transistor M ₈ , the source of the pMOS output transistor M ₈ is grounded, and the gate is used as an output buffer The input end of the device is connected to the drain of the inductor L _b , the harmonic short-circuit capacitor C ₂ , and the output capacitor C _out , respectively. One end of the inductor L _b is connected to the drain of the pMOS output transistor M ₈ , and the other end is connected to the bypass capacitor C ₁ and the voltage source V _DD respectively. One end of the bypass capacitor C ₁ is connected to the inductor L _b and the other end is grounded. One end of the harmonic short-circuit capacitor _C2 is connected to the drain of the pMOS output transistor _M8 , and the other end is grounded. One end of the output capacitor C _out is connected to the drain of the pMOS output transistor M ₈ , and the other end is used as the output end of the output buffer.

The source of the No. ₁ cross-coupling tube M1 and the No. 2 cross-coupling tube M ₂ provide negative resistance for the frequency divider circuit when it is turned on, compensating for the loss of the resonant cavity. No. 1 nMOS injection pipe M ₃ , No. 1 pMOS injection pipe M ₄ , No. 2 nMOS injection pipe M ₅ , No. 2 pMOS injection pipe M ₆ , which are equivalent to mixers, and combine the injected double frequency signal with the fundamental frequency feedback signal Mixing, so as to get the base frequency output, complete the frequency division function. In this topology, the No. 1 nMOS injection pipe M ₃ , the No. 1 pMOS injection pipe M ₄ , the No. 2 nMOS injection pipe M ₅ , and the No. 2 pMOS injection pipe M ₆ are two pairs of injection pipes connecting the source and drain of the nMOS and the pMOS respectively. While realizing the differential injection, the transconductance is enhanced, the injection efficiency is improved, the size of the overall parasitic capacitance is reduced, and the locking range of the frequency divider is improved. The transformer adopts the combination of coaxial coupling and vertical coupling to reduce the parasitic capacitance of the transformer, and at the same time, the coupling coefficients between L ₁ L ₂ L ₃ , L ₄ L ₅ L ₆ are almost equal. The No. 1 transformer capacitor C _t1 and the No. 2 transformer capacitor C _t2 are used to adjust the parameters of the transformer. Finally, the output signal is coupled to the input end of the buffer by the transformer, and output to the next-stage frequency divider.

The frequency divider proposed by the invention adopts a fourth-order resonant cavity, which reduces the phase shift of the resonant cavity, and is more favorable for the frequency divider to satisfy the phase condition of injection locking. The phase response curve of the traditional second-order LC resonator has a large slope at the center frequency point, which makes the phase shift of the resonator in a wide frequency band too large, and it is difficult to be compensated by the phase shift provided by the injection tube, resulting in the frequency divider. The locking range becomes smaller. Although the impedance of the second-order LC resonator is larger at the center frequency, which can fully satisfy the gain condition, the steeper phase response curve cannot satisfy the phase condition in a wider bandwidth, and the overall locking range is narrow. To improve this situation, this topology uses a fourth-order LC resonator to effectively extend the locking range. The impedance of the fourth-order LC resonator presents two adjacent peaks, and its phase response presents a corrugated flat curve near 0°, which can satisfy the gain and phase conditions of the frequency divider injection locking in a wider bandwidth. .

In order to further expand the locking range, this topology adopts the method of distributed injection, and increases the locking range by increasing iinj. The traditional injection locking frequency divider has only one resonance point, the injection current is independent of the frequency, and the locking range is limited. The distributed injection method can enhance the injection current, which can make the frequency divider meet the start-up conditions at multiple resonance points, so the locking range and the injection power required by the frequency divider are improved. The size of the injection current of the distributed injection is related to the frequency ω. When the frequency is greater than the first resonance point, the injection current gradually increases and is larger than the current size of the traditional structure. The number of injection stages is proportional to the locking range, but for this topology, two-stage distributed injection is selected for the consideration of chip area, which can achieve a wider locking range. By carefully selecting the size of the injection tubes M ₃ to M ₆ and the inductance values of L ₂ and L ₃ , the injection currents of the two stages are superimposed forward. Therefore, the injection current in the frequency band above the self-resonant frequency of the frequency divider is enhanced, which effectively enhances the energy injected into the frequency divider, increases the highest frequency dividing frequency, and expands the locking range.

In addition to distributed injection, this topology also uses differential injection, in the form of interconnecting the source and drain of nMOS and pMOS, which enhances the transconductance of the injection tube, increases the injection current, and reduces the overall parasitic capacitance. The locking range of the frequency converter has been improved. At the same time, the differential injection tube is easy to connect with the differential output of the VCO.

The output buffer of the present invention adopts the harmonic suppression technology. The injection-locked frequency divider is used as the first-stage frequency divider of the phase-locked loop, and the fundamental wave of the output signal should be greater than its harmonics. In the output buffer shown in FIG. 2 , the inductor L _b and the bypass capacitor C ₁ are used to bias the pMOS output transistor M8 . In order to filter out the harmonics, the inductance value of L _b is often larger, otherwise the harmonic size will be larger than the fundamental wave, resulting in poor signal quality and narrowing of the locking range. But L _b takes up too much chip area. Therefore, the present invention re-introduces the harmonic short-circuit capacitor C ₂ into the bias network, so that the bias network becomes the AC ground for the second and third harmonics, thereby achieving the effect of suppressing the harmonics. Through simulation comparison, this buffer structure can increase the power ratio of the fundamental wave to the second harmonic by 10.91dB.

As shown in FIG. 3 , the simulation verifies that the present invention can achieve a locking range of 22.8-36.3 GHz (45.7%) under 0dBm injection power, and the power consumption is 3.54 mW, achieving a wider locking range and better overall performance.

Although the functions and working process of the present invention have been described above in conjunction with the accompanying drawings, the present invention is not limited to the above-mentioned specific functions and working processes. Under the inspiration of the present invention, those of ordinary skill in the art can also make many forms without departing from the scope of the present invention and the protection scope of the claims, which all belong to the protection of the present invention.

Claims (2)

1. A broadband injection-locked frequency divider based on distributed injection and transformer, comprising No. 1 transformer and No. 2 transformer, it is characterized in that, one end of the No. 1 primary coil (L ₁ ) of the No. 1 transformer is grounded, and the other end is grounded. Connect the input end of the No. 1 output buffer (Buffer1); one end of the No. 1 secondary coil (L ₂ ) of the No. 1 transformer is connected to the voltage source (V _DD ), and the other end is connected to the No. 1 tertiary coil (L _{3 )} ) is connected, and the drains of the No. 2 nMOS injection tube (M ₅ ) and the No. 2 pMOS injection tube (M ₆ ) are respectively connected; one end of the No. 1 tertiary coil (L ₃ ) of the No. 1 transformer is connected to the No. The stage coil (L ₂ ) is connected, and the other end is respectively connected to the drain of the No. 1 cross-coupling tube (M ₁ ), the gate of the No. 2 cross-coupling tube (M ₂ ), the drain of the No. 1 nMOS injection tube (M ₃ ), and the drain of the No. 1 nMOS injection tube (M 3 ). pMOS injection tube (M ₄ ) drain; One end of the No. 2 primary coil (L ₄ ) of the No. 2 transformer is grounded, and the other end is connected to the input end of the No. 2 output buffer (Buffer2); one end of the No. 2 secondary coil (L ₅ ) of the No. 2 transformer is connected to the voltage The source (V _DD ) is connected, the other end is connected to the No. 2 tertiary coil connection (L ₆ ), and the sources of the No. 2 nMOS injection tube (M ₅ ) and the No. 2 pMOS injection tube (M ₆ ) are respectively connected; One end of the No. 2 tertiary coil (L ₃ ) of the No. 2 transformer is connected to the No. 2 secondary coil (L ₅ ), and the other end is respectively connected to the grid of the No. 1 cross-coupling tube (M ₁ ) and the No. 2 cross-coupling tube ( M ₂ ) drain, No. 1 nMOS injection tube (M ₃ ) source, and No. 1 pMOS injection tube (M ₄ ) source; The source of the No. 1 cross-coupling tube (M ₁ ) and the source of the No. 2 cross-coupling tube (M ₂ ) are both connected to the drain of the current source tube (M ₇ ), and the source of the current source tube (M ₇ ) is grounded, The gate of the current source tube (M ₇ ) is input with the control voltage (V _B ); the gate of the No. 1 nMOS injection tube (M ₃ ) is connected to the negative terminal (V _inj ) of the input signal through the No. 3 transmission line (TL ₃ ). -); the gate of the No. 2 nMOS injection tube (M ₅ ) is connected to the negative terminal (V _inj -) of the input signal through the No. 4 transmission line (TL ₄ ) and the No. 3 transmission line (TL ₃ ) in turn; the No. 1 pMOS The gate of the injection tube (M ₄ ) is connected to the forward terminal (V _inj + ) of the input signal through the No. 1 transmission line (TL ₁ ); the gate of the No. 2 pMOS injection tube (M ₆ ) is sequentially connected to the No. 2 transmission line (TL ₂ ) . The No. 1 transmission line (TL ₁ ) is connected to the forward end (V _inj + ) of the input signal. 2. The broadband injection-locked frequency divider based on distributed injection and transformer according to claim 1, wherein the circuit structures of the No. 1 output buffer (Buffer1) and the No. 2 output buffer (Buffer2) are the same , all include a pMOS output transistor (M ₈ ), the source of the pMOS output transistor (M ₈ ) is grounded, the gate is used as the input end of the output buffer, and the drain is connected to the inductor (L _b ), the harmonic short-circuit capacitor (C ₂ ). ), output capacitor (C _out ); one end of the inductor (L _b ) is connected to the drain of the pMOS output transistor (M ₈ ), and the other end is connected to the bypass capacitor (C ₁ ) and the voltage source (V _DD ), respectively. One end of the circuit capacitor (C ₁ ) is connected to the inductor (L _b ), and the other end is grounded; one end of the harmonic short-circuit capacitor (C ₂ ) is connected to the drain of the pMOS output tube (M ₈ ), and the other end is grounded; the output capacitor (C 2 ) _out ) one end is connected to the drain of the pMOS output transistor (M ₈ ), and the other end is used as the output end of the output buffer.

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