CN110729348B - Infrared sensor and preparation method thereof - Google Patents
Infrared sensor and preparation method thereof Download PDFInfo
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Abstract
本发明提供了一种传感器，其特征在于，包括：晶体管(1)，光电探测器(2)，参考电阻(3)以及衬底(4)；晶体管(1)包括第一源极(7)，第一漏极(8)以及第一无机半导体纳米线(9)，第一无机半导体纳米线(9)与第一源极(7)与第一漏极(8)连接；光电探测器(2)包括第二无机半导体纳米线(10)，第二源极(11)以及第二漏极(12)，第二无机半导体纳米线(10)与第二源极(11)与第二漏极(12)连接；参考电阻(3)包括第二无机半导体纳米线(10)，第三源极(13)以及第三漏极(14)，第二无机半导体纳米线(10)与第三源极(13)与第三漏极(14)连接。该传感器用于解决暗电流过大、光电流过小的问题，显著增强开关比。
The invention provides a sensor, which is characterized by comprising: a transistor (1), a photodetector (2), a reference resistor (3) and a substrate (4); the transistor (1) includes a first source electrode (7) , a first drain electrode (8) and a first inorganic semiconductor nanowire (9), the first inorganic semiconductor nanowire (9) is connected to the first source electrode (7) and the first drain electrode (8); the photodetector ( 2) comprising a second inorganic semiconductor nanowire (10), a second source electrode (11) and a second drain electrode (12), a second inorganic semiconductor nanowire (10), a second source electrode (11) and a second drain electrode The electrode (12) is connected; the reference resistor (3) includes a second inorganic semiconductor nanowire (10), a third source (13) and a third drain (14), and the second inorganic semiconductor nanowire (10) and the third The source electrode (13) is connected to the third drain electrode (14). The sensor is used to solve the problem of too large dark current and too small photocurrent, and significantly enhance the on-off ratio.
Description
Technical Field
The invention belongs to the field of flexible electronic devices and the field of photoelectric detectors, and particularly relates to a development and preparation method of an infrared sensor.
Background
The optical communication technology is the important factor in the informatization technology, and has the advantages of high confidentiality, interference resistance, long transmission distance and the like. However, the existing photodetectors, whether one-dimensional materials, two-dimensional materials or organic materials, have a large dark current, so that the on-off ratio of the devices is low, and the discrimination between the photocurrent and the dark current is not high.
In the research work of predecessors, the traditional infrared photoelectric detector is mainly manufactured on a silicon substrate, cannot be bent, and cannot meet the requirements of flexibility, wearability and portability. Therefore, those skilled in the art adopt a one-dimensional inorganic nanowire as a semiconductor layer to obtain an infrared photodetector, the switching ratio of which is only 2 times or less than 2 times, and under such a low switching ratio, when there are interferences such as noise and the like and limitations of device stability in practical application scenes, errors occur in the transmission process, the information transmission reliability is reduced, and the infrared photodetector is basically unusable. In another research work, technicians in the field use organic materials to manufacture photodetectors, but the problems of short service life, harsh requirements on the preparation environment, easy environmental influence, oversize of the prepared photodetectors and the like exist.
Disclosure of Invention
Technical problem to be solved
The invention provides an infrared sensor and a preparation method thereof, which are used for at least partially solving the problems of overlarge dark current, overlow on-off ratio and the like of a dark electric sensor.
(II) technical scheme
The present invention provides a sensor, characterized by comprising: a transistor 1, a photodetector 2, a reference resistor 3, and a substrate 4; the transistor 1 comprises a gate 5, an insulating layer 6, a first source 7, a first drain 8 and a first inorganic semiconductor nanowire 9; a first source 7 and a first drain 8 are arranged on the substrate 4, a first inorganic semiconductor nanowire 9 is connected with the first source 7 and the first drain 8, an insulating layer 6 is arranged on the first source 7, the first drain 8 and the first inorganic semiconductor nanowire 9, and a gate 5 is arranged on the insulating layer 6; the photodetector 2 includes a second inorganic semiconductor nanowire 10, a second source electrode 11, and a second drain electrode 12; a second source 11 and a second drain 12 are disposed on the substrate 4, and a second inorganic semiconductor nanowire 10 is connected to the second source 11 and the second drain 12; the reference resistor 3 comprises a second inorganic semiconductor nanowire 10, a third source 13 and a third drain 14; a third source electrode 13 and a third drain electrode 14 are arranged on the substrate 4, and the second inorganic semiconductor nanowire 10 is connected with the third source electrode 13 and the third drain electrode 14; the second drain electrode 12 and the third drain electrode 14 are connected with the gate electrode 5; wherein the forbidden band width of the first inorganic semiconductor nanowire 9 is larger than that of the second inorganic semiconductor nanowire 10.
Optionally, the forbidden bandwidth of the first inorganic semiconductor nanowire 9 is greater than or equal to 2.3 eV; the second inorganic semiconductor nanowire 10 has a forbidden band width of less than 0.26 eV.
Optionally, the first inorganic semiconductor nanowire 9 is at least one of indium oxide, gallium oxide, zinc oxide, steel gallium oxide, and steel gallium zinc oxide.
Optionally, the second inorganic semiconductor nanowire 10 material is bismuth selenide sulfide.
Optionally, the area of the contact surface of the first inorganic semiconductor nanowire 9 with the insulating layer 6 is smaller than the area of the contact surface of the gate electrode 5 with the insulating layer 6.
Optionally, the area of the contact surface between the gate 5 and the insulating layer 6 is smaller than the area of the contact surface between the insulating layer 6 and the gate 5.
Optionally, the substrate 4 is a bendable flexible substrate.
The invention also provides a device comprising a plurality of sensors as described above, which are interconnected via the second drain electrode 11, the gate electrode 5 and the third drain electrode 14.
The invention also provides a preparation method of the sensor, which comprises the following steps: s1, preparing a first source 7, a first drain 8, a second source 11, a second drain 12, a third source 13 and a third drain 14 on the substrate 4; s2, preparing a first inorganic semiconductor nanowire 9 and a second inorganic semiconductor nanowire 10; connecting the first inorganic semiconductor nanowire 9 with the first source electrode 7 and the first drain electrode 8; connecting the second inorganic semiconductor nanowire 10 with a second source electrode 11 and a second drain electrode 12; connecting the second inorganic semiconductor nanowire 10 to a third source electrode 13 and a third drain electrode 14; s3, preparing an insulating layer 6 on the first source electrode 7, the first drain electrode 8 and the first inorganic semiconductor nanowire 9; s4, the gate electrode 5 is formed on the insulating layer 6, and then the second drain electrode 12, the gate electrode 5, and the third drain electrode 14 are connected to obtain the sensor.
Alternatively, preparing the first source electrode 7, the first drain electrode 8, the second source electrode 11, the second drain electrode 12, the third source electrode 13, and the third drain electrode 14 on the substrate 4 includes:
preparing a chromium metal layer on the substrate 4, preparing a gold metal layer on the chromium metal layer, and then preparing the chromium metal layer on the gold metal layer to obtain a first source electrode 7, a first drain electrode 8, a second source electrode 11, a second drain electrode 12, a third source electrode 13 and a third drain electrode 14.
(III) advantageous effects
1. The invention suppresses dark current (I) by disposing a first inorganic semiconductor nanowire in a transistor and a second inorganic semiconductor nanowire in a photodetector and a reference resistoroff1pA), increase photocurrent (I)on100nA) to significantly improve the switching ratio (10 ten thousand times), and external circuit noise interference can be suppressed;
2. the first inorganic semiconductor nanowire and the second inorganic semiconductor nanowire provided by the invention have stronger elasticity and toughness, so that a device or a sensor is not easy to crack in a bending state, and the device or the sensor still has excellent and stable electrical properties in the bending state;
3. the first inorganic semiconductor nanowire and the second inorganic semiconductor nanowire provided by the invention have larger specific surface area than that of semiconductor materials with a bulk structure and a thin film structure, and also have higher crystallinity and a small size comparable to the Debye length, so that the first inorganic semiconductor nanowire and the second inorganic semiconductor nanowire have more excellent optical and electrical properties than those of semiconductor materials with a bulk structure and a thin film structure;
4. the flexible full-nanowire infrared sensor provided by the invention has the advantages of simple manufacturing process, easiness in operation, small volume, light weight, flexibility, easiness in carrying and the like, can be combined with the traditional silicon processes such as photoetching and the like, and is favorable for industrial production;
5. the size of a single sensor of the infrared sensor provided by the invention can be 1mm in length, 1mm in width and not more than 500 micrometers in thickness, any n multiplied by m device can be manufactured according to the requirement, and with the progress of the process, the size of the single sensor can be smaller, the density of pixel points in unit area can be higher, and further, the infrared image sensing is realized.
Drawings
FIG. 1 is a side sectional view schematically showing an infrared sensor according to an embodiment of the present invention;
FIG. 2 schematically illustrates a three-dimensional structural view of an infrared sensor in an embodiment of the invention;
FIG. 3 schematically illustrates a circuit schematic of a nanowire infrared sensor in an embodiment of the invention;
FIG. 4 schematically shows a transfer characteristic graph of a transistor in an embodiment of the invention;
FIG. 5A schematically illustrates a current-time plot of a nanowire infrared sensor applying 1342nm infrared light in an embodiment of the invention;
FIG. 5B schematically illustrates a current-time plot of a nanowire infrared sensor applying 915nm infrared light in an embodiment of the invention;
FIG. 6 is a flow chart of a method for fabricating a nanowire infrared sensor in an embodiment of the invention;
figure 7A schematically illustrates an SEM image of indium gallium oxide nanowires in an embodiment of the invention;
fig. 7B schematically shows an SEM image of bismuth selenide sulfide nanowires in an embodiment of the invention.
Description of reference numerals: 1-a transistor; 2-a photodetector; 3-reference resistance; 4-a substrate; 5-a grid; 6-an insulating layer; 7-a first source; 8-a first drain electrode; 9-a first inorganic semiconductor nanowire; 10-a second inorganic semiconductor nanowire; 11-a second source; 12-a second drain electrode; 13-a third source; 14-third drain electrode.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings.
Referring to fig. 1, fig. 1 schematically shows a side cross-sectional structural view of an infrared sensor in an embodiment of the present invention. The sensor includes:
a transistor 1, a photodetector 2, a reference resistor 3, and a substrate 4;
the transistor 1 comprises a gate 5, an insulating layer 6, a first source 7, a first drain 8 and a first inorganic semiconductor nanowire 9; the first source electrode 7, the first drain electrode 8 are disposed on the substrate 4, the first inorganic semiconductor nanowire 9 is connected with the first source electrode 7 and the first drain electrode 8, the insulating layer 6 is disposed on the first source electrode 7, the first drain electrode 8 and the first inorganic semiconductor nanowire 9, and the gate 5 is disposed on the insulating layer 6.
The shapes of the first source 7 and the first drain 8 in the embodiment of the invention can be circular and n-polygon (n ≧ 3); the material of the first source electrode 7 and the first drain electrode 8 may be a metal layer, such as a chromium metal layer and a gold metal layer, in this embodiment, a chromium metal layer is evaporated on the substrate 4, a gold metal layer is evaporated on the chromium metal layer, and a chromium metal layer is evaporated on the gold metal layer, taking the structure of the three metal layers as an example, the thickness range of the chromium metal layer evaporated on the substrate 4 and the thickness range of the chromium metal layer evaporated on the gold metal layer may be, for example, 3nm to 5nm, the thickness range of the gold metal layer may be, for example, 5nm to 15nm, and the specific thickness range is not specifically limited by the present invention, but the total thickness range of the three metal layers is less than or equal to 35 nm.
The shape of the gate 5 in the embodiment of the present invention may be a circle or an n-polygon (n is greater than or equal to 3), and the specific shape is not limited in this embodiment, and the area of the contact surface between the first inorganic semiconductor nanowire 9 and the insulating layer 6 is smaller than the area of the contact surface between the gate 5 and the insulating layer 6, and the area of the contact surface between the gate 5 and the insulating layer 6 is smaller than the area of the contact surface between the insulating layer 6 and the gate 5, where the contact surface between the gate 5 and the insulating layer 6 represents a surface on the gate 5, and the contact surface between the insulating layer 6 and the gate 5 represents a surface on the insulating. The structure is similar to a FinFET structure, and the gate control performance of the transistor can be better improved.
In this embodiment, the first inorganic semiconductor nanowire 9 is a one-dimensional inorganic wide bandgap semiconductor nanowire. The first inorganic semiconductor nanowire 9 is connected to the first source electrode 7 and the first drain electrode 8. The inorganic wide bandgap semiconductor represents an inorganic semiconductor material with a bandgap greater than or equal to 2.3eV, so that the first inorganic semiconductor nanowire 9 has a good transistor gate voltage regulation performance. The material of the first inorganic semiconductor nanowire 9 includes: binary oxides such as indium oxide, gallium oxide, zinc oxide, etc., ternary oxides such as indium gallium oxide, etc., quaternary oxides such as indium gallium zinc oxide, etc., and specific inorganic wide bandgap semiconductor materials are not particularly limited in the present invention.
In this embodiment, the material of the insulating layer 6 may be a high-dielectric-constant material such as silicon dioxide, silicon nitride, aluminum oxide, hafnium oxide, etc., and the specific material of this embodiment is not particularly limited. When silicon dioxide is used as the insulating layer 6, the thickness of the insulating layer may be in the range of 100nm to 300nm, for example.
The photodetector 2 includes a second inorganic semiconductor nanowire 10, a second source electrode 11, and a second drain electrode 12; the second source 11 and the second drain 12 are disposed on the substrate 4, and the second inorganic semiconductor nanowire 10 is connected to the second source 11 and the second drain 12.
The second source electrode 11 and the second drain electrode 12 are made of metal, and in this embodiment, for example, a chromium metal layer and a gold metal layer may be used, a chromium metal layer is deposited on the substrate 4, a gold metal layer is deposited on the chromium metal layer, and a chromium metal layer is deposited on the gold metal layer to obtain the second source electrode 11 and the second drain electrode 12, where the thickness of the chromium metal layer may be, for example, 3nm to 5nm, and the thickness of the gold metal layer may be, for example, 5nm to 15 nm. The cross-sectional shapes of the second source electrode 11 and the second drain electrode 12 may be interdigital, circular, or n-sided (n.gtoreq.3).
The second inorganic semiconductor nanowire 10 is a one-dimensional inorganic narrow-gap semiconductor nanowire, so the forbidden band width of the second inorganic semiconductor nanowire 10 is less than 0.26eV, and further the forbidden band width is much less than the forbidden band width of the first inorganic semiconductor nanowire 9. Meanwhile, the material of the one-dimensional inorganic narrow-bandgap semiconductor nanowire is mainly a BiSeS ternary mixed material, so that the one-dimensional inorganic narrow-bandgap semiconductor nanowire has good response characteristics to light in an infrared band, and the material of the one-dimensional inorganic narrow-bandgap semiconductor nanowire is not particularly limited in the invention.
The reference resistor 3 includes a second inorganic semiconductor nanowire 10, a third source 13 and a third drain 14; a third source 13 and a third drain 14 are disposed on the substrate 4, and the second inorganic semiconductor nanowire 10 is connected to the third source 13 and the third drain 14. The third source electrode 13 and the third drain electrode 14 are made of metal, and in this embodiment, for example, a chromium metal layer and a gold metal layer may be used, a chromium metal layer is deposited on the substrate 4, a gold metal layer is deposited on the chromium metal layer, and a chromium metal layer is deposited on the gold metal layer to obtain the third source electrode 13 and the third drain electrode 14, where the thickness of the chromium metal layer may be, for example, 3nm to 5nm, and the thickness of the gold metal layer may be, for example, 5nm to 15 nm. Wherein the second inorganic semiconductor nanowire 10 is connected to a third source 13 and a third drain 14.
Referring to fig. 2, fig. 2 schematically shows a three-dimensional structure diagram of an infrared sensor in an embodiment of the present invention; and referring to fig. 3, fig. 3 schematically illustrates a circuit schematic diagram of a nanowire infrared sensor in an embodiment of the present invention. The photodetector 2, the reference resistor 3, and the gate 5 of the transistor 1 are connected by a wire. As can be seen from fig. 1, 2 and 3, the specific connection method is: the second drain 12 of the photodetector 2 and the third drain 14 of the reference resistor 3 are connected to the gate 5 of the transistor 1 by wires. Moreover, the InGaO ternary nanowire is adopted as the first inorganic semiconductor nanowire 9 in the transistor 1, the BiSeS ternary nanowire is adopted as the second inorganic semiconductor nanowire 10 in the photodetection 2 and the second inorganic semiconductor nanowire 10 in the reference resistor 3, and the beneficial effects brought by the structure and the selected materials are as follows: the photodetector 2 and the reference resistor 3 can build a voltage division circuit, the voltage division of the voltage division circuit is applied to the transistor 1, when a light source irradiates on the photodetector 2, the resistance of the reference resistor 3 connected with the photodetector 2 changes, so that the voltage applied to the grid 5 on the transistor 1 changes, the output of the first source 7 in the transistor 1 is used as the final output of the whole sensor, and when the voltage changes, the on and off of the transistor 1 can be controlled. Because the off-state current of the transistor 1 is smaller than the off-state current of the photoelectric detector 2, and the on-state current is larger than the photoelectric current of the photoelectric detector 2, the final output of the first source 7 has the effects of extremely small dark current and extremely large photoelectric current, and the sensor can also avoid overlarge noise when an external circuit is connected, so that noise interference is inhibited.
The substrate 4 is a flexible substrate, and the material of the flexible substrate may be, for example, polyethylene terephthalate (PET) or Polyimide (PI), and the specific material is not limited in this embodiment.
In order to examine the performance of the transistor of the present invention, referring to fig. 4, fig. 4 schematically shows a transfer characteristic graph of the transistor in the embodiment of the present invention. As can be seen from fig. 4, the average value of the dark current is about 1 × 10-13The average value of the photocurrents is about 1 × 10-6On/off ratio of 107And the subthreshold swing is less than 100mV, so that dark current can be restrained and photocurrent can be enhanced.
The present invention further provides an embodiment, and referring to fig. 5A, fig. 5A schematically shows a current-time curve of 1342nm infrared light applied by the nanowire infrared sensor in the embodiment of the present invention. As can be seen from fig. 5A, when the photodetector 2 receives the irradiation of the infrared light with the wavelength of 1342nm, the average value of the dark current in this embodiment is about 1pA, the average value of the photocurrent is about 100nA, and the on-off ratio is about 10 ten thousand times, which is significantly improved compared to the conventional sensor with twice the on-off ratio. Referring to FIG. 5B, FIG. 5B is a graph schematically illustrating the current-time curve of the infrared light of 915nm applied by the nanowire infrared sensor in the embodiment of the present invention, and FIG. 5B shows that when the infrared wavelength of 915nm is received by the photodetector 2 in the embodiment, the average value of the dark current is about 1 × 10-12A, the average value of the photocurrent is about 1 × 10-7A, on-off ratio of about 105There is also a significant improvement.
The embodiment of the present invention further provides a device, which includes a plurality of sensors, where the plurality of sensors are connected to each other through the second drain electrode 11, the gate electrode 5, and the third drain electrode 14. And, since the size of a single sensor can be 1mm × 1mm, the thickness range does not exceed 500 μm. So that the device can be obtained by connecting the second drain electrode 11, the gate electrode 5 and the third drain electrode 14 by a plurality of sensors, and then forming an m × n sensor array. When the light receiving area is large, the number of devices connected by the sensors can be increased properly, and when the light receiving area is small, the number of devices formed by connecting the sensors can be reduced properly, so that the device can adapt to different light receiving areas to obtain an optimal test result.
The embodiment of the present invention further provides a method for manufacturing a sensor, referring to fig. 6, fig. 6 schematically illustrates a flowchart of a method for manufacturing a nanowire infrared sensor in an embodiment of the present invention, including:
s1, preparing a first source 7, a first drain 8, a second source 11, a second drain 12, a third source 13 and a third drain 14 on the substrate 4.
First, the substrate 4 is prepared and cleaned. The substrate 4 in this embodiment is a flexible substrate, which may be, for example, polyethylene terephthalate (PET), the PET is cut into a suitable size, the size is ultrasonically treated in acetone for 10min, then the size is ultrasonically treated in ethanol for 10min, and the process is repeated several times to obtain a clean substrate 4.
Then, a layer of photoresist is spin-coated on the substrate 4, the photoresist is heated and baked and then developed, then the photoresist is put into an evaporation coating machine to be evaporated to form a first source electrode 7, a first drain electrode 8, a second source electrode 11, a second drain electrode 12, a third source electrode 13 and a third drain electrode 14, and a patterned electrode is obtained after stripping, wherein the obtained first source electrode 7, the first drain electrode 8, the second source electrode 11, the second drain electrode 12, the third source electrode 13 and the third drain electrode 14 are composed of three metal layers, a chromium metal layer is vapor-coated on the substrate 4, a gold metal layer is vapor-coated on the chromium metal layer, and then a chromium metal layer is vapor-coated on the gold metal layer to form the first source electrode 7, the first drain electrode 8, the second source electrode 11, the second drain electrode 12, the third source electrode 13 and the third drain electrode 14.
S2, preparing a first inorganic semiconductor nanowire 9 and a second inorganic semiconductor nanowire 10; connecting the first inorganic semiconductor nanowire 9 with the first source electrode 7 and the first drain electrode 8; connecting the second inorganic semiconductor nanowire 10 with a second source electrode 11 and a second drain electrode 12; the second inorganic semiconductor nanowire 10 is connected to the third source electrode 13 and the third drain electrode 14.
First, the first inorganic semiconductor nanowire 9 is transferred onto the substrate 4, in particular the first inorganic semiconductor nanowire 9 is arranged between the first source 7, the first drain 8. In this embodiment, the first inorganic semiconductor nanowire 9 is an InGaO nanowire, and the invention is not limited to specific materials. The growth method of the InGaO nanowire adopts a growth mechanism of a VLS method, and the detailed process is shown as follows:
0.1gIn2O3Powder, 0.06gGa2O3The powder and 0.06g of C powder were mixed and put into a quartz tube having a small size, a small piece of Si sheet having a 3nmAu film deposited on the surface thereof was placed at the gate of the quartz tube, and the quartz tube was then placed in the center of a tube furnace. The temperature of the tube furnace is increased to 1100 ℃ within 40min, the temperature is kept at 1100 ℃ for 1 hour, the InGaO nanowire is obtained after the InGaO nanowire is naturally cooled to room temperature, and an SEM image of the InGaO nanowire refers to FIG. 7A, and FIG. 7A schematically shows an SEM image of the indium gallium oxide nanowire in the embodiment of the invention, which shows that the InGaO semiconductor is successfully synthesized in the embodiment, and the shape of the InGaO semiconductor is exactly the shape of the nanowire. Firstly transferring the InGaO nanowire to SiO in a contact friction mode2On the thin film, the InGaO nanowire is picked up through the optical fiber and transferred to a position between the first source electrode 7 and the first drain electrode 8.
Then, the second inorganic semiconductor nanowire 10 is synthesized. The synthesis method also selects the growth mechanism of the VLS method, and the detailed process is shown as follows:
0.1gBi2O3Placing the powder into a ceramic boat, mixing 0.5g S powder and 0.5g 0.5gSe powder, placing into another ceramic boat, placing the ceramic boat containing 0.5g S powder and 0.5g 0.5gSe powder into the non-heating zone of a tube furnace, placing the ceramic boat containing 0.1g 0.1gBi powder2O3Placing the ceramic boat of powder into the heating zone in the middle of the tube furnace, and placing a piece of SiO in the other non-heating zone of the tube furnace2For depositing material. The temperature of the tube furnace was set to rise to 650 ℃ within 30min, and when the temperature of the tube furnace was raised to 600 ℃, the ceramic boat containing 0.5g of S powder and 0.5g of 0.5gSe powder was transferred to the heating zone, and then the temperature was maintained at 1 ℃ at 650 ℃After 0min, the sample was naturally cooled to room temperature, and an SEM image of the tsbi nanowire shown in fig. 7B was obtained, and it can be seen from fig. 7B that the tsbi semiconductor was successfully synthesized in this example, and it can be clearly seen from the SEM that the tsbi semiconductor is in a nanowire shape.
Finally, the synthesized BiSeS nanowire is firstly transferred to SiO by contact friction in the same way2On the thin film, the BiSeS nanowire is picked up through the optical fiber and transferred to a position between the second source electrode 11 and the second drain electrode 12. And the synthesized BiSeS nanowire is transferred between the third source electrode 13 and the third drain electrode 14 in the same manner.
Because the first inorganic semiconductor nanowire 9 is a one-dimensional wide-bandgap inorganic semiconductor InGaO nanowire, and the second inorganic semiconductor nanowire 10 is a one-bit narrow-bandgap inorganic semiconductor BiSeS nanowire, the semiconductor has elasticity and toughness, cracks are not easy to generate on the surface of a material after deformation, and the sensor still has excellent electrical stability in a bent state. Moreover, the first inorganic semiconductor nanowire 9 and the second inorganic semiconductor nanowire 10 have larger surface areas than those of the bulk structure and the thin film structure, and have better crystallinity and smaller size than that of the debye length, so that excellent optical performance and electrical performance of the nanowires are further determined.
S3, preparing an insulating layer 6 on the first source electrode 7, the first drain electrode 8 and the first inorganic semiconductor nanowire 9.
On the basis of step S2, a layer of photoresist is spin-coated on the first source electrode 7, the first drain electrode 8 and the first inorganic semiconductor nanowire 9, and a layer of SiO 200nm thick is sputtered by ion sputtering after heating, baking, photolithography and development2And stripping to obtain the patterned insulating layer 6, wherein the insulating layer 6 can completely cover the InGaO nanowire.
S4, the gate electrode 5 is formed on the insulating layer 6, and then the second drain electrode 12, the gate electrode 5, and the third drain electrode 14 are connected to obtain the sensor.
And (6) on the basis of the step S3, spin-coating photoresist on the insulating layer 6, heating, baking, photoetching, developing, putting into an evaporation coating machine for evaporation, and stripping to obtain the patterned grid 5. The grid 5 is also composed of two metal layers, wherein a chromium metal layer is evaporated on the insulating layer 6, and a gold metal layer is evaporated on the chromium metal layer. The gate electrode 5 can completely cover the first inorganic semiconductor nanowire 9 and partially cover the insulating layer 6, which structure is similar to a FinFET structure, which can improve the gate control performance of the transistor. Then, the second drain electrode 12, the gate electrode 5, and the third drain electrode 14 are connected to obtain the sensor.
For the dimensional parameters and material types of the structures in the preparation method, reference is made to the above-mentioned structural embodiments, which are not described herein again.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
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