CN110729236A - Manufacturing method of array substrate, array substrate and display panel - Google Patents

Abstract

The present invention provides a manufacturing method of an array substrate, an array substrate and a display panel. The manufacturing method of the array substrate comprises: sequentially depositing a transparent conductive layer and a gate metal layer on a base substrate, and performing a first photolithography process to forming a pixel electrode and a gate electrode; sequentially depositing a gate insulating layer, a metal oxide semiconductor layer and a protective layer on the base substrate formed with the pixel electrode and the gate electrode, and performing a second photolithography process to form a metal oxide Semiconductor patterns, protective patterns, contact vias between source and drain electrodes and metal oxide semiconductor patterns, and contact vias between drain electrodes and pixel electrodes; deposition on a base substrate formed with metal oxide semiconductor patterns and protective patterns A source-drain metal layer is performed, and a third photolithography process is performed to form a source electrode and a drain electrode, and the drain electrode and the pixel electrode are electrically connected. The invention can reduce the number of photolithography process, the process is simple, and the manufacturing cost is low.

Description

Manufacturing method of array substrate, array substrate and display panel

technical field

The invention relates to the field of liquid crystal display, and in particular, to a manufacturing method of an array substrate, an array substrate and a display panel.

Background technique

With the development of display technology, flat display devices such as Liquid Crystal Display (LCD) are widely used in mobile phones, televisions, personal Various consumer electronic products such as digital assistants and notebook computers have become the mainstream of display devices. A liquid crystal display panel is generally composed of an array substrate, a color filter substrate, and a liquid crystal molecule layer sandwiched between the array substrate and the color filter substrate. By applying a driving voltage between the array substrate and the color filter substrate, the rotation of the liquid crystal molecules can be controlled, so that the light from the backlight module is refracted to produce a picture.

The manufacturing method of the array substrate provided by the prior art includes six lithography processes, including: the first step: depositing a metal layer on a glass substrate, and performing the first lithography process to form a gate; the second step, depositing sequentially The gate insulating layer and the indium gallium zinc oxide IGZO semiconductor layer are subjected to a second photolithography process to form an active island pattern; the third step is to deposit an etching barrier layer, and a third photolithography process is performed to form Etching the blocking pattern; the fourth step, depositing the source and drain metal layers, and performing the fourth photolithography process to form the source and drain electrodes; the fifth step, depositing the passivation layer and the planarization layer, and performing the fifth step A second photolithography process is performed to form a conductive via hole; in the sixth step, a transparent conductive film is deposited, and a sixth photolithography process is performed to form a pixel electrode and a connection pattern between the conductive via hole and the pixel electrode.

The six-step photolithography process provided by the above-mentioned prior art is complicated in process and high in manufacturing cost.

SUMMARY OF THE INVENTION

The invention provides a manufacturing method of an array substrate, an array substrate and a display panel, which can reduce the number of photolithography processes, have simple process and low manufacturing cost.

In a first aspect, the present invention provides a method for manufacturing an array substrate, comprising: sequentially depositing a transparent conductive layer and a gate metal layer on a base substrate, and performing a first photolithography process to form a pixel electrode and a gate electrode; A gate insulating layer, a metal oxide semiconductor layer and a protective layer are sequentially deposited on the base substrate on which the pixel electrode and the gate are formed, and a second photolithography process is performed to form a metal oxide semiconductor pattern, a protective pattern, a source Contact via holes between the electrode and drain electrode and the metal oxide semiconductor pattern, and contact via hole between the drain electrode and the pixel electrode; deposit a source and drain metal layer on the base substrate on which the metal oxide semiconductor pattern and the protective pattern are formed, and A third photolithography process is performed to form a source electrode and a drain electrode and electrically connect the drain electrode and the pixel electrode.

In a second aspect, the present invention provides an array substrate, including a base substrate, a pixel electrode, a gate electrode, a transparent conductive pattern, a gate insulating layer, a metal oxide semiconductor pattern, a source electrode, a drain electrode, and a protection pattern, and a pixel electrode. It is arranged on the base substrate, the transparent conductive pattern and the pixel electrode are arranged on the same layer, the gate is arranged on the transparent conductive pattern, the gate insulating layer is covered on the substrate with the gate and the pixel electrode, and the metal oxide The protection pattern and the protection pattern are sequentially arranged on the gate insulating layer, at least part of the structure of the source electrode and the drain electrode are arranged on the metal oxide semiconductor pattern, the drain electrode is electrically connected with the pixel electrode, and the pixel electrode and the gate electrode are in the same primary light. formed in the engraving process.

In a third aspect, the present invention provides a display panel, comprising a color filter substrate, a liquid crystal layer and the above-mentioned array substrate, and the liquid crystal layer is sandwiched between the color filter substrate and the array substrate.

Embodiments of the present invention provide a method for manufacturing an array substrate, an array substrate, and a display panel. The method for manufacturing an array substrate includes: sequentially depositing a transparent conductive layer and a gate metal layer on a base substrate, and performing a first photolithography process, to form a pixel electrode and a gate; deposit a gate insulating layer, a metal oxide semiconductor layer and a protective layer on the base substrate formed with the pixel electrode and the gate, and perform a second photolithography process to form a metal oxide A semiconductor pattern, a protection pattern, a contact via hole between the source electrode and the drain electrode and the metal oxide semiconductor pattern, and a contact via hole between the drain electrode and the pixel electrode; after forming the metal oxide semiconductor pattern and the protection pattern A source and drain metal layer is deposited on the base substrate, and a third photolithography process is performed to form a source electrode and a drain electrode. By forming the transparent conductive layer under the gate metal layer, the pixel electrode and the gate electrode can be formed simultaneously in the same photolithography process, which is different from the prior art in which the pixel electrode is formed above the planarization layer and the gate electrode is formed on the planar surface. Below the chemical layer, compared with the case where the pixel electrode and the gate need to be formed in two photolithography processes, the number of one photolithography process is reduced, so the manufacturing process is simple and the manufacturing cost is low.

Description of drawings

In order to illustrate the technical solutions of the present invention or the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are of the present invention. For some embodiments of the present invention, for those of ordinary skill in the art, other drawings can also be obtained according to these drawings without any creative effort.

FIG. 1 is a schematic flowchart of a method for manufacturing an array substrate according to Embodiment 1 of the present invention;

2 is a schematic structural diagram of the array substrate in the first state in the manufacturing method of the array substrate provided in the first embodiment of the present invention;

3 is a schematic structural diagram of the array substrate in the second state in the manufacturing method of the array substrate provided in the first embodiment of the present invention;

4 is a schematic structural diagram of the array substrate after the first etching in the second lithography process in the method for manufacturing the array substrate provided in the first embodiment of the present invention;

5 is a schematic structural diagram of the array substrate after the second etching in the second photolithography process in the method for manufacturing the array substrate provided in the first embodiment of the present invention;

6 is a schematic structural diagram of an array substrate in a method for manufacturing an array substrate provided in Embodiment 1 of the present invention;

7 is a top view of the array substrate in the manufacturing method of the array substrate provided in the first embodiment of the present invention;

8 is a schematic structural diagram of an array substrate according to Embodiment 2 of the present invention;

FIG. 9 is a schematic structural diagram of an array substrate of another structure according to the second embodiment of the present invention.

Reference number:

1-substrate; 2-pixel electrode; 3-gate; 4-gate insulating layer; 5'-metal oxide semiconductor layer; 6'-protection layer; 5-metal oxide semiconductor pattern; 6-protection pattern ; 7-source electrode; 8-drain electrode; 9-contact via hole of drain electrode and pixel electrode; 10-first via hole; 10'-second via hole; 11-isolation via hole; 80-first lithography 81-resist partial reserved area; 82-photoresist completely removed area.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention. , not all examples. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

Example 1

FIG. 1 is a schematic flowchart of a method for manufacturing an array substrate according to Embodiment 1 of the present invention. As shown in FIG. 1 , the method for manufacturing an array substrate in this embodiment includes:

S10 , sequentially depositing a transparent conductive layer and a gate metal layer on the base substrate 1 , and performing a first photolithography process to form a pixel electrode 2 and a gate electrode 3 .

的透明导电层和厚度为

的栅金属层。透明导电层一般为ITO，IZO，也可以是其它的透明电极层，栅金属层可以选用Cr、W、Cu、Ti、Ta、Mo、等金属或合金，由多层金属组成的栅金属层也能满足需要。通过一次灰色调或者半色调掩膜版光刻工艺后，形成透明的像素电极2和栅极3。需要注意的是由于在衬底基板1上先沉积透明导电层再沉积栅金属层，因此在栅极3和衬底基板1之间夹设有透明导电金属材料，这样可以增加栅极3和衬底基板1的附着性。Specifically, optionally, on the base substrate 1, such as a glass substrate, sputtering or thermal evaporation are used to sequentially deposit a thickness of about

The transparent conductive layer and thickness are

gate metal layer. The transparent conductive layer is generally ITO, IZO, or other transparent electrode layers. The gate metal layer can be selected from metals or alloys such as Cr, W, Cu, Ti, Ta, Mo, etc. The gate metal layer composed of multi-layer metals is also can meet the needs. The transparent pixel electrode 2 and the gate electrode 3 are formed after passing through a gray-tone or half-tone mask photolithography process. It should be noted that since the transparent conductive layer is first deposited on the base substrate 1 and then the gate metal layer is deposited, a transparent conductive metal material is sandwiched between the gate 3 and the base substrate 1, which can increase the gate 3 and the lining. Adhesion of the base substrate 1 .

By forming the transparent conductive layer under the gate metal layer, the pixel electrode 2 and the gate electrode 3 can be formed simultaneously in the same photolithography process, which is different from the prior art that the pixel electrode 2 is formed above the planarization layer, the gate electrode is formed 3 is formed under the planarization layer, and the pixel electrode 2 and the gate electrode 3 need to be formed in two photolithography processes. Compared with the case where the number of photolithography processes is reduced, the manufacturing process of the entire array substrate is simplified and the manufacturing cost is reduced. Low.

S20, sequentially depositing the gate insulating layer 4, the metal oxide semiconductor layer 5' and the protective layer 6' on the base substrate 1 on which the pixel electrode 2 and the gate electrode 3 are formed, and performing a second photolithography process to form The metal oxide semiconductor pattern 5, the protection pattern 6, the contact via holes between the source and drain electrodes and the metal oxide semiconductor pattern, and the contact via hole 9 between the drain electrode and the pixel electrode.

的栅极绝缘层4，栅极绝缘层4可以选用氧化物、氮化物或者氧氮化合物，对应的反应气体采用SiH₄，N₂O；所述等离子体增强化学的气相沉积法中形成氮化物或氧氮化合物对应的反应气体是SiH₄、NH₃、N₂或SiH₂Cl₂、NH₃、N₂；然后在其上通过溅射或热蒸发的方法沉积上厚度约为

的金属氧化物半导体层5’，金属氧化物半导体层5’可以是采用非晶IGZO、HIZO、IZO、a-InZnO、a-InZnO、ZnO:F、In₂O₃:Sn、In₂O₃:Mo、Cd₂SnO₄、ZnO:Al、TiO₂:Nb、Cd-Sn-O或其他金属氧化物制成，接着再通过等离子体增强化学的气相沉积法沉积厚度为

的保护层6’，保护层6’可以选用氧化物、氮化物或者氧氮化合物，硅的氧化物对应的反应气体可以为SiH₄，N₂O；氮化物或者氧氮化合物对应气体是SiH₄，NH₃，N₂或SiH₂Cl₂，NH₃，N₂；保护层6’也可以使用Al₂O₃，或者双层的保护结构。Optionally, on the base substrate 1 on which the gate electrode 3 and the pixel electrode 2 are formed, the thickness is continuously deposited by the plasma-enhanced chemical vapor deposition method.

The gate insulating layer 4, the gate insulating layer 4 can be selected from oxides, nitrides or oxygen-nitrogen compounds, and the corresponding reactive gases are SiH ₄ , N ₂ O; nitrides are formed in the plasma-enhanced chemical vapor deposition method Or the corresponding reactive gases of oxygen and nitrogen compounds are SiH ₄ , NH ₃ , N ₂ or SiH ₂ Cl ₂ , NH ₃ , N ₂ ;

The metal oxide semiconductor layer 5', the metal oxide semiconductor layer 5' can be made of amorphous IGZO, HIZO, IZO, a-InZnO, a-InZnO, ZnO:F, In ₂ O ₃ :Sn, In ₂ O ₃ : Mo, Cd ₂ SnO ₄ , ZnO:Al, TiO ₂ :Nb, Cd-Sn-O or other metal oxides, and then deposited by plasma enhanced chemical vapor deposition with a thickness of

The protective layer 6', the protective layer 6' can be selected from oxides, nitrides or oxygen-nitrogen compounds, and the reactive gases corresponding to silicon oxides can be SiH ₄ , N ₂ O; the corresponding gases of nitrides or oxygen-nitrogen compounds are SiH ₄ , NH ₃ , N ₂ or SiH ₂ Cl ₂ , NH ₃ , N ₂ ; the protective layer 6 ′ can also use Al ₂ O ₃ , or a double-layer protective structure.

After depositing the gate insulating layer 4, the metal oxide semiconductor layer 5' and the protective layer 6', a second photolithography process is performed to form the metal oxide semiconductor pattern 5 and the protective pattern 6. Optionally, the second photolithography process is performed through a half-tone mask process or a gray-tone mask process.

Optionally, a second photolithography process is performed to form the metal oxide semiconductor pattern 5 and the protection pattern 6, which specifically includes:

A photoresist is arranged on the protective layer 6 ′, and a first photoresist pattern 80 is formed by a patterning process, wherein the first photoresist pattern 80 includes a photoresist completely reserved area, a photoresist partially reserved area 81 and a photoresist The photoresist completely removed area 82, the photoresist partially reserved area 81 corresponds to the area where the first via hole 10 and the second via hole 10' will be formed, and the photoresist completely removed area 82 corresponds to the contact via hole 9 of the drain electrode and the pixel electrode and an area of isolation vias 11, wherein the first vias 10 and the second vias 10' are used for contacting the source electrode 7 and the drain electrode 8 with the semiconductor pattern, respectively, and the isolation vias 11 are used for forming metal oxide patterns, That is, it is used to separate the metal oxide pattern from the rest of the metal oxide layer.

The photoresist is etched away to completely remove the protective layer 6', the metal oxide semiconductor layer 5', and the gate insulating layer 4 in the region 82; in this way, the contact vias 9 and isolation vias 11 of the drain electrode and the pixel electrode can be formed , the metal oxide semiconductor pattern 5 and the protection pattern 6 are also formed at the same time.

The photoresist in the partial photoresist reserved area 81 is removed and the photoresist in the completely reserved photoresist area is thinned, and the protective layer 6' in the partially reserved photoresist area 81 is etched away. In this way, the first via hole 10 and the second via hole 10' can be formed.

Further, the projection of the isolation via hole 11 on the base substrate 1 is arranged around the source electrode 7 and the drain electrode 8 . In this way, the isolation via hole 11 can define the metal oxide pattern and isolate the metal oxide pattern from the surrounding metal oxide layer.

S30, deposit a source and drain metal layer on the base substrate 1 on which the metal oxide semiconductor pattern 5 and the protection pattern 6 are formed, and perform a third photolithography process to form the source electrode 7 and the drain electrode 8, and make the The drain electrode 8 is electrically connected to the pixel electrode 2 .

的源漏金属层。源漏金属层可以选用Cr、W、Cu、Ti、Ta、Mo、等金属或合金，由多层金属组成的金属层也能满足需要。通过一次普通的光刻工艺形成源极7、漏极8、及数据线。Specifically, optionally, the substrate substrate 1 on which the metal oxide semiconductor pattern 5 and the protective pattern 6 are formed is sequentially deposited by sputtering or thermal evaporation with a thickness of

source-drain metal layer. The source and drain metal layers can be selected from metals or alloys such as Cr, W, Cu, Ti, Ta, Mo, and the like, and a metal layer composed of multiple layers of metals can also meet the requirements. The source electrode 7, the drain electrode 8, and the data line are formed through a common photolithography process.

Further, in order to make the source electrode 7 and the drain electrode 8 well contact with the metal oxide semiconductor pattern 5, optionally, on the protection pattern 6 and the first via hole 10, the second via hole 10' and the drain and the A source/drain metal layer is deposited in the contact via hole 9 of the pixel electrode, and a third photolithography process is performed, so that the source/drain metal layer deposited in the first via hole 10 and the second via hole 10 ′ forms the source electrode 7 respectively and the drain electrode 8, and the drain electrode 8 and the pixel electrode 2 are electrically connected. Since the first via hole 10 and the second via hole 10' extend through the protective pattern 6 to the metal oxide semiconductor pattern 5, the source electrode 7 and the drain electrode 8 deposited therein can both directly contact the metal oxide semiconductor pattern 5.

In addition, the metal oxide semiconductor layer 5', the transparent conductive layer, the source-drain metal layer and the gate metal layer are all formed by sputtering or thermal evaporation. Further, the gate insulating layer 4 and the protective layer 5' are both deposited and formed by a process of plasma enhanced chemical vapor deposition.

A specific example is given below to illustrate the manufacturing process of the array substrate of this embodiment.

Step 1: forming a pixel electrode 2 and a gate electrode 3 on the base substrate 1, FIG. 2 is a schematic structural diagram of the array substrate in the first state in the manufacturing method of the array substrate provided in the first embodiment of the present invention, as shown in FIG. 2 , the transparent conductive layer and the gate metal layer are sequentially deposited on the base substrate 1 by sputtering or thermal evaporation, and the pixel electrode 2 and the gate electrode 3 are formed after a gray tone or halftone mask lithography process.

Step 2: deposit a gate insulating layer 4, a metal oxide semiconductor layer 5', and a protective layer 6' on the pixel electrode 2 and the gate 3, and coat the photoresist on the protective layer 6', and form through a patterning process The first photoresist pattern 80 . FIG. 3 is a schematic structural diagram of the array substrate in the second state in the manufacturing method of the array substrate provided in the first embodiment of the present invention. On the basis of the array substrate in the first state shown in FIG. 2 , a gate insulating layer 4 , a metal oxide semiconductor layer 5 ′, and a protective layer 6 ′ are sequentially deposited, and a photoresist is coated on the protective layer 6 ′ , through a patterning process, such as exposure and development, the photoresist is formed into a first photoresist pattern 80, wherein the first photoresist pattern 80 includes a photoresist completely reserved area, a photoresist partially reserved area 81 and a photoresist The photoresist completely removed area 82, the photoresist partially reserved area 81 corresponds to the area where the first via hole 10 and the second via hole 10' will be formed, and the photoresist completely removed area 82 corresponds to the contact vias 9 of the drain electrode and the pixel electrode and The region of isolation vias 11 , wherein the first vias 10 and the second vias 10 ′ are used to contact the source electrode 7 and the drain electrode 8 with the semiconductor pattern, respectively, and the isolation vias 11 are used to form the metal-oxide-semiconductor pattern 5 ; Wherein, the photoresist completely reserved area is an area other than the photoresist partially reserved area 81 and the photoresist completely removed area 82 .

After the first photoresist pattern 80 is formed, the array substrate in the second state shown in FIG. 3 is etched by using the modified first photoresist pattern 80 as a mask, and FIG. 4 is the array provided in the first embodiment of the present invention. In the manufacturing method of the substrate, a schematic diagram of the structure of the array substrate after the first etching in the second photolithography process; as shown in FIG. The oxide semiconductor layer 5 ′ and the gate insulating layer 4 form contact vias 9 and isolation vias 11 for the drain electrode and the pixel electrode. Since the isolation via holes 11 are arranged around the source electrode 7 and the drain electrode 8, after this process, the metal oxide semiconductor pattern 5 and the protection pattern 6 are also formed.

5 is a schematic structural diagram of the array substrate after the second etching in the second photolithography process in the method for manufacturing the array substrate provided in the first embodiment of the present invention. As shown in FIG. 5 , an ashing process is then performed on the first photoresist pattern 80 to remove the photoresist in the photoresist partially reserved area 81 and thin the photoresist in the photoresist completely reserved area to etch away the photoresist. The resist partially retains the protective layer 6' in the region 81 to form the first via hole 10 and the second via hole 10'.

The photoresist is then stripped.

Step 3: A source-drain metal film is deposited on the array substrate after stripping the photoresist by sputtering or thermal evaporation, and a source electrode 7, a drain electrode 8, and a data line are formed by a common photolithography process. FIG. 6 is a schematic structural diagram of an array substrate in the manufacturing method of the array substrate provided by the first embodiment of the present invention, and FIG. 7 is a top view of the array substrate in the manufacturing method of the array substrate provided by the first embodiment of the present invention, as shown in FIGS. 6 and 7 . , the drain electrode 8 is deposited in the second via hole 10 ′ and the contact via hole 9 of the drain electrode and the pixel electrode at the same time, so as to realize the electrical connection between the drain electrode 8 and the pixel electrode 2 .

In this embodiment, the manufacturing method of the array substrate includes: sequentially depositing a transparent conductive layer and a gate metal layer on a base substrate, and performing a first photolithography process to form a pixel electrode and a gate; A gate insulating layer, a metal oxide semiconductor layer and a protective layer are deposited on the base substrate of the electrode and the gate, and a second photolithography process is performed to form a metal oxide semiconductor pattern, a protective pattern, source and drain electrodes and Contact via holes of the metal oxide semiconductor pattern, and contact via holes between the drain electrode and the pixel electrode; deposit a source-drain metal layer on the base substrate formed with the metal oxide semiconductor pattern and the protective pattern, and perform the third photolithography process to form the source and drain. By forming the transparent conductive layer under the gate metal layer, the pixel electrode and the gate electrode can be formed simultaneously in the same photolithography process, which is different from the prior art in which the pixel electrode is formed above the planarization layer and the gate electrode is formed on the planar surface. Below the chemical layer, the pixel electrode and gate need to be formed in two photolithography processes, which reduces the number of one photolithography process. In addition, the metal oxide semiconductor pattern and protection pattern are formed by one photolithography process. Compared with the prior art, the number of photolithography processes is reduced again, and the contact via holes of the drain electrode and the pixel electrode are completed in the second photolithography process for forming the metal oxide semiconductor pattern, so the photolithography process is reduced again. Therefore, the photolithography process of the entire array substrate is reduced to three times, the process is simple, and the manufacturing cost is low.

Embodiment 2

FIG. 8 is a schematic structural diagram of an array substrate provided in Embodiment 2 of the present invention. As shown in FIG. 8 , this embodiment provides an array substrate, including a base substrate 1 , a pixel electrode 2 , a gate 3 , a transparent conductive pattern, a gate The electrode insulating layer 4, the metal oxide semiconductor pattern 5, the source electrode 7, the drain electrode 8, and the protection pattern 6, the pixel electrode 2 is arranged on the base substrate 1, the transparent conductive pattern and the pixel electrode 2 are arranged on the same layer, and the gate electrode 3 is arranged on the transparent conductive pattern, the gate insulating layer 4 covers the base substrate 1, and is located on the gate 3 and the pixel electrode 2, and the metal oxide semiconductor pattern 5 and the protection pattern 6 are sequentially stacked and arranged on the gate insulating layer. On the layer 4, at least part of the structure of the source electrode 7 and the drain electrode 8 is arranged on the metal oxide semiconductor pattern 5, the drain electrode 8 is electrically connected to the pixel electrode 2, and the pixel electrode 2 and the gate electrode 3 are in the same photolithography process. form.

Optionally, the array substrate further includes a metal oxide semiconductor layer 5 ′ and a protective layer 6 ′ covering the entire gate insulating layer 4 , and an isolation via hole 11 , and the isolation via hole 11 penetrates through the protection pattern 6 and the metal oxide semiconductor pattern. 5 and the gate insulating layer 4, and the projection of the isolation via hole 11 on the base substrate 1 is arranged around the source electrode 7 and the drain electrode 8, and the metal oxide semiconductor layer 5' and A protective layer 6 ′ is formed as the metal oxide semiconductor pattern 5 and the protective pattern 6 . That is, the isolation via hole 11 is used to isolate the active island shape of the thin film transistor. The depth of the isolation via hole 11 is the same as the depth of the contact via hole 9 between the drain electrode and the pixel electrode, and both penetrate the protective pattern 6 and the metal oxide semiconductor pattern. 5 and the gate insulating layer 4 are provided, so both can be formed in the same photolithography process.

In addition, the protection pattern 6 is provided with a first via hole 10 and a second via hole 10' penetrating the protection pattern 6. The first via hole 10 is used for contacting the source electrode 7 with the metal oxide semiconductor pattern 5, and the second via hole 10 is used to contact the source electrode 7 and the metal oxide semiconductor pattern 5. The hole 10 ′ is used to contact the drain electrode 8 and the metal oxide semiconductor pattern 5 .

The array substrate is also provided with a contact via hole 9 penetrating the protection pattern 6, the metal oxide semiconductor pattern 5, the drain electrode of the gate insulating layer 4 and the pixel electrode. The contact via hole extends to the pixel electrode 2, and a part of the drain electrode 8 metal is located in the contact via hole to electrically connect the drain electrode 8 and the pixel electrode 2 .

FIG. 9 is a schematic structural diagram of an array substrate with another structure provided in Embodiment 2 of the present invention. For the positions of the second via hole 10 ′ and the contact via hole 9 between the drain electrode and the pixel electrode, as shown in FIG. 8 , By keeping the two at a certain distance, as shown in FIG. 9 , the two may be formed into an integrated structure.

In this embodiment, the array substrate includes a base substrate, a pixel electrode, a gate, a transparent conductive pattern, a gate insulating layer, a metal oxide semiconductor pattern, a source electrode, a drain electrode, and a protection pattern, and the pixel electrode is disposed on the base substrate On the top, the transparent conductive pattern and the pixel electrode are arranged on the same layer, the gate is arranged on the transparent conductive pattern, the gate insulating layer covers the substrate with the gate and the pixel electrode, the metal oxide semiconductor pattern and the protective pattern It is sequentially stacked and arranged on the gate insulating layer, at least part of the structure of the source electrode and the drain electrode is arranged on the metal oxide semiconductor pattern, the drain electrode is electrically connected with the pixel electrode, and the pixel electrode and the gate electrode are formed in the same photolithography process . By forming the transparent conductive layer under the gate metal layer, the pixel electrode and the gate electrode can be formed simultaneously in the same photolithography process, which is different from the prior art in which the pixel electrode is formed above the planarization layer and the gate electrode is formed on the planar surface. Below the chemical layer, compared with the case where the pixel electrode and the gate need to be formed in two photolithography processes, the number of one photolithography process is reduced, so the manufacturing process is simple and the manufacturing cost is low.

Embodiment 3

This embodiment provides a display panel, including a color filter substrate, a liquid crystal layer, and the array substrate described in Embodiment 2, wherein the liquid crystal layer is sandwiched between the color filter substrate and the array substrate. The specific structure and function of the array substrate have been described in detail in the second embodiment, and thus will not be repeated here.

Another aspect of this embodiment further provides a display device including the above-mentioned display panel. The display device may be a flexible display device. In this embodiment, the display device may be electronic paper, a tablet computer, or a liquid crystal display.

In the description of the present invention, it is to be understood that the terms "center", "length", "width", "thickness", "top", "bottom", "upper", "lower", " "Left", "right", "front", "rear", "vertical", "horizontal", "inner", "outer", "axial", "circumferential" and other indications of orientation or positional relationship are based on the accompanying drawings The illustrated orientation or positional relationship is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the indicated position or the original must have a specific orientation, a specific configuration and operation, and therefore should not be construed as a limitation of the present invention. limit.

In addition, the terms "first" and "second" are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature defined as "first" or "second" may expressly or implicitly include one or more of that feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise expressly and specifically defined.

In the present invention, unless otherwise expressly specified and limited, the terms "installed", "connected", "connected", "fixed", etc. should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection, or It can be a mechanical connection or an electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, and it can make the internal communication of two elements or the interaction relationship between the two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

In the present invention, unless otherwise expressly specified and limited, a first feature "on" or "under" a second feature may include the first and second features in direct contact, or may include the first and second features Not directly but through additional features between them. Also, the first feature being "above", "over" and "above" the second feature includes the first feature being directly above and obliquely above the second feature, or simply means that the first feature is level higher than the second feature. The first feature is "below", "below" and "below" the second feature includes the first feature being directly below and diagonally below the second feature, or simply means that the first feature has a lower level than the second feature.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features thereof can be equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the embodiments of the present invention. scope.

Claims (10)

1. A method for manufacturing an array substrate, comprising: A transparent conductive layer and a gate metal layer are sequentially deposited on the base substrate, and a first photolithography process is performed to form a pixel electrode and a gate electrode; A gate insulating layer, a metal oxide semiconductor layer and a protective layer are sequentially deposited on the base substrate on which the pixel electrode and the gate electrode are formed, and a second photolithography process is performed to form a metal oxide semiconductor pattern and a protective pattern , a contact via hole between the source electrode and the drain electrode and the metal oxide semiconductor pattern, and a contact via hole between the drain electrode and the pixel electrode; A source and drain metal layer is deposited on the base substrate on which the metal oxide semiconductor pattern and the protective pattern are formed, and a third photolithography process is performed to form a source electrode and a drain electrode, and make the drain electrode and the pixel electrode electrical connection. 2 . The method for manufacturing an array substrate according to claim 1 , wherein the second photolithography process is performed by a half-tone mask process or a gray-tone mask process. 3 . 3 . The method for manufacturing an array substrate according to claim 2 , wherein the second photolithography process is performed to form a metal oxide semiconductor pattern, a protection pattern, source and drain electrodes and the metal oxide. 4 . The contact via hole of the object semiconductor pattern, and the contact via hole between the drain electrode and the pixel electrode, specifically include: A photoresist is arranged on the protective layer, and a first photoresist pattern is formed through a patterning process, wherein the first photoresist pattern includes a photoresist completely reserved area, a photoresist partially reserved area, and a photoresist pattern. The photoresist completely removed area, the photoresist partially reserved area corresponds to the area where the first via hole and the second via hole are formed, and the photoresist completely removed area corresponds to the contact via hole and the isolation via hole of the drain electrode and the pixel electrode. a region of holes, wherein the first via hole and the second via hole are used for contacting the source electrode and the drain electrode with the semiconductor pattern, respectively, and the isolation via hole is used for forming a metal oxide pattern; Etching away the protective layer, the metal oxide semiconductor layer, and the gate insulating layer in the photoresist completely removed area; The photoresist in the partially reserved area of the photoresist is removed, the photoresist in the area where the photoresist is completely reserved is thinned, and the protective layer in the partially reserved area of the photoresist is etched away. 4. The method for manufacturing an array substrate according to claim 3, wherein: The projection of the isolation via hole on the base substrate is arranged around the source electrode and the drain electrode. 5 . The method for manufacturing an array substrate according to claim 3 , wherein the source-drain metal layer is deposited on the base substrate on which the metal oxide semiconductor pattern and the protective pattern are formed, and a third photolithography is performed. 6 . process to form the source and drain, including: A source-drain metal layer is deposited on the protection pattern and in the first via hole, the second via hole, and the contact via hole of the drain electrode and the pixel electrode, and a third photolithography process is performed, so that the first via hole is formed. The source and drain metal layers deposited in the via hole and the second via hole respectively form the source electrode and the drain electrode, and electrically connect the drain electrode and the pixel electrode. 6 . The manufacturing method of an array substrate according to claim 1 , wherein the metal oxide semiconductor layer, the transparent conductive layer, the source-drain metal layer and the gate metal layer all pass through 6 . Process deposition by sputtering or thermal evaporation. 7 . The manufacturing method of the array substrate according to claim 6 , wherein the gate insulating layer and the protective layer are both deposited and formed by a process of plasma enhanced chemical vapor deposition. 8 . 8. An array substrate, characterized in that it comprises a base substrate, a pixel electrode, a gate, a transparent conductive pattern, a gate insulating layer, a metal oxide semiconductor pattern, a source electrode, a drain electrode, and a protection pattern, and the pixel The electrode is arranged on the base substrate, the transparent conductive pattern and the pixel electrode are arranged on the same layer, the gate is arranged on the transparent conductive pattern, and the gate insulating layer covers the substrate on the bottom substrate and on the gate electrode and the pixel electrode, the metal oxide semiconductor pattern and the protection pattern are sequentially stacked on the gate insulating layer, the source electrode and the drain electrode are At least part of the structure is disposed on the metal oxide semiconductor pattern, the drain electrode is electrically connected to the pixel electrode, and the pixel electrode and the gate electrode are formed in the same photolithography process. 9 . The array substrate according to claim 8 , further comprising a metal oxide semiconductor layer and a protective layer overlying the gate insulating layer, and an isolation via hole, the isolation via hole passing through the gate insulating layer. 10 . the protection pattern, the metal oxide semiconductor pattern and the gate insulating layer, and the projection of the isolation via on the base substrate surrounds the source and the drain, and is located around the isolation via The metal oxide semiconductor layer and the protective layer within the formed range form the metal oxide semiconductor pattern and the protective pattern. 10. A display panel, comprising a color filter substrate, a liquid crystal layer and the array substrate according to claim 8 or 9, wherein the liquid crystal layer is sandwiched between the color filter substrate and the array substrate.

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