CN110727149A - Display substrate, preparation method and display device - Google Patents
Display substrate, preparation method and display device Download PDFInfo
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- CN110727149A CN110727149A CN201911142721.5A CN201911142721A CN110727149A CN 110727149 A CN110727149 A CN 110727149A CN 201911142721 A CN201911142721 A CN 201911142721A CN 110727149 A CN110727149 A CN 110727149A
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- 238000002360 preparation method Methods 0.000 title abstract description 7
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- 239000000463 material Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000002161 passivation Methods 0.000 claims description 4
- 239000003990 capacitor Substances 0.000 abstract description 30
- 238000003860 storage Methods 0.000 abstract description 25
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- 239000010409 thin film Substances 0.000 description 19
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000010408 film Substances 0.000 description 4
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- 229910052710 silicon Inorganic materials 0.000 description 4
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- 229910052814 silicon oxide Inorganic materials 0.000 description 4
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
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Abstract
The invention provides a display substrate, a preparation method and a display device, wherein the display substrate comprises a substrate, a plurality of pixel units are defined by criss-cross grid lines and data lines on one side of the substrate in a crossed manner, and the display substrate also comprises: the gate electrode receives a gate driving signal of a corresponding GOA unit through a gate line of a pixel unit row where the gate electrode is located; the pull-up electrode is electrically connected with the pull-up node of the GOA unit corresponding to the pixel unit row where the pull-up electrode is located; the pull-up electrode and the gate electrode are separated by at least an insulating layer, and an orthographic projection of at least one of the gate electrode and the gate line on the substrate has an overlapping portion with an orthographic projection of the pull-up electrode on the substrate. The preparation method is suitable for preparing the display substrate. According to the invention, the pull-up electrode is manufactured in the pixel area, and the pull-up electrode and the gate electrode/gate line in the pixel area form part or all of the storage capacitor of the GOA circuit, so that the occupied space of the GOA circuit in the non-display area is effectively reduced, and the display substrate with a narrow frame is favorably realized.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display substrate, a preparation method and a display device.
Background
In general, for a GOA (Gate drive on Array) circuit product, a structure for implementing a Gate driving function is disposed in a non-display area of a display panel. As shown in fig. 1, the display panel includes a display area 31 and a non-display area located at the periphery of the display area, wherein the GOA circuits may be disposed at opposite sides of the display area (double-edge driving), and fig. 1 shows a GOA area 32 located at the non-display area, and the GOA area 32 has a capacitor area 33 therein. In addition, the GOA circuit can also be disposed on one side of the display area (single-side driving). The GOA technology is helpful for realizing a narrow frame, but while realizing a very narrow frame of a display product, the wiring space of the non-display area is greatly compressed, and in order to ensure the screen occupation ratio, the size of the gate driving circuit needs to be further reduced.
Disclosure of Invention
In view of the above-mentioned drawbacks and deficiencies of the prior art, it is desirable to provide a display substrate, a manufacturing method, and a display device.
In a first aspect, the present invention provides a display substrate, including a substrate, wherein a plurality of parallel gate lines and a plurality of parallel data lines are formed on one side of the substrate, and the gate lines and the data lines are insulated from each other and cross to define a plurality of pixel units, and further including:
the gate electrode and the grid line are formed on the same layer, and the grid line of the pixel unit row where the gate electrode and the grid line are located receives the grid driving signal of the corresponding GOA unit;
the pull-up electrode is positioned on one side, provided with the gate electrode, of the substrate base plate, the pull-up electrode and the gate electrode are arranged in different layers, the pull-up electrode and the gate electrode are at least mutually insulated through an insulating layer positioned between the pull-up electrode and the gate electrode, and the pull-up electrode of each row of pixel units is electrically connected with the pull-up node of the GOA unit corresponding to the pixel unit row where the pull-up electrode is positioned;
an orthogonal projection of at least one of the gate electrode and the gate line on the substrate and an orthogonal projection of the pull-up electrode on the substrate have an overlapping portion.
Preferably, an orthographic projection of the pull-up electrode on the substrate is located in an area of an orthographic projection of the gate electrode and/or the gate line on the substrate.
Preferably, each pixel unit further includes a pixel electrode located on a side of the insulating layer away from the substrate, the pull-up electrode and the pixel electrode are disposed in a common layer and are insulated from each other, and a material of the pull-up electrode is the same as a material of the pixel electrode.
Preferably, the pixel unit further includes:
the gate insulating layer is positioned on one side, away from the substrate, of the gate electrode;
the active layer is positioned on one side, away from the substrate, of the gate insulating layer; and the number of the first and second groups,
a source electrode and a drain electrode respectively connected to the active layer;
the insulating layer is arranged on one side of the active layer far away from the substrate, and the insulating layer covers the source electrode, the drain electrode and the active layer.
Preferably, the pixel unit further includes:
the active layer is positioned on one side, close to the substrate, of the gate electrode;
a source electrode and a drain electrode respectively connected to the active layer; and the number of the first and second groups,
a gate insulating layer between the gate electrode and the active layer, the gate insulating layer covering the active layer, the source electrode, and the drain electrode;
the insulating layer is arranged on one side of the gate electrode, which is far away from the substrate base plate.
Preferably, an orthographic projection of the source electrode, the drain electrode and the active layer on the substrate does not coincide with an orthographic projection of the pull-up electrode on the substrate.
Preferably, the insulating layer is a passivation layer or an organic film layer.
In a second aspect, the present invention provides a display device, including the display substrate.
In a third aspect, the present invention provides a method for manufacturing a display substrate, including:
forming a gate metal layer on one side of a substrate, wherein the gate metal layer comprises a gate electrode and a gate line; the gate electrode may be a part of the gate line, or a part extending from the gate line;
forming an insulating layer on one side of the gate electrode, which is far away from the substrate;
forming a pull-up electrode on one side of the insulating layer, which is far away from the substrate, wherein the pull-up electrode is electrically connected with a pull-up node of a GOA unit corresponding to the row where the pull-up electrode is located; wherein,
an orthogonal projection of at least one of the gate electrode and the gate line on the substrate and an orthogonal projection of the pull-up electrode on the substrate have an overlapping portion.
Preferably, the method for manufacturing a display substrate further includes: and forming a pixel electrode on one side of the insulating layer far away from the substrate, wherein the pull-up electrode and the pixel electrode are arranged on the same layer and are insulated from each other.
According to the technical scheme provided by the embodiment of the invention, the pull-up electrode is manufactured in the pixel area, and the pull-up electrode and at least one of the gate electrode/the gate line in the pixel area form part or all of the storage capacitor of the GOA circuit, so that the occupied space of the GOA circuit in the non-display area is effectively reduced, and the display substrate with a narrow frame is favorably realized;
interference influence of the pull-up electrode on the data line and the source and drain electrodes is effectively avoided through the insulating layer;
in the direction vertical to the substrate, the orthographic projection of the source and drain electrodes and the active layer is not overlapped with the orthographic projection of the pull-up electrode, so that the risk of forming coupling capacitance among the pull-up electrode, the source and drain electrodes and the active layer is reduced, and the negative influence of the pull-up electrode on the normal display of a pixel is avoided;
the pull-up electrode and the pixel electrode are arranged on the same layer, so that the frame of the display substrate is extremely narrowed, and the thin design of the display substrate is guaranteed.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments made with reference to the following drawings:
fig. 1 is a schematic structural diagram of a display panel provided in the prior art;
FIG. 2 is a schematic diagram of a basic 4T1C GOA unit;
fig. 3 is a schematic structural diagram of a display substrate according to an embodiment of the invention;
FIG. 4 is a cross-sectional view of portion A-A' of FIG. 3;
FIG. 5 is a cross-sectional view of portion B-B' of FIG. 3;
FIG. 6 is a cross-sectional view of portion C-C' of FIG. 3;
FIG. 7 is a schematic structural diagram of a display substrate according to another embodiment of the present invention;
FIG. 8 is a cross-sectional view of portion A-A' of FIG. 7;
FIG. 9 is a cross-sectional view of portion B-B' of FIG. 7;
fig. 10 is a cross-sectional view of portion C-C' of fig. 7.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
A pixel structure of a general display product includes a Gate (Gate) line for controlling a Thin Film Transistor (TFT) to be turned on, a Data (Data) line for writing a signal, a common electrode, and a pixel electrode. The present invention takes two pixel structures of ADS (Advanced Dimension Switch) type and HADS (High-Advanced Dimension Switch) type as examples respectively, and describes the design of the capacitance of the gate driving circuit in the pixel area in detail.
Fig. 2 shows a basic 4T1C GOA cell structure, which includes four tfts (M1, M2, M3, M4), a storage capacitor Cst, a clock signal terminal CLK, a signal Input terminal Input, a Reset signal terminal Reset, a reference signal terminal VSS, and a signal output terminal Gate output. Wherein, M3 is a transistor for controlling the signal output terminal Gate output to output high level, and the pull-up node PU is the Gate pole of M3, and during the working process of the GOA unit, the clock signal terminal CLK connected to M3 outputs a signal to the signal output terminal Gate output through M3. However, during the research process, the inventors found that the noise generated by the clock signal terminal CLK is coupled to the signal output terminal Gate output through M3 during the pixel holding period, thereby affecting the picture quality, and the noise coupled from the clock signal terminal CLK to the pull-up node PU through M3 can be equivalently expressed as:
wherein, △ VclkA voltage difference of an output signal for a clock signal terminal CLK; c1 is the capacitance value of the storage capacitor Cst; cgs1Is the coupling capacitance between the gate and the source in M1; cgd2Is the coupling capacitance between the gate and the drain in M2; cgs3Is the coupling capacitance between the gate and the source in M3; cgd3Is the coupling capacitance between the gate and the drain in M3. As can be seen from the above equation, the larger the capacity of the storage capacitor Cst, the smaller the noise. However, when the capacity of the storage capacitor Cst is increased, the size of the storage capacitor Cst is also increased, which causes the GOA circuit to occupy more wiring space, which is not favorable for the narrow frame design of the display panel.
Taking the ADS type lcd as an example, as shown in fig. 3 to 6, an embodiment of the invention provides a display substrate, which includes a substrate 11, a plurality of parallel gate lines 12 and a plurality of parallel data lines 13 are formed on one side of the substrate 11, and the gate lines 12 and the data lines 13 are insulated from each other and cross to define a plurality of pixel units. The gate metal layer where the gate line 12 is located further includes a gate electrode 1, and the gate electrode 1 receives a gate driving signal of a corresponding GOA unit through the gate line 12 of the pixel unit row where the gate electrode 1 is located, so as to control the on and off of a thin film transistor of the pixel unit corresponding to the gate electrode 1. It should be noted that the gate electrode 1 may be a part of the gate line 12, or may be a part extending from the gate line 12, which is not limited in the present invention.
A pull-up electrode 2 is also formed on the side of the base substrate 11 on which the gate electrode 1 is provided, the pull-up electrode 2 being arranged in a different layer from the gate electrode 1 and being insulated from each other at least by an insulating layer 3 located therebetween. The pull-up electrode 2 may be provided corresponding to each pixel unit of the display substrate, or may be provided corresponding to only a part of the pixel units of the display substrate, which is not limited in the present invention. The pull-up electrode 2 of each row of pixel units is electrically connected with the pull-up node of the corresponding GOA unit of the row. For example, the pull-up electrodes 2 of each pixel unit are connected to each other and are finally electrically connected to the pull-up nodes of the corresponding GOA units in the row of the pixel unit.
In this embodiment, an orthogonal projection of at least one of the gate electrode 1 and the gate line 12 on the substrate 11 and an orthogonal projection of the pull-up electrode 2 on the substrate 11 have an overlapping portion. The capacitor formed by at least one of the gate electrode 1 and the gate line 12 and the pull-up electrode 2 can be used as part or all of the storage capacitor of the GOA circuit in the row where the GOA circuit is located, so that the occupied space of the GOA circuit in a non-display area is effectively reduced, and the display substrate with a narrow frame is favorably realized.
In this embodiment, it may be further preferable to arrange that an orthographic projection of the pull-up electrode on the substrate is located in a region of an orthographic projection of the gate electrode and/or the gate line on the substrate. Compared with the situation that the orthographic projection of the pull-up electrode on the substrate is partially overlapped with the orthographic projection of the gate electrode and/or the grid line on the substrate, when the orthographic projection of the pull-up electrode on the substrate is positioned in the orthographic projection area of the gate electrode and/or the grid line on the substrate, the GOA storage capacitor with larger capacity can be obtained.
Compared with the prior art in which the storage capacitors of the GOA circuits are all formed in the non-display area, this embodiment can provide enough design space to form storage capacitors with larger capacitance values, and can reduce the noise of the clock signal terminal CLK coupled to the PU point through the transistor M3 while further reducing the space occupied by the non-display area. In addition, on the premise that the storage capacitor of the GOA circuit is already arranged in the non-display area, the capacitor formed by the pull-up electrode, the gate electrode and/or the gate line provided by this embodiment can be used as a complementary capacitor of the storage capacitor of the GOA circuit in the non-display area, so that the storage capacitor of the GOA circuit can be increased without increasing the space occupied by the non-display area, and the noise of the clock signal terminal CLK coupled to the PU point through the transistor M3 can be reduced.
As shown in fig. 3, a dotted line frame shows one of the pixel units, the pixel unit further includes a common electrode line 10, and the pixel electrode 4 and the common electrode 9 which are disposed in different layers and insulated from each other, and the common electrode line 10 is electrically connected to the common electrode 9. The pixel electrode 4 is a slit electrode and is located on the side of the common electrode 9 away from the substrate 11. The common electrode 9 may be a plate electrode or a slit electrode, which is not limited in the present invention.
Referring to fig. 4 to 6, the pixel unit further includes a thin film transistor including an active layer 5, a source electrode 6, and a drain electrode 7, wherein the active layer 5 is connected to the source electrode 6 and the drain electrode 7, respectively, the source electrode 6 is electrically connected to the pixel electrode 4, and the data line 13 is electrically connected to the drain electrode. It is to be understood that the source and drain electrodes of the thin film transistor used in the present invention are symmetrical, so that the source and drain electrodes may be interchanged.
This embodiment will be described by taking a bottom gate thin film transistor as an example. Wherein, the active layer 5 is positioned on one side of the gate electrode 1 far away from the substrate 11 and is respectively connected with the source electrode 6 and the drain electrode 7; the gate electrode 1 is insulated from the active layer 5, the source electrode 6, and the drain electrode 7 by a gate insulating layer 8. The insulating layer 3 is disposed on a side of the active layer 5 remote from the base substrate 11, and the insulating layer 3 covers the source electrode 6, the drain electrode 7, and the active layer 5. The pixel electrode 4 is located on one side of the insulating layer 3 away from the substrate base plate, and the pixel electrode 4 can be electrically connected with the source electrode through a via hole.
In this embodiment, an insulating layer 3 and a gate insulating layer 8 are interposed between the layers of the pull-up electrode 2 and the gate electrode 1.
Embodiments of the present invention include, but are not limited to, for example, the thin film transistor may also be a top gate type thin film transistor or a double gate type thin film transistor. When the thin film transistor is a top gate type thin film transistor, the active layer 5 is positioned on one side of the gate electrode 1 close to the substrate base plate 11, and the active layer is respectively connected with the source electrode 6 and the drain electrode 7; the gate insulating layer 8 is located between the gate electrode 1 and the active layer 5, and the gate insulating layer 8 covers the active layer 5, the source electrode 6, and the drain electrode 7. The insulating layer 3 is provided on the side of the gate electrode 1 remote from the base substrate 11. The pixel electrode 4 is located on one side of the insulating layer 3 away from the substrate base plate, and the pixel electrode 4 can be electrically connected with the source electrode through a via hole. In this embodiment, an insulating layer 3 is interposed between the layers of the pull-up electrode 2 and the gate electrode 1.
In some examples, the pull-up electrode 2 and the pixel electrode 4 are disposed in a common layer and insulated from each other, and the material of the pull-up electrode 2 may be the same as that of the pixel electrode 4. By the design, the complexity of the process can be effectively reduced, and the thickness of the display substrate cannot be increased.
In some examples, the material of the gate insulating layer 8 includes at least one of silicon nitride, silicon oxide, or silicon oxynitride, which is not limited by the present invention; the insulating layer 3 may be a passivation layer, and the material thereof includes one or more of silicon nitride, silicon oxide, or silicon oxynitride, which is not limited in the present invention.
In some examples, the data line 13 may be formed in the same layer as the source and drain electrodes, and the pull-up electrode 2 is separated from the source and drain electrodes by at least the insulating layer 3, so that wiring interference between the pull-up electrode and the data line can be effectively avoided.
Furthermore, the orthographic projections of the source electrode 6, the drain electrode 7 and the active layer 5 on the substrate 11 are not overlapped with the orthographic projection of the pull-up electrode 2 on the substrate 11, so that the risk of forming coupling capacitance among the pull-up electrode, the source and drain electrodes and the active layer is reduced, and the phenomenon that the pull-up electrode has negative influence on normal display of the pixel is avoided. In addition, in the output time of the non-local row signal output end Gateoutput, the pull-up electrode and the gate electrode are both VGL potential, and the coupling or other influences on other electrodes of the pixel cannot be generated.
Next, a HADS type liquid crystal display will be described as an example. As shown in fig. 7 to 10, another embodiment of the present invention provides a display substrate, which includes a substrate 11, wherein a plurality of parallel gate lines 12 and a plurality of parallel data lines 13 are formed on one side of the substrate 11, and the gate lines 12 and the data lines 13 are insulated from each other and cross to define a plurality of pixel units. The gate metal layer where the gate line 12 is located further includes a gate electrode 1, and the gate electrode 1 receives a gate driving signal of a corresponding GOA unit through the gate line 12 of the pixel unit row where the gate electrode 1 is located, so as to control the on and off of a thin film transistor of the pixel unit corresponding to the gate electrode 1. It should be noted that the gate electrode 1 may be a part of the gate line 12, or may be a part extending from the gate line 12, which is not limited in the present invention.
A pull-up electrode 2 is further formed on the side of the substrate 11 on which the gate electrode 1 is provided, and the pull-up electrode 2 is provided in a different layer from the gate electrode 1 and is insulated from each other at least by an insulating layer 3 interposed therebetween. The pull-up electrode 2 may be provided corresponding to each pixel unit of the display substrate, or may be provided corresponding to only a part of the pixel units of the display substrate, which is not limited in the present invention. The pull-up electrode 2 of each row of pixel units is electrically connected with the pull-up node of the corresponding GOA unit of the pixel unit row. For example, the pull-up electrodes 2 of each pixel unit are connected to each other and are finally electrically connected to the pull-up nodes of the corresponding GOA units in the row of the pixel unit.
In this embodiment, an orthogonal projection of at least one of the gate electrode 1 and the gate line 12 on the substrate 11 and an orthogonal projection of the pull-up electrode 2 on the substrate 11 have an overlapping portion. The capacitor formed by at least one of the gate electrode 1 and the gate line 12 and the pull-up electrode 2 can be used as part or all of the storage capacitor of the GOA circuit in the row where the GOA circuit is located, so that the occupied space of the GOA circuit in a non-display area is effectively reduced, and the display substrate with a narrow frame is favorably realized.
In this embodiment, it may be further preferable to arrange that an orthographic projection of the pull-up electrode on the substrate is located in a region of an orthographic projection of the gate electrode and/or the gate line on the substrate. Compared with the situation that the orthographic projection of the pull-up electrode on the substrate is partially overlapped with the orthographic projection of the gate electrode and/or the grid line on the substrate, when the orthographic projection of the pull-up electrode on the substrate is positioned in the orthographic projection area of the gate electrode and/or the grid line on the substrate, the GOA storage capacitor with larger capacity can be obtained.
Compared with the prior art in which the storage capacitors of the GOA circuits are all formed in the non-display area, this embodiment can provide enough design space to form storage capacitors with larger capacitance values, and can reduce the noise of the clock signal terminal CLK coupled to the PU point through the transistor M3 while further reducing the space occupied by the non-display area. In addition, on the premise that the storage capacitor of the GOA circuit is already arranged in the non-display area, the capacitor formed by the pull-up electrode, the gate electrode and/or the gate line provided by this embodiment can be used as a complementary capacitor of the storage capacitor of the GOA circuit in the non-display area, so that the storage capacitor of the GOA circuit can be increased without increasing the space occupied by the non-display area, and the noise of the clock signal terminal CLK coupled to the PU point through the transistor M3 can be reduced.
As shown in fig. 7, a dotted line frame shows one of the pixel units, and the pixel unit further includes a pixel electrode 4 'and a transparent common electrode 9' which are disposed in different layers and insulated from each other. The common electrode 9 ' is a slit electrode, and the common electrode 9 ' is located on a side of the pixel electrode 4 ' away from the substrate 11. The pixel electrode 4' may be a slit electrode or a plate electrode, but the invention is not limited thereto.
Referring to fig. 8 to 10, the pixel unit further includes a thin film transistor including an active layer 5, a source electrode 6, and a drain electrode 7, wherein the active layer 5 is connected to the source electrode 6 and the drain electrode 7, respectively, the source electrode 6 is electrically connected to the pixel electrode 4', and the data line 13 is electrically connected to the drain electrode. It is to be understood that the source and drain electrodes of the thin film transistor used in the present invention are symmetrical, so that the source and drain electrodes may be interchanged.
This embodiment will be described by taking a bottom gate thin film transistor as an example. Wherein, the active layer 5 is positioned on one side of the gate electrode 1 far away from the substrate 11 and is respectively connected with the source electrode 6 and the drain electrode 7; the gate electrode 1 is insulated from the active layer 5, the source electrode 6, and the drain electrode 7 by a gate insulating layer 8. The insulating layer 3 is disposed on a side of the active layer 5 remote from the base substrate 11, and the insulating layer 3 covers the source electrode 6, the drain electrode 7, and the active layer 5. The pixel electrode 4' is located on one side of the insulating layer 3 away from the substrate base plate, and the pixel electrode 4 can be electrically connected with the source electrode through a via hole.
In this embodiment, an insulating layer 3 is interposed between the layers of the pull-up electrode 2 and the gate electrode 1.
The embodiments include but are not limited to this, for example, the thin film transistor may also be a top gate type thin film transistor or a dual gate type thin film transistor, which will not be described in detail.
In some examples, the pull-up electrode 2 and the pixel electrode 4 are disposed in a common layer and insulated from each other, and the material of the pull-up electrode 2 may be the same as that of the pixel electrode 4. By the design, the complexity of the process can be effectively reduced, and the thickness of the display substrate cannot be increased.
In some examples, the material of the gate insulating layer 8 includes at least one of silicon nitride, silicon oxide, or silicon oxynitride, which is not limited by the present invention; the insulating layer 3 may be an organic film layer, and the material thereof may include at least one of polyimide, polyurethane, or polydimethylsiloxane in a solid state, which is not limited in the present invention.
In some examples, the data line 13 may be formed in the same layer as the source and drain electrodes, and the pull-up electrode 2 is separated from the source and drain electrodes by at least the insulating layer 3, so that wiring interference between the pull-up electrode and the data line can be effectively avoided.
Furthermore, the orthographic projections of the source electrode 6, the drain electrode 7 and the active layer 5 on the substrate 11 are not overlapped with the orthographic projection of the pull-up electrode 2 on the substrate 11, so that the risk of forming coupling capacitance among the pull-up electrode, the source and drain electrodes and the active layer is reduced, and the phenomenon that the pull-up electrode has negative influence on normal display of the pixel is avoided. In addition, in the output time of the non-local row signal output end Gateoutput, the pull-up electrode and the gate electrode are both VGL potential, and the coupling or other influences on other electrodes of the pixel cannot be generated.
The method for manufacturing the display substrate according to the embodiment of the present invention is described next. The method for manufacturing the display substrate illustrated in fig. 3 to 6 includes:
forming a gate metal layer on one side of a substrate 11, where the gate metal layer includes a gate electrode 1 and a gate line 12, where the gate electrode 1 may be a part of the gate line 12, or may be a part extending from the gate line 12;
forming an insulating layer 3 on one side of the gate electrode 1 far away from the substrate 11;
and a pull-up electrode 2 is formed on one side of the insulating layer 3, which is far away from the substrate base plate, and the pull-up electrode 2 is electrically connected with a pull-up node of the GOA unit corresponding to the row where the pull-up electrode is located.
In some examples, the method of making further comprises: a common electrode line 10 and a common electrode 9 connected to the common electrode line 10 are formed on one side of the substrate 11 on which the gate line 12 is disposed, wherein the common electrode 9, the common electrode line 10 and the gate metal layer are formed on the same layer.
In some examples, after forming the gate metal layer and before forming the insulating layer 3, the preparation method further includes:
forming a gate insulating layer 8 on one side of the gate electrode 1 away from the substrate 11;
forming an active layer 5 on one side of the gate insulating layer 8 away from the substrate base plate 11;
a source electrode 6 and a drain electrode 7 are formed on the side of the active layer 5 remote from the base substrate 11 and at opposite ends of the active layer 5.
Next, forming an insulating layer 3 covering the source electrode 6, the drain electrode 7, and the active layer 5, and forming a via hole exposing the source electrode 6 on the insulating layer 3;
forming a pull-up electrode 2 and a pixel electrode 4 which are arranged in the same layer and insulated from each other on one side of the insulating layer 3 away from the substrate 11, wherein the pixel electrode 4 is positioned on one side of the common electrode 9 away from the substrate 11;
the pixel electrode 4 is electrically connected to the source electrode 6 via a via hole in the insulating layer 3.
In this embodiment, the orthographic projection of at least one of the gate electrode 1 and the gate line 12 on the substrate 11 and the orthographic projection of the pull-up electrode 2 on the substrate 11 have an overlapping portion, and the capacitance formed by at least one of the gate electrode 1 and the gate line 12 and the pull-up electrode 2 can be used as part or all of the storage capacitance of the GOA circuit in the row where the GOA circuit is located, so that the occupied space of the GOA circuit in a non-display area is effectively reduced, and the display substrate with a narrow frame is facilitated.
In this embodiment, it may be further preferable to arrange that an orthographic projection of the pull-up electrode on the substrate is located in a region of an orthographic projection of the gate electrode and/or the gate line on the substrate. Compared with the situation that the orthographic projection of the pull-up electrode on the substrate is partially overlapped with the orthographic projection of the gate electrode and/or the grid line on the substrate, when the orthographic projection of the pull-up electrode on the substrate is positioned in the orthographic projection area of the gate electrode and/or the grid line on the substrate, the GOA storage capacitor with larger capacity can be obtained.
In this embodiment, it may be further preferable that the orthographic projection of the source electrode 6, the drain electrode 7, and the active layer 5 on the substrate 11 is not overlapped with the orthographic projection of the pull-up electrode 2 on the substrate 11, so as to reduce the risk of forming coupling capacitance between the pull-up electrode and the source/drain electrode, and between the pull-up electrode and the active layer, and avoid the negative influence of the pull-up electrode on the normal display of the pixel.
The thin film transistor implemented in this embodiment is a bottom gate type thin film transistor. Of course, the top gate thin film transistor may also be formed by changing the order of film formation, which is not described in detail.
The method of manufacturing the display substrate illustrated in fig. 7 to 10 includes:
forming a gate metal layer on one side of a substrate 11, where the gate metal layer includes a gate electrode 1 and a gate line 12, where the gate electrode 1 may be a part of the gate line 12, or may be a part extending from the gate line 12;
forming an insulating layer 3 on one side of the gate electrode 1 far away from the substrate 11;
and a pull-up electrode 2 is formed on one side of the insulating layer 3, which is far away from the substrate base plate, and the pull-up electrode 2 is electrically connected with a pull-up node of the GOA unit corresponding to the row where the pull-up electrode is located.
In some examples, after forming the gate metal layer and before forming the insulating layer 3, the preparation method further includes:
forming a gate insulating layer 8 on one side of the gate electrode 1 away from the substrate 11;
forming an active layer 5 on one side of the gate insulating layer 8 away from the substrate base plate 11;
a source electrode 6 and a drain electrode 7 are formed on the side of the active layer 5 remote from the base substrate 11 and at opposite ends of the active layer 5.
Next, forming an insulating layer 3 covering the source electrode 6, the drain electrode 7, and the active layer 5, and forming a via hole exposing the source electrode 6 on the insulating layer 3;
a pull-up electrode 2 and a pixel electrode 4' which are disposed in the same layer and insulated from each other are formed on the insulating layer 3, and the pixel electrode 4 is electrically connected to the source electrode 6 through a via hole on the insulating layer 3.
Then, an interlayer insulating layer 14 is formed on the side of the pixel electrode 4' away from the substrate 11;
the common electrode 9 ' is formed on a side of the interlayer insulating layer 14 away from the substrate 11, and the pull-up electrode 2 and the pixel electrode 4 ' are insulated and separated from the common electrode 9 ' by the interlayer insulating layer 14, and the interlayer insulating layer 14 is a passivation layer made of one or more materials selected from silicon nitride, silicon oxide, and silicon oxynitride, which is not limited in the present invention.
In this embodiment, the orthographic projection of at least one of the gate electrode 1 and the gate line 12 on the substrate 11 and the orthographic projection of the pull-up electrode 2 on the substrate 11 have an overlapping portion, and the capacitance formed by at least one of the gate electrode 1 and the gate line 12 and the pull-up electrode 2 can be used as part or all of the storage capacitance of the GOA circuit in the row where the GOA circuit is located, so that the occupied space of the GOA circuit in a non-display area is effectively reduced, and the display substrate with a narrow frame is facilitated.
In this embodiment, it may be further preferable to arrange that an orthographic projection of the pull-up electrode on the substrate is located in a region of an orthographic projection of the gate electrode and/or the gate line on the substrate. Compared with the situation that the orthographic projection of the pull-up electrode on the substrate is partially overlapped with the orthographic projection of the gate electrode and/or the grid line on the substrate, when the orthographic projection of the pull-up electrode on the substrate is positioned in the orthographic projection area of the gate electrode and/or the grid line on the substrate, the GOA storage capacitor with larger capacity can be obtained.
In this embodiment, it may be further preferable that the orthographic projection of the source electrode 6, the drain electrode 7, and the active layer 5 on the substrate 11 is not overlapped with the orthographic projection of the pull-up electrode 2 on the substrate 11, so as to reduce the risk of forming coupling capacitance between the pull-up electrode and the source/drain electrode, and between the pull-up electrode and the active layer, and avoid the negative influence of the pull-up electrode on the normal display of the pixel.
The thin film transistor implemented in this embodiment is a bottom gate type thin film transistor. Of course, the top gate thin film transistor may also be formed by changing the order of film formation, which is not described in detail.
The embodiment of the invention also provides a display device which comprises the display substrate provided by any one of the embodiments. The display device may be a mobile phone, a tablet computer, a notebook computer, a television, a monitor, a digital camera, etc.
The foregoing description is only exemplary of the preferred embodiments of the invention and is illustrative of the principles of the technology employed. It will be appreciated by those skilled in the art that the scope of the invention is not limited to the specific combination of the above-mentioned features, but also encompasses other embodiments in which any combination of the above-mentioned features or their equivalents is possible without departing from the inventive concept. For example, the above features and (but not limited to) features having similar functions disclosed in the present invention are mutually replaced to form the technical solution.
Claims (10)
1. A display substrate comprises a substrate base plate, wherein a plurality of parallel grid lines and a plurality of parallel data lines are formed on one side of the substrate base plate, the grid lines and the data lines are mutually insulated and cross to define a plurality of pixel units, and the display substrate is characterized by further comprising:
the gate electrode and the grid line are formed on the same layer, and the grid line of the pixel unit row where the gate electrode and the grid line are located receives the grid driving signal of the corresponding GOA unit;
the pull-up electrode is positioned on one side, provided with the gate electrode, of the substrate base plate, the pull-up electrode and the gate electrode are arranged in different layers, the pull-up electrode and the gate electrode are at least mutually insulated through an insulating layer positioned between the pull-up electrode and the gate electrode, and the pull-up electrode of each row of pixel units is electrically connected with the pull-up node of the GOA unit corresponding to the pixel unit row where the pull-up electrode is positioned;
an orthogonal projection of at least one of the gate electrode and the gate line on the substrate and an orthogonal projection of the pull-up electrode on the substrate have an overlapping portion.
2. The display substrate of claim 1, wherein an orthographic projection of the pull-up electrode on the substrate is located within a region of an orthographic projection of the gate electrode and/or the gate line on the substrate.
3. The display substrate according to claim 1, wherein each pixel unit further comprises a pixel electrode located on a side of the insulating layer away from the substrate, the pull-up electrode and the pixel electrode are arranged in a common layer and are insulated from each other, and a material of the pull-up electrode is the same as a material of the pixel electrode.
4. The display substrate of claim 1, wherein the pixel cell further comprises:
the gate insulating layer is positioned on one side, away from the substrate, of the gate electrode;
the active layer is positioned on one side, away from the substrate, of the gate insulating layer; and the number of the first and second groups,
a source electrode and a drain electrode respectively connected to the active layer;
the insulating layer is arranged on one side of the active layer far away from the substrate, and the insulating layer covers the source electrode, the drain electrode and the active layer.
5. The display substrate of claim 1, wherein the pixel cell further comprises:
the active layer is positioned on one side, close to the substrate, of the gate electrode;
a source electrode and a drain electrode respectively connected to the active layer; and the number of the first and second groups,
a gate insulating layer between the gate electrode and the active layer, the gate insulating layer covering the active layer, the source electrode, and the drain electrode;
the insulating layer is arranged on one side of the gate electrode, which is far away from the substrate base plate.
6. The display substrate according to claim 4 or 5, wherein an orthographic projection of the source electrode, the drain electrode and the active layer on the base substrate does not coincide with an orthographic projection of the pull-up electrode on the base substrate.
7. The display substrate according to any one of claims 1 to 5, wherein the insulating layer is a passivation layer or an organic film layer.
8. A display device comprising the display substrate according to any one of claims 1 to 7.
9. A method for preparing a display substrate is characterized by comprising the following steps:
forming a gate metal layer on one side of a substrate, wherein the gate metal layer comprises a gate electrode and a gate line; the gate electrode may be a part of the gate line, or a part extending from the gate line;
forming an insulating layer on one side of the gate electrode, which is far away from the substrate;
forming a pull-up electrode on one side of the insulating layer, which is far away from the substrate, wherein the pull-up electrode is electrically connected with a pull-up node of a GOA unit corresponding to the row where the pull-up electrode is located; wherein,
an orthogonal projection of at least one of the gate electrode and the gate line on the substrate and an orthogonal projection of the pull-up electrode on the substrate have an overlapping portion.
10. The method for manufacturing a display substrate according to claim 8, further comprising: and forming a pixel electrode on one side of the insulating layer far away from the substrate, wherein the pull-up electrode and the pixel electrode are arranged on the same layer and are insulated from each other.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111312770A (en) * | 2020-02-24 | 2020-06-19 | 京东方科技集团股份有限公司 | Display substrate, method for manufacturing the same, and display device |
| CN111323984A (en) * | 2020-03-25 | 2020-06-23 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
| CN112051692A (en) * | 2020-05-30 | 2020-12-08 | 京东方科技集团股份有限公司 | Display substrate, driving method and maintenance method thereof, display panel and display device |
| CN113724595A (en) * | 2021-08-30 | 2021-11-30 | 京东方科技集团股份有限公司 | Display panel |
| WO2024183540A1 (en) * | 2023-03-09 | 2024-09-12 | 京东方科技集团股份有限公司 | Display panel and display apparatus |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202332230U (en) * | 2011-11-25 | 2012-07-11 | 京东方科技集团股份有限公司 | Shift register, gate drive circuit and liquid crystal display device thereof |
| US20130300775A1 (en) * | 2012-05-10 | 2013-11-14 | Samsung Display Co., Ltd. | Electrowetting display device |
| CN105607362A (en) * | 2016-01-04 | 2016-05-25 | 京东方科技集团股份有限公司 | Shifting register unit, grid driving circuit and display base plate |
| CN106023944A (en) * | 2016-08-03 | 2016-10-12 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
| CN109416902A (en) * | 2017-04-13 | 2019-03-01 | 京东方科技集团股份有限公司 | Gate driver circuit and touch-sensitive display panel in shift-register circuit and its driving method, array substrate |
| US20190245095A1 (en) * | 2016-10-19 | 2019-08-08 | Sharp Kabushiki Kaisha | Tft substrate |
-
2019
- 2019-11-20 CN CN201911142721.5A patent/CN110727149B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202332230U (en) * | 2011-11-25 | 2012-07-11 | 京东方科技集团股份有限公司 | Shift register, gate drive circuit and liquid crystal display device thereof |
| US20130300775A1 (en) * | 2012-05-10 | 2013-11-14 | Samsung Display Co., Ltd. | Electrowetting display device |
| CN105607362A (en) * | 2016-01-04 | 2016-05-25 | 京东方科技集团股份有限公司 | Shifting register unit, grid driving circuit and display base plate |
| CN106023944A (en) * | 2016-08-03 | 2016-10-12 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
| US20190245095A1 (en) * | 2016-10-19 | 2019-08-08 | Sharp Kabushiki Kaisha | Tft substrate |
| CN109416902A (en) * | 2017-04-13 | 2019-03-01 | 京东方科技集团股份有限公司 | Gate driver circuit and touch-sensitive display panel in shift-register circuit and its driving method, array substrate |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111312770A (en) * | 2020-02-24 | 2020-06-19 | 京东方科技集团股份有限公司 | Display substrate, method for manufacturing the same, and display device |
| CN111312770B (en) * | 2020-02-24 | 2022-09-16 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method thereof and display device |
| CN111323984A (en) * | 2020-03-25 | 2020-06-23 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
| CN112051692A (en) * | 2020-05-30 | 2020-12-08 | 京东方科技集团股份有限公司 | Display substrate, driving method and maintenance method thereof, display panel and display device |
| CN113724595A (en) * | 2021-08-30 | 2021-11-30 | 京东方科技集团股份有限公司 | Display panel |
| CN113724595B (en) * | 2021-08-30 | 2023-10-13 | 京东方科技集团股份有限公司 | display panel |
| WO2024183540A1 (en) * | 2023-03-09 | 2024-09-12 | 京东方科技集团股份有限公司 | Display panel and display apparatus |
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|---|---|
| CN110727149B (en) | 2022-08-23 |
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