CN110718587B - Semiconductor device and manufacturing method - Google Patents

Abstract

The semiconductor device and the fabrication method provided by the embodiments of the present application. The semiconductor device includes: a substrate; a semiconductor layer arranged on the substrate; a first electrode and a second electrode arranged on the side of the semiconductor layer away from the substrate; a surface passivation dielectric layer on one side of the substrate and located between the first electrode and the second electrode; and a surface passivation dielectric layer disposed on the side of the semiconductor layer away from the substrate, located between the first electrode and the substrate An isolation layer between the surface passivation medium layers for isolating the first electrode and the surface passivation medium layer. The surface passivation dielectric layer is isolated from the first electrode by the isolation layer, which can effectively inhibit the formation of NiSi compounds, improve the quality of the Schottky junction of the first electrode, reduce leakage and improve the reliability of the device.

Description

Semiconductor device and manufacturing method

technical field

The present application relates to the technical field of semiconductors and semiconductor manufacturing, and in particular, to a semiconductor device and a manufacturing method.

Background technique

The reliability requirements of high electron mobility devices, which are widely used in the fields of radio frequency, microwave and power electronics, are relatively high. In particular, the study of high temperature, high frequency, high voltage and high power device reliability has become one of the current research hotspots in the field of semiconductor devices. For example, gallium nitride high electron mobility devices and gallium arsenide high electron mobility devices, etc., the process design of the metal electrode in contact with the semiconductor layer Schottky is related to the reliability of the electronic device. Because the performance of the metal electrode is mainly affected by the electric field at the edge of the electrode and the ambient temperature, the performance of the metal electrode of the electronic device is easily degraded, and the Schottky leakage becomes larger, which inhibits the pressure bearing capacity of the electronic device.

In the prior art, a nickel-gold-NiAu metal lamination process is often used to form a good Schottky contact with the semiconductor interface. In order to improve the quality of the semiconductor surface, a surface passivation layer of silicide, such as silicon nitride (SiN), is often used. However, Ni-Ni and silicon nitride contact easily to form Ni silicide NiSi. The work function of NiSi is lower than that of metal Ni and will reduce the dielectric constant of the original silicon nitride, resulting in the Schottky performance of the metal electrode. If it is reduced, the leakage of the metal electrode will increase, and even lead to the failure of the metal electrode, which seriously affects the reliability of the device.

Therefore, how to isolate the Ni in the metal electrode and the surface passivation dielectric layer, while still ensuring high-quality Schottky contact and passivation performance of the semiconductor surface, is a technical problem that needs to be solved urgently.

SUMMARY OF THE INVENTION

In view of this, the purpose of the present application is to provide a semiconductor device and a method for fabricating the semiconductor device to solve the above problems.

In a first aspect, embodiments of the present application provide a semiconductor device, the semiconductor device comprising:

substrate;

a semiconductor layer disposed on the substrate;

a first electrode and a second electrode disposed on the side of the semiconductor layer away from the substrate;

a surface passivation dielectric layer disposed on the side of the semiconductor layer away from the substrate and between the first electrode and the second electrode; and

An isolation layer is provided on the side of the semiconductor layer away from the substrate and located between the first electrode and the surface passivation medium layer for isolating the first electrode and the surface passivation medium layer.

Optionally, in this embodiment, the height of the isolation layer in the direction perpendicular to the semiconductor layer is greater than the height of the passivation medium layer in the direction perpendicular to the semiconductor layer.

Optionally, in this embodiment, the width of the isolation layer between the first electrode and the surface passivation dielectric layer is not less than 50 nm.

Optionally, in this embodiment, the isolation layer extends toward the first electrode at a position close to the semiconductor layer, so as to reduce the contact surface between the first electrode and the semiconductor layer.

Optionally, in this embodiment, the isolation layer extends completely toward the first electrode at a position close to the semiconductor layer, and the isolation layer completely extends between the first electrode and the semiconductor layer. isolation.

Optionally, a thickness of a portion of the isolation layer extending toward the first electrode at a position close to the semiconductor layer ranges from 5 nm to 50 nm.

Optionally, the isolation layer and the semiconductor layer form a PN junction.

Optionally, in this embodiment, the isolation layer is made of a P-type semiconductor material, and the P-type semiconductor material includes P-GaN and P-AlGaN.

Optionally, in this embodiment, the material of the first electrode is Ni or Ni/Au, or a combination of Ni and single or multiple metals.

Optionally, in this embodiment, the material of the surface passivation layer is one or more of SiN, SiO2, SiON, and Al2O3.

Optionally, in this embodiment, the semiconductor device is a diode, the first electrode is an anode of the diode, the second electrode is a cathode of the diode, and the surface passivation dielectric layer is provided on between the anode and the cathode.

Optionally, in this embodiment, the semiconductor device is a triode, the first electrode is the gate of the triode, the second electrode is the source and drain of the triode, and the surface is blunt. A dielectric layer is disposed between the source electrode and the gate electrode and between the drain electrode and the gate electrode.

In a second aspect, an embodiment of the present application further provides a method for fabricating a semiconductor device, the method comprising:

providing a substrate;

sequentially depositing semiconductor layers including a first semiconductor layer and a second semiconductor layer on one side of the substrate;

forming an isolation layer on a side of the semiconductor layer away from the substrate;

Removing a specified portion of the isolation layer through an etching process, leaving the isolation layer for Schottky with the first electrode;

forming a second electrode in ohmic contact with the semiconductor layer on a side of the semiconductor layer away from the substrate;

The first electrode is formed in the isolation layer or between the isolation layer and the semiconductor layer, wherein the first electrode is in Schottky contact with the isolation layer or the semiconductor layer;

A surface passivation dielectric layer is formed on the surface of the semiconductor layer between the isolation layer and the second electrode.

The semiconductor device and the fabrication method provided by the embodiments of the present application. The semiconductor device comprises: a substrate; a semiconductor layer arranged on the substrate; a first electrode and a second electrode arranged on the side of the semiconductor layer away from the substrate; a surface passivation dielectric layer on one side of the substrate and located between the first electrode and the second electrode; and a surface passivation dielectric layer disposed on the side of the semiconductor layer away from the substrate, located between the first electrode and the substrate An isolation layer between the surface passivation medium layers for isolating the first electrode and the surface passivation medium layer. The surface passivation dielectric layer is isolated from the first electrode by the isolation layer, which can effectively inhibit the formation of NiSi compounds, improve the quality of the Schottky junction of the first electrode, reduce leakage and improve the reliability of the device.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present application more clearly, the accompanying drawings required in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation of the scope. Other related figures are obtained from these figures.

FIG. 1 is a schematic structural diagram of a first semiconductor device provided by an embodiment of the present application;

FIG. 2 is a schematic structural diagram of a second semiconductor device according to an embodiment of the present application;

FIG. 3 is a schematic structural diagram of a third semiconductor device according to an embodiment of the present application;

FIG. 4 is a schematic structural diagram of a fourth semiconductor device provided by an embodiment of the present application;

FIG. 5 is a process flow diagram of a semiconductor device provided by an embodiment of the present application;

6A-6E are process diagrams of the semiconductor device provided by the present embodiment.

Icon: 11-substrate; 12-semiconductor layer; 121-first semiconductor layer; 122-second semiconductor layer; 123-two-dimensional electron gas; 13-first electrode; 14-second electrode; 15-surface passivation Dielectric layer; 16-isolation layer.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. The components of the embodiments of the present application generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations.

Thus, the following detailed description of the embodiments of the application provided in the accompanying drawings is not intended to limit the scope of the application as claimed, but is merely representative of selected embodiments of the application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

It should be noted that like numerals and letters refer to like items in the following figures, so once an item is defined in one figure, it does not require further definition and explanation in subsequent figures.

In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", etc. is based on the orientation or positional relationship shown in the accompanying drawings, or is usually placed when the product of the invention is used. The orientation or positional relationship is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Furthermore, the terms "first", "second", etc. are only used to differentiate the description and should not be construed to indicate or imply relative importance.

With the development of semiconductor device technology, the third-generation wide-bandgap semiconductor device technology with high frequency, high voltage and high reliability has gradually become the core technology of current semiconductor equipment systems. High-quality Schottky junction or MIS (metal-insulator-semiconductor) gate is one of the key technologies for obtaining low leakage and high reverse breakdown voltage characteristics, and it has also become the basic basis for judging the quality of semiconductor devices. Although various techniques for improving the gate quality of the device Schottky junction or MIS structure, and for improving reverse leakage and breakdown voltage have been reported in the field of semiconductor technology, there is still much room for further optimization.

Therefore, how to further suppress the degradation of the gate performance of the Schottky junction or the MIS structure, improve its reliability, reduce the leakage current under the reverse bias voltage of the semiconductor device, and improve the withstand voltage characteristics has become an urgent technical problem to be solved.

In order to solve the above problems, the embodiments of the present application provide a semiconductor device as described below. The semiconductor device includes: a substrate;

a semiconductor layer disposed on the substrate;

a first electrode and a second electrode disposed on the side of the semiconductor layer away from the substrate;

a surface passivation dielectric layer disposed on the side of the semiconductor layer away from the substrate and between the first electrode and the second electrode; and

The isolation layer is arranged on the side of the semiconductor layer away from the substrate, and is located between the first electrode and the surface passivation medium layer for isolating the first electrode and the surface passivation medium layer.

Please refer to FIG. 1 , which is a schematic diagram of a first structure of a semiconductor device provided by an embodiment of the present application. The semiconductor device is a triode, and the semiconductor device includes a substrate 11 , a semiconductor layer 12 , a first electrode 13 , a second electrode 14 , a surface passivation medium layer 15 and an isolation layer 16 .

The material of the substrate 11 can be gallium nitride, silicon, sapphire, silicon nitride, aluminum nitride, SOI (Silicon-On-Insulator, silicon on insulating substrate) or other materials that can epitaxially grow III-V nitrides. Material.

The semiconductor layer 12 includes a first semiconductor layer 121 and a second semiconductor layer 122 . The first semiconductor layer 121 is located on the side of the substrate 11. It can be understood that, between the first semiconductor layer 121 and the substrate 11, one of a nucleation layer, a buffer layer or a back barrier layer can also be formed by sequentially depositing or a combination of multiple layers. The embodiments of the present application do not limit the specific structure between the substrate 11 and the first semiconductor layer 121 .

The second semiconductor layer 122 is located on the side of the first semiconductor layer 121 away from the substrate 11 , the forbidden band width of the first semiconductor layer 121 is smaller than that of the second semiconductor layer 122 , and the material of the first semiconductor layer 121 may be It is gallium nitride (GaN), the material of the second semiconductor layer 122 may be aluminum gallium nitride (AlGaN), and a two-dimensional electron gas 123 is formed at the interface between the first semiconductor layer 121 and the second semiconductor layer 122 .

The isolation layer 16 is located on the surface of the second semiconductor layer 122 away from the substrate 11. The material of the isolation layer 16 may be a P-type material, P-nitride, which is electrically opposite to the first semiconductor layer 121 and the second semiconductor layer 122. Gallium or P-AlGaN. In this embodiment, the isolation layer 16 and the second semiconductor layer 122 form a groove.

In this semiconductor device structure, the first electrode 13 is a gate electrode, and the second electrode 14 includes a source electrode of a triode and a drain electrode of the triode. The source electrode of the triode and the drain electrode of the triode are disposed on opposite sides of the second semiconductor layer 122 .

The first electrode 13 is disposed in the groove formed by the isolation layer 16 and the second semiconductor layer 122. It is understood that the surface of the first electrode 13 and/or the isolation layer 16 near the substrate side may extend to the second semiconductor layer 122 Inside, the first electrode 13 is in Schottky contact with the isolation layer 16 or/and the second semiconductor layer 122, respectively. The first electrode may be formed of a metal stack such as Ni, Ni/Au or Ni/Au/Ti.

The surface passivation dielectric layer 15 is located on the second semiconductor layer 122 between the isolation layer 16 and the source electrode, and between the isolation layer 16 and the drain electrode. Wherein, the material of the surface passivation dielectric layer 15 may be a silicide dielectric, for example, SiN, SiO2, and the like.

The height of the isolation layer 16 in the direction perpendicular to the semiconductor layer 12 is higher than the height of the surface passivation dielectric layer 15 , preferably, the height in the direction perpendicular to the semiconductor layer 12 is at least 5 nm higher. Setting the height of the isolation layer 16 higher than the surface passivation medium layer 15 can prevent the surface passivation medium layer 15 from contacting the first electrode.

In the embodiment of the present application, the isolation layer 16 is made of P-gallium nitride or P-aluminum gallium nitride, which can effectively isolate the contact between the surface passivation dielectric layer 15 and the first electrode 13 . Further, in this embodiment, the width of the isolation layer 16 between the first electrode 13 and the surface passivation dielectric layer 15 is not less than 50 nm. The above arrangement can ensure that the isolation layer 16 sufficiently isolates the first electrode 13 from the surface passivation dielectric layer 15 . In order to prevent the Ni metal element in the first electrode 13 and the Si element in the surface passivation dielectric layer 15 from reacting to form a compound NiSi, the formation of the NiSi compound is suppressed, and the Schottky junction formed by the first electrode 13 and the semiconductor layer 12 is improved. quality, reduce leakage and improve device reliability. At the same time, since the P-type isolation layer 16 also forms a PN junction with the second semiconductor layer 12 , the Schottky junction or electron leakage at the interface between the first electrode edge and the second semiconductor layer 12 can be effectively suppressed, and the first electrode 13 can be further improved. quality, reduce leakage, and improve the pressure-bearing capacity of semiconductor devices.

Referring to FIG. 2 , FIG. 2 shows a schematic diagram of a second structure of the semiconductor device provided by the embodiment of the present application.

The structure of the second semiconductor device is still a triode structure. The difference from the first structure is that in the second structure of the semiconductor device, the isolation layer 16 faces the first electrode in a direction parallel to the semiconductor layer at a position close to the semiconductor layer 12. 13 is extended, and the part of the isolation layer 16 extending toward the first electrode 13 is in Schottky contact with the surface of the first electrode 13 in contact with the extended part. In this embodiment, the isolation layer 16 extends toward the first electrode 13 at a position close to the semiconductor layer 12 to reduce the contact surface between the first electrode 13 and the semiconductor layer 12 . The portion of the isolation layer 16 extending toward the first electrode 13 is not isolated to completely isolate the first electrode.

The advantage of the second semiconductor device structure improvement is that the extension of the isolation layer 16 relative to the first electrode 13 and the second semiconductor layer 122 will form a PN junction, so that the leakage of electrons on the first electrode 13 can be better suppressed. Compared with the first structure, the leakage current of the Schottky junction formed by the first electrode 13 and the semiconductor layer 12 can be further reduced on the basis of ensuring that the performance degradation of the first electrode 13 is suppressed, and the pressure bearing capability of the entire semiconductor device can be improved.

Please refer to FIG. 3 , which shows a third schematic structural diagram of a semiconductor device provided by an embodiment of the present application.

The structure of the third semiconductor device is still a triode structure. Different from the schematic diagram of the second structure, in the semiconductor device structure provided in the third embodiment, the isolation layer 16 faces the first semiconductor layer 12 near the semiconductor layer 12 . The electrode 13 extends to completely isolate the contact between the first electrode 13 and the semiconductor layer 12 . In this structure, the thickness of the isolation layer 16 between the first electrode 13 and the semiconductor layer 12 ranges from 5 nm to 50 nm.

The advantage of the third semiconductor device structure improvement is that the first electrode 13 is completely isolated from the second semiconductor layer 122 and the surface passivation dielectric layer 15 by the isolation layer 16, the isolation layer 16 and the second semiconductor layer 122 form a PN junction, and the third An electrode 13 forms Schottky contact with the isolation layer 16 . Compared with the second semiconductor device structure, on the basis of ensuring that the performance degradation of the first electrode 13 is suppressed, the leakage current of the Schottky junction is further reduced due to the existence of the PN junction, and the pressure bearing capability of the semiconductor device is improved.

Please refer to FIG. 4 , which shows a fourth schematic structural diagram of the semiconductor device provided by the embodiment of the present application.

As shown in FIG. 4 , different from the previous three semiconductor device structures, the fourth semiconductor device structure is a Schottky diode structure, the first electrode 13 corresponds to the anode of the diode, and the second electrode corresponds to the cathode of the diode. The first electrode 13 is effectively isolated from the surface passivation dielectric layer 15 by the isolation layer 16 , and the isolation layer 16 and the second semiconductor layer 122 form a PN junction. The use of the isolation layer 16 in the present invention can improve the anode performance of the Schottky diode device, and improve the pressure bearing capacity and reliability of the Schottky diode.

The embodiment of the present application also provides a method for fabricating a semiconductor device. The following is an example of fabricating the semiconductor device in FIG. 1 for explanation. The method includes the following steps:

In step S501, a substrate 11 is provided.

Step S502 , referring to FIG. 6A , sequentially depositing the semiconductor layer 12 including the first semiconductor layer 121 and the second semiconductor layer 122 on one side of the substrate 11 .

Step S503 , referring to FIG. 6B , an isolation layer 16 is formed on a side of the semiconductor layer 12 away from the substrate 11 .

In step S504 , referring to FIG. 6C , a specified portion of the isolation layer 16 is removed by an etching process, and the isolation layer 16 for contacting the first electrode 13 is reserved.

Step S505 , referring to FIG. 6D , a second electrode 14 in ohmic contact with the semiconductor layer is formed on the side of the semiconductor layer 12 away from the substrate 11 .

Step S506 , referring to FIG. 6E or FIG. 1 , the first electrode 13 is formed in the isolation layer 16 or between the isolation layer 16 and the semiconductor layer 12 , wherein the first electrode 13 is Schottky with the isolation layer 16 or the semiconductor layer 12 base contact;

Step S507 , referring to FIG. 6E or FIG. 1 again, a surface passivation dielectric layer 15 is formed on the surface of the semiconductor layer 12 between the isolation layer 16 and the second electrode 14 .

The semiconductor device and the manufacturing method thereof provided by the embodiments of the present application. The semiconductor device includes: a substrate; and a semiconductor layer disposed on the substrate. A first electrode and a second electrode are provided on the side of the semiconductor layer away from the substrate, wherein the first electrode is in Schottky contact with the semiconductor layer, and the second electrode is in ohmic contact with the semiconductor layer. A surface passivation dielectric layer disposed on the side of the semiconductor layer away from the substrate and between the first electrode and the second electrode. and an isolation layer disposed on the side of the semiconductor layer away from the substrate and between the first electrode and the surface passivation dielectric layer for isolating the first electrode and the surface passivation dielectric layer . The use of an isolation layer (such as P-GaN or P-AlGaN, etc.) to isolate the surface passivation dielectric layer of the silicide from the first electrode containing Ni metal elements can effectively inhibit the formation of NiSi compounds and improve the first electrode. The quality of the Schottky junction formed with the semiconductor layer reduces leakage and improves device reliability. At the same time, since the P-type isolation layer also forms a PN junction with the semiconductor layer, the electron leakage at the interface between the Schottky junction or the edge of the first electrode and the semiconductor layer can also be effectively suppressed, which further improves the quality of the Schottky junction MIS structure and reduces the leakage current. , to improve the pressure bearing capacity of the device.

The above descriptions are only preferred embodiments of the present application, and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this application shall be included within the protection scope of this application.

Claims (11)

1. A semiconductor device, comprising:

a substrate;

a semiconductor layer disposed on the substrate;

the first electrode and the second electrode are arranged on one side of the semiconductor layer, which is far away from the substrate;

the surface passivation dielectric layer is arranged on one side, far away from the substrate, of the semiconductor layer and is positioned between the first electrode and the second electrode; and

the isolation layer is arranged on one side, far away from the substrate, of the semiconductor layer and is positioned between the first electrode and the surface passivation dielectric layer and used for isolating the first electrode from the surface passivation dielectric layer;

the isolation layer and the semiconductor layer form a PN junction, the isolation layer is made of a P-type semiconductor material, and the P-type semiconductor material comprises P-GaN and P-AlGaN.

2. The semiconductor device of claim 1, wherein a height of the isolation layer in a direction perpendicular to the semiconductor layer is greater than a height of the passivation dielectric layer in a direction perpendicular to the semiconductor layer.

3. The semiconductor device according to claim 1, wherein a width of the isolation layer between the first electrode and the surface passivation dielectric layer is not less than 50 nm.

4. The semiconductor device according to claim 1, wherein the isolation layer extends toward the first electrode at a position close to the semiconductor layer to reduce a contact surface of the first electrode with the semiconductor layer.

5. The semiconductor device according to claim 4, wherein the isolation layer extends completely toward the first electrode at a position close to the semiconductor layer, and the first electrode is completely isolated from the semiconductor layer by the isolation layer.

6. The semiconductor device according to claim 4, wherein a thickness of a portion of the isolation layer extending toward the first electrode at a position near the semiconductor layer is in a range of 5nm to 50 nm.

7. The semiconductor device according to claim 1, wherein a material of the first electrode is Ni or Ni/Au, or a combination of Ni and a single or a plurality of metals.

8. The semiconductor device of claim 1, wherein the material of the surface passivation layer is one or more of SiN, SiO2, SiON, Al2O 3.

9. The semiconductor device according to any one of claims 1 to 8, wherein the semiconductor device is a diode, the first electrode is an anode of the diode, the second electrode is a cathode of the diode, and the surface passivation dielectric layer is disposed between the anode and the cathode.

10. The semiconductor device according to any one of claims 1 to 8, wherein the semiconductor device is a transistor, the first electrode is a gate electrode of the transistor, the second electrode is a source electrode and a drain electrode of the transistor, and the surface passivation dielectric layer is provided between the source electrode and the gate electrode and between the drain electrode and the gate electrode.

11. A method of fabricating a semiconductor device, the method comprising:

providing a substrate;

depositing a semiconductor layer comprising a first semiconductor layer and a second semiconductor layer in sequence on one side of the substrate;

forming an isolation layer on one side of the semiconductor layer far away from the substrate;

removing a designated part in the isolation layer through an etching process, and reserving the isolation layer for contacting with the first electrode;

forming a second electrode in ohmic contact with the semiconductor layer on the side far away from the substrate;

forming the first electrode in the isolation layer or between the isolation layer and the semiconductor layer, wherein the first electrode is in schottky contact with the isolation layer or the semiconductor layer;

forming a surface passivation dielectric layer on the surface of the semiconductor layer between the isolation layer and the second electrode;

the isolation layer and the semiconductor layer form a PN junction, the isolation layer is made of a P-type semiconductor material, and the P-type semiconductor material comprises P-GaN and P-AlGaN.

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