CN110708618A - Method for realizing large-capacity line crossing structure - Google Patents
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- H04Q11/0005—Switch and router aspects
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
- H04Q11/0005—Switch and router aspects
- H04Q2011/0052—Interconnection of switches
- H04Q2011/0056—Clos
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
- H04Q11/0005—Switch and router aspects
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Abstract
The invention discloses a method for realizing a high-capacity line crossing structure. The method is realized on a hardware platform based on FPGA, and a cross structure of the method is composed of an input stage and an output stage. The input stage comprises m input stage selection units, each input stage selection unit corresponds to one input signal to be crossed, and m represents the number of paths to be crossed; the output stage comprises m output stage OR units, and each output stage OR unit corresponds to one path of crossed output signals; the input stage and the output stage are connected in sequence according to the unit label sequence, thereby completing the cross function from m-path input to m-path output. The line crossing method provided by the invention has strict non-blocking characteristic, is simple in configuration and easy to operate, can well meet the performance requirement when the m value is increased, namely the crossing capacity is increased, and has wide application value in the technical field of optical crossing.
Description
Technical Field
The invention relates to optical crossing in the field of optical communication, in particular to a method for realizing a high-capacity line crossing structure, which is used for crossing equipment in an optical fiber network node to realize high-capacity line crossing.
Background
Optical cross connect (OXC) is a device for optical network nodes, which can flexibly and efficiently manage optical transmission networks by performing line crossing on optical signals, and is an important means for realizing reliable network protection/restoration and automatic wiring and monitoring. One of the technical difficulties in the field of optical crossing is how to implement large-capacity line crossing. For example, the classic CLOS cross network, proposed by bell laboratories Charles CLOS in 1953, is a three-stage symmetric cross structure that has strict non-blocking properties only under certain conditions. Furthermore, when cross-switching a CLOS network, a complicated method is required to configure the structure. Because the CLOS network routing is not unique, i.e. the output can be generated in various ways, and a newly-built route considers the previously configured route and cannot influence the previously configured route, a high requirement is put on a routing algorithm when the CLOS structure is used. Usually, an FPGA is selected as a hardware platform for implementing the cross structure, because a large number of logic units and flip-flops are arranged in the FPGA, the cross structure is particularly suitable for implementing large-capacity line crossing, but due to strong coupling between various levels of the CLOS cross structure, great congestion is generated when wiring is arranged in the FPGA, so that a time sequence is poor, and thus cross performance is reduced. Therefore, a good realization method for realizing a large-capacity line crossing structure plays a crucial role in the technical field of optical crossing.
Disclosure of Invention
The present invention aims to solve the problems in the above technologies, and provides a simple, operable, strictly non-blocking configuration scheme which has a good timing sequence when implemented on an FPGA and is suitable for large-scale optical fiber cross connection, that is, an implementation method for implementing a large-capacity line cross structure.
The technical scheme adopted by the invention is as follows: a realization method for realizing a high-capacity line crossing structure is realized on a hardware platform based on an FPGA and is characterized in that: the cross structure is composed of an input stage and an output stage;
the input stage comprises m input stage selection units, each input stage selection unit corresponds to input signals to be crossed with the same label, for example, the input stage selection unit m corresponds to input signals im to be crossed, m represents the number of paths to be crossed, each input stage selection unit has m outputs which are distinguished by underlining and labeling, for example, the outputs of the input stage selection unit m are im _0, im _1, and im _ m;
the output stage comprises m output stage or units, each output stage or unit corresponds to a signal output after crossing with the same label, for example, the output stage or unit m corresponds to a signal output after crossing, each output stage or unit has m inputs, which are also distinguished by underlining and marking, for example, the inputs of the output stage or unit m are om _0, om _1, and.
The input stage units and the output stage units are sequentially connected according to the unit number sequence, so as to complete the cross function from m inputs to m outputs, and the description is made from the perspective of the outputs, the output stage unit m corresponds to the crossed output signal om, the 0 th input om _0 of the output stage unit m comes from the m output i0_ m of the input stage selection unit 0, the 1 st input om _1 of the output stage unit m comes from the m output i1_ m of the input stage selection unit 1,... the m th input m of the output stage unit m comes from the m output im _ m of the input stage selection unit m, and in summary, the m inputs of the output stage unit m come from the m outputs of the m input stage selection units respectively;
the specific implementation method of the input stage selection unit is as follows:
the input stage selection unit has 1 input m outputs, and the functional meaning of the input stage selection unit is that an input signal is selected to be output at a plurality of output ports; for example, the input signal is selected to be output at the output port of the r-th path, then the output port of the r-th path has a signal, and the output of 0 at the other output ports has no signal; in order to realize the described function, a parallel processing structure is adopted for a large-capacity line crossing structure, namely an input stage selection unit comprises m judgment equal units, each judgment equal unit has the same function and is responsible for detecting whether a signal is allowed to pass, if the signal is allowed to pass, the signal is output, otherwise, 0 is output, and the signal is not allowed to pass; the input of each judgment equality unit is the same and is the input signal of the input stage selection unit, namely the input signal to be crossed; judging whether the equality unit outputs 0 or the signal depends on the user requirement, namely, what kind of intersection from input to output is realized by the user, for example, the user wants to realize the intersection from input n to output r, then the input signal in is output from the r-th output port of the input stage selection unit n, and the rest output ports output 0;
the specific function of the output stage OR unit is described as follows:
the output stage OR unit has m inputs and 1 output, and the realization function is to OR the m inputs and then output the inputs; it can be seen from the connection relationship between the input stage and each unit of the output stage and the description that only one path of m paths of outputs of each unit of the input stage has a signal and the other paths are 0, that only one path of m paths of inputs of the or unit of each output stage has a signal and all the other paths are 0, so that the or operation is actually to select and output one path of the signal.
The beneficial effects produced by the invention are as follows: 1. the cross connection routing capacity is large, and the method is suitable for large-scale optical fiber cross connection routing configuration. 2. The method has strict non-blocking characteristic, does not have the problem of routing switching failure, and has no any limitation condition. 3. The control method is simple and reliable, and complex routing algorithm is not needed for cooperation. 4. When the structure is realized, only comparison logic and OR logic are used, and selection logic is not used, so that the realization mode is easier to realize on an FPGA, the realization time sequence is better, and overlarge congestion cannot be generated. The method provided by the invention has wide application value in the technical field of optical cross.
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FIG. 1 is a block diagram of the present invention for implementing large capacity line crossing;
FIG. 2 is a schematic diagram of an implementation of an input stage selection unit according to the present invention;
FIG. 3 is a cross-sectional diagram of implementation of i0- > o3, i1- > o0, i2- > o1, i3- > o2 according to the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings:
FIG. 1 is a structural diagram of the present invention for realizing large-capacity line crossing, which is composed of two stages, i.e., an input stage and an output stage; the input stage comprises m input stage selection units, each input stage selection unit corresponds to input signals to be crossed with the same label, for example, the input stage selection unit m corresponds to input signals im to be crossed, m represents the number of paths to be crossed, each input stage selection unit has m outputs which are distinguished by underlining and labeling, for example, the outputs of the input stage selection unit m are im _0, im _1, and im _ m; the output stage comprises m output stage or units, each output stage or unit corresponds to a signal output after crossing with the same label, for example, the output stage or unit m corresponds to a signal output after crossing, each output stage or unit has m inputs, which are also distinguished by underlining and marking, for example, the inputs of the output stage or unit m are om _0, om _1, and. The units of the input stage and the units of the output stage are sequentially connected according to the unit number sequence, so as to complete the cross function from m inputs to m outputs, and it is described from the perspective of the outputs that the unit m of the output stage corresponds to the cross output signal om, the 0 th input om _0 of the unit m of the output stage comes from the m output i0_ m of the input stage selecting unit 0, the 1 st input om _1 of the unit m of the output stage comes from the m output i1_ m of the input stage selecting unit 1, and.
Fig. 2 illustrates an implementation schematic diagram of an input stage selection unit, where it is assumed that an input signal of the input stage selection unit n is selected as an analysis object, and it is assumed that the input signal of the input path, i.e. the input signal in of the nth path, needs to be crossed to the output of the r path, and how to implement the present invention will be described in detail below.
The invention adopts a parallel processing structure, namely an input stage selection unit comprises m judgment equality units, each judgment equality unit has the same function and is responsible for detecting whether a signal is allowed to pass, if the signal is allowed to pass, the signal is output, otherwise, 0 is output, and the signal is not allowed to pass; the input of each judgment equality unit is the same and is the input signal of the input stage selection unit, namely the input signal to be crossed; the decision whether the equality unit outputs 0 or a signal depends on the user requirements, i.e. what kind of crossover from input to output is realized by the user, e.g. here the crossover from input n to output r is required to be realized, then the input stage selection unit n has its r-th output port outputting the input signal in and the remaining output ports outputting 0.
In order to better understand the method proposed by the present invention, an example is seen below in conjunction with fig. 3, which requires implementing the crossover from input 0 to output 3, input 1 to output 0, input 2 to output 1, input 3 to output 2. Since input 0 is required to cross to output 3, the 0 th to 3 rd outputs of the input stage selection unit 0 are 0, i0 in order; also, since input 1 is required to cross to output 0, the 0 th to 3 rd outputs of input stage selection unit 1 are i1, 0 in order; also, since input 2 is required to cross to output 1, the 0 th to 3 rd outputs of the input stage selection unit 2 are 0, i2, 0 in order; also, since it is required that input 3 cross to output 2, the 0 th to 3 rd outputs of the input stage selection unit 3 are 0, i3, 0 in order. According to the structure provided by the invention, the connection relation between each input stage selection unit and each output stage OR unit is obtained, the input of the output stage OR unit 0 is 0, i1, 0 and 0 in sequence, so that a signal i1 is output after OR operation, and the intersection of i1 to o0, namely input 1 to output 0 is realized; similarly, the input of the output stage or unit 1 is 0, i2 and 0 in sequence, so that the signal i2 is output after the or operation, and the intersection of i2 to o1, namely input 2 to output 1 is realized; similarly, the input of the output stage or unit 2 is 0, i3 in sequence, so the signal i3 is output after the or operation, and the intersection of i3 to o2, i.e. input 3 to output 2 is realized; similarly, the input of the output stage or unit 3 is i0, 0 and 0 in sequence, so the or operation outputs the signal i0, and the intersection of i0 to o3, i.e., input 0 to output 3 is realized.
It can be seen from the above method for implementing line crossing of the present invention that the method has strict non-blocking property, does not need any precondition, and does not have the problem of route switching failure; the method is simple and reliable in control, complex routing algorithms are not needed to be matched, and the routing intersection can be realized only by informing the requirement of the user on the input and output from which path to cross from which input and output paths to each sub judgment equality unit in the input stage selection unit; when the method is realized on an FPGA, the coupling is that each input of each output stage OR unit needs to be subjected to OR operation, all the inputs are subjected to bit-wise OR operation and then output, the operation is much smaller than the resource consumed by performing MUX operation on all the inputs in a CLOS structure, the layout and the wiring are easier to realize, the congestion degree is greatly reduced, the final performance is that the realization time sequence is good, and the performance is improved; the method can meet the requirement of high-capacity intersection, although the CLOS network can also realize the high-capacity intersection, the logic resource consumed by the CLOS network is much larger than that of the method provided by the invention along with the increase of the m value, so the method provided by the invention is more beneficial to the realization of the high-capacity line intersection.
Claims (1)
1. A realization method for realizing a high-capacity line crossing structure is realized on a hardware platform based on an FPGA and is characterized in that: the cross structure is composed of an input stage and an output stage;
the input stage comprises m input stage selection units, each input stage selection unit corresponds to input signals to be crossed with the same label, for example, the input stage selection unit m corresponds to input signals im to be crossed, m represents the number of paths to be crossed, each input stage selection unit has m outputs which are distinguished by underlining and labeling, for example, the outputs of the input stage selection unit m are im _0, im _1, and im _ m;
the output stage comprises m output stage or units, each output stage or unit corresponds to a signal output after crossing with the same label, for example, the output stage or unit m corresponds to a signal output after crossing, each output stage or unit has m inputs, which are also distinguished by underlining and marking, for example, the inputs of the output stage or unit m are om _0, om _1, and.
The input stage units and the output stage units are sequentially connected according to the unit number sequence, so as to complete the cross function from m inputs to m outputs, and the description is made from the perspective of the outputs, the output stage unit m corresponds to the crossed output signal om, the 0 th input om _0 of the output stage unit m comes from the m output i0_ m of the input stage selection unit 0, the 1 st input om _1 of the output stage unit m comes from the m output i1_ m of the input stage selection unit 1,... the m th input m of the output stage unit m comes from the m output im _ m of the input stage selection unit m, and in summary, the m inputs of the output stage unit m come from the m outputs of the m input stage selection units respectively;
the specific implementation method of the input stage selection unit is as follows:
the input stage selection unit has 1 input m outputs, and the functional meaning of the input stage selection unit is that an input signal is selected to be output at a plurality of output ports; for example, the input signal is selected to be output at the output port of the r-th path, then the output port of the r-th path has a signal, and the output of 0 at the other output ports has no signal; in order to realize the described function, the structure adopts a parallel processing structure, namely the input stage selection unit comprises m judgment equality units, each judgment equality unit has the same function and is responsible for detecting whether the signal is allowed to pass, if the signal is allowed to pass, the signal is output, otherwise, 0 is output, and the signal is not allowed to pass; the input of each judgment equality unit is the same and is the input signal of the input stage selection unit, namely the input signal to be crossed; judging whether the equality unit outputs 0 or the signal depends on the user requirement, namely, what kind of intersection from input to output is realized by the user, for example, the user wants to realize the intersection from input n to output r, then the input signal in is output from the r-th output port of the input stage selection unit n, and the rest output ports output 0;
the specific function of the output stage OR unit is described as follows:
the output stage OR unit has m inputs and 1 output, and the realization function is to OR the m inputs and then output the inputs; from the connection relationship between the input stage and each unit of the output stage and the description that only one path of output of m paths of units of the input stage has a signal and the other paths are 0, it can be seen that only one path of input of m paths of the or unit of each output stage has a signal and all the other paths are 0, so that the or operation is actually to select and output one path of the signal.
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Application publication date: 20200117 |