CN110708067A - A capacitance correction method for double-sort interval selection applied to analog-to-digital converters - Google Patents

Abstract

The invention discloses a capacitance correction method applied to the double-sort interval selection of an analog-to-digital converter, and relates to the fields of microelectronics and solid electronics, in particular to the capacitance in the mixed capacitance-resistance type successive approximation analog-to-digital converter in the field. Set method. The invention adopts the unit capacitor to form the positive and negative capacitor array of the mixed capacitor resistance type successive approximation analog-to-digital converter. (MSB-1) ...... least significant bit (LSB), Dummy capacitance. Compared with the traditional SAR ADC, the static performance and dynamic performance are significantly improved; compared with the traditional analog and digital correction algorithms, the adjustment and correction method proposed by the present invention only needs to perform two sorting, and the operation is simpler and greatly improved. Save area and power consumption.

Description

A capacitance correction method for double-sort interval selection applied to analog-to-digital converters

technical field

The invention relates to the field of microelectronics and solid state electronics, in particular to a capacitance setting method in a mixed capacitance-resistance type successive approximation analog-to-digital converter in the field.

Background technique

In the age of intelligence, digital signals are involved in all aspects of life. Analog-to-Digital Converter (abbreviated as ADC) and Digital-to-Analog Converter (abbreviated as DAC) are bridges connecting digital signals and analog signals, and are important foundations of the digital world. Successive approximation analog-to-digital converters (SAR ADCs) have the advantages of high precision, low power consumption, small size, and moderate speed, and are widely used in embedded low-power applications such as implantable medical equipment and smart sensors.

High-frequency noise of switching power supply, noise of analog input signal, unstable power supply output, mismatch of components, etc. will affect the accuracy of ADC. In the design of SAR ADC, the comprehensive consideration of performance indicators such as accuracy, speed, power consumption, and area, as well as the selection of ADC structure and correction algorithm, are problems that designers need to face. The literature [J.Shen et al.,"A 16-bit16MS/s SAR ADC with on-chip calibration in 55nm CMOS,"2017Symposium on VLSICircuits,Kyoto,2017,pp.C282-C283.] proposes a low input capacitance And high-efficiency on-chip foreground calibration algorithm, using a reference switch independent of the signal from the storage capacitor to increase speed and reduce area, there is a significant improvement in performance after calibration, but the overall power consumption is increased. Literature [W.Tung and S.Huang,"An Energy-Efficient11-bit 10-MS/s SAR ADC with Monotonic Switching Split Capacitor Array,"2018IEEE International Symposium on Circuits and Systems(ISCAS),Florence,2018,pp.1 -5.] proposed an asynchronous differential SAR ADC, which uses a monotonic switching procedure and a split capacitor structure at the same time to achieve the purpose of reducing area and energy consumption, and proposed a digital calibration method that makes the difference between capacitor mismatch and bridge parasitics The influence caused by capacitor mismatch is minimized, but this method is more complicated, which increases the complexity of layout design, and the improvement of linearity and dynamic parameters is not obvious. Patent 201910772581.3 proposed a capacitance correction method for median selection in 2019. Through multiple sorting and multiple median selection, the static performance and dynamic performance of the ADC are effectively improved. However, up to 6 capacitor sequencing and 5 capacitor combinations greatly increase the power consumption of the ADC and reduce the conversion rate of the ADC.

SUMMARY OF THE INVENTION

Aiming at the defects of the prior art in terms of poor performance, high power consumption, complex capacitor layout design, and large volume, the present invention designs a capacitor correction method for double-sort interval selection applied to successive approximation analog-to-digital converters.

The technical solution of the present invention is a capacitance correction method applied to double-sort interval selection of an analog-to-digital converter, the method comprising:

Step 1: Use unit capacitors to form the positive and negative capacitor arrays in the mixed capacitor resistance type successive approximation analog-to-digital converter. Set the positive and negative capacitor arrays to each contain n unit capacitors, and label the unit capacitors as: C _u1 , C _u2 , C _u3 ......C _u(n-1) , C _un ;

将位于中间位置的两个单位电容

分别作为转换器的最低有效位LSB与Dummy电容；然后将剩余的电容首尾组合，得到n/2-1个新的电容组C_i：

与

组合为C₁、

与

组合为C₂、

与

组合为C₃……

与

组合为C_(n/2-1)；Step 2: Perform the first sorting: Arrange the unit capacitances C _ui in ascending order according to the capacitance value, and number them as follows

Place the two unit capacitors in the middle

As the least significant bit LSB of the converter and the Dummy capacitor, respectively; then combine the remaining capacitors end to end to get n/2-1 new capacitor banks C _i :

and

The combination is C ₁ ,

and

The combination is C ₂ ,

and

_The combination is C3...

and

The combination is C _(n/2-1) ;

Step 3: Perform the second sorting: Arrange n/2-1 new capacitor banks in ascending order according to the capacitance value, and number them as follows:

Step 4: For the sorted capacitor banks, start with the first capacitor bank Start interval selection, and select the current n/4 capacitor banks as the most significant bit MSB of the converter;

开始间隔选取，选取出当前n/8个电容组作为转换器的次高有效位MSB－1；Step 5: For the remaining capacitor banks, start with the first capacitor bank

Start interval selection, select the current n/8 capacitor banks as the second most significant bit MSB-1 of the converter;

作为转换器的次低有效位LSB+1；Step 6: Repeat Step 5. In the remaining capacitor groups, select from the first capacitor group at intervals, and each time the number of capacitor groups selected is halved, as the remaining valid bits of the converter: MSB-2, MSB-3... , until one capacitor bank remains

As the second least significant bit LSB+1 of the converter;

Step 7: Use the obtained MSB, MSB-1, MSB-2, MSB-3... LSB, dummy capacitors as the capacitor array of the successive approximation analog-to-digital converter to perform analog-to-digital conversion.

Compared with the traditional SAR ADC, the capacitance calibration method proposed by the present invention has significantly improved static performance and dynamic performance; compared with the traditional analog and digital calibration algorithms, the adjustment and calibration method proposed by the present invention Only two sortings are required, which makes the operation simpler and greatly saves area and power consumption.

Description of drawings

Figure 1 is a schematic diagram of the structure of a mixed capacitor-resistance SAR ADC.

FIG. 2 is a schematic diagram of selecting a double-sort interval proposed by the present invention.

Figure 3 is a schematic diagram of comparing the unit capacitors Cu1 and Cu2 in two steps; (a) the upper plates of all unit capacitors in the positive and negative capacitor arrays are connected to VCM, the lower plates of Cu1 in the positive capacitor array are connected to VREFP, and the lower plates of other unit capacitors are connected to Connect VREFN, the lower plate of Cu1 in the negative capacitor array is connected to VREFN, and the lower plate of other unit capacitors is connected to VREFP; (b) The upper plates of all unit capacitors in the positive and negative capacitor array are disconnected from VCM, and Cu2 in the positive capacitor array is connected The lower plate is connected to VREFP, the lower plate of other unit capacitors is connected to VREFN, the lower plate of Cu2 in the negative capacitor array is connected to VREFN, and the lower plate of other unit capacitors is connected to VREFP.

Figure 4 shows the simulation results of the static performance of the 18-bit SAR ADC.

Figure 5 shows the static performance simulation results of the 16-bit SAR ADC.

Figure 6 shows the simulation results of the static performance of the 14-bit SAR ADC.

Figure 7 shows the simulation results of the dynamic performance of the 18-bit SAR ADC.

Figure 8 shows the simulation results of the dynamic performance of the 16-bit SAR ADC.

Figure 9 shows the simulation results of the dynamic performance of the 14-bit SAR ADC.

Detailed ways

The present invention proposes a capacitance correction method with double sorting interval selection. For a traditional binary array, an 18-bit mixed capacitance resistance type successive approximation analog-to-digital converter composed of a high 8-bit capacitance DAC and a low 10-bit resistance DAC is taken as an example for detailed description.

Figure 1 shows the structure of the M+N-bit mixed capacitance-resistance type successive approximation analog-to-digital converter of the high-M-bit capacitance DAC and the low-N potential resistance DAC. If M=8, N=10, it means the 18-bit SAR ADC composed of high 8-bit capacitance DAC and low 10-bit resistance DAC. The positive and negative capacitor arrays of the upper 8 bits each contain 128 unit capacitors, and the 128 unit capacitors are labeled as: C_u1, C_u2, C_u3... C_u127, C_u128 (as shown in (1) in Figure 2). The capacitance values of the 128 unit capacitors should be equal, but in practice, due to the influence of various factors, the 128 unit capacitors are often not exactly equal, but obey a normal distribution.

First Ascending Sorting of 128 Unit Capacitors: Adoption and Literature [H.-.Lee, D.A.Hodges and P.R.Gray, "A Self-Calibrating 15Bit CMOS A/D Converter," IEEE Journal of Solid-State Circuits ,1984,19(6):813-819] Similar capacitance comparison method (as shown in Figure 3) completes the comparison of capacitance and capacitance, and then sorts the 128 unit capacitances in ascending order, and labels them in turn: C_u1^*, C_u2^*, C_u3^*...C_u127^*, C_u128^* (as shown in Figure 2(2)). Use the two unit capacitors C_u64^* and C_u65^* located in the middle as the least significant bit (LSB) and Dummy capacitor of the converter respectively, and then combine the remaining capacitors end to end to get 63 new capacitors Group C_i: The combination of C_u1^* and C_u128^* is C_1, the combination of C_u2^* and C_u127^* is C_2, the combination of C_u3^* and C_u126^* is C_3... The combination of C_u63^* and C_u66^* is C_63.

In Figure 2:

(1) There are 128 unit capacitors in the positive and negative capacitor arrays, which are denoted as C _ui .

(2) The first sorting: Arrange the 128 unit capacitors in ascending order according to the capacitance value, denoted as C _ui ^* ;

Use the two capacitors C _u64 and C _u65 in the middle as the LSB and Dummy capacitors of the converter respectively;

The remaining capacitors are combined end to end to obtain 63 new capacitor banks, denoted as C _i .

(3) Second sorting: Arrange the new 63 capacitance groups in ascending order according to the capacitance value, and denote it as C _i ^* ;

The capacitor groups are selected at intervals, and 32 capacitor groups (64 unit capacitors) are selected as the MSB of the converter.

(4) Select 16 capacitor groups (32 unit capacitors) as the MSB-1 of the converter by interval selection of the remaining capacitor groups.

(5) Select 8 capacitor groups (16 unit capacitors) as the MSB-2 of the converter by interval selection of the remaining capacitor groups.

(6) The remaining capacitor groups are selected at intervals to obtain other valid bits of the converter: MSB-3, MSB-4, MSB-5.

Sort the 63 capacitor groups in ascending order for the second time, and label them as: C_1^*, C_2^*, C_3^*...C_62^*, C_63^*, and then select the interval (as shown in (3)) : Select from the first capacitor group (C_1^*) at intervals, and select 32 capacitor groups (64 unit capacitors) as the most significant bit (MSB) of the converter; The first capacitor group (C_2^*) is selected at intervals, and 16 capacitor groups (32 unit capacitors) are selected as the second most significant bit (MSB-1) of the converter; continue to repeat the above interval selection in the remaining capacitor groups method, starting from the first capacitor group, and halving the number of capacitor groups each time, as the remaining valid bits of the converter: MSB-2, MSB-3..., until the remaining capacitor group (C_32^*) is used as the conversion the second least significant bit (LSB+1) of the register.

In Figure 1, if M=8, N=8, it means a 16-bit mixed capacitor resistance type successive approximation analog-to-digital converter composed of high 8-bit capacitors and low 8-bit resistors; if M=8, N=6, Then it represents a 14-bit mixed capacitance-resistance type successive approximation analog-to-digital converter composed of a high 8-bit capacitance and a low 6-bit resistance. The capacitance calibration method of double-sequencing interval selection is exactly the same as that of the 18-bit (M=8, N=10) mixed capacitor-resistance successive approximation analog-to-digital converter. For 16-bit (M=8, N=8), 14-bit (M=8, N=6) mixed capacitance-resistance type successive approximation analog-to-digital converter for correction.

The 18-bit, 16-bit, and 14-bit mixed capacitor-resistance successive approximation analog-to-digital converters are simulated in Matlab, and the capacitance mismatch ratio ( ) is set to 0.1%, 0.15%, and 0.2%, respectively, and the static simulation (differential non- Linear (DNL), integral nonlinear (INL)) Monte Carlo simulation times are set to 100 times, dynamic simulation (spurious free dynamic range (SFDR), signal-to-noise harmonic ratio (SNDR)) Monte Carlo simulation times are set for 500 times.

The static simulation results are shown in Figure 4 (18-bit), Figure 5 (16-bit), Figure 6 (14-bit), and summarized in Table 1.

For an 18-bit SAR ADC, the double-sort interval selection proposed in the present invention increases the DNL maximum root-mean-square (RMS) and INL maximum RMS by 95.1% and 97.1% to 0.43dB and 0.40dB, respectively. For the 16-bit SAR ADC, the double-sort interval selection improves the DNL maximum RMS and INL maximum RMS by 94.4% and 96.3% to 0.22dB and 0.18dB, respectively. For the 14-bit SAR ADC, the double-sort interval selection increases the DNL maximum RMS and INL maximum RMS by 87.3% and 89.7% to 0.16dB and 0.15dB, respectively.

The dynamic simulation results are shown in Figure 7 (18-bit), Figure 8 (16-bit), Figure 9 (14-bit), and are summarized in Table 2.

For the 18-bit SAR ADC, the dual-sort interval selection proposed in the present invention increases the minimum and average SFDR by 28.76dB, 33.79dB to 106.40dB, and 122.52dB, respectively; and increases the minimum and average SNDR by 28.38dB and 25.86dB to 102.44 dB, 108.80dB. For the 16-bit SAR ADC, the selection of double sorting interval increases the minimum and average SFDR by 26.50dB, 32.21dB to 101.65dB, and 117.16dB; the minimum and average SNDR increases by 24.31dB, 18.66dB to 95.21dB, and 97.84dB. . For the 14-bit SAR ADC, the selection of double sorting interval increases the minimum and average SFDR by 26.13dB, 25.76dB to 98.24dB, and 108.58dB; the minimum and average SNDR increases by 17.00dB, 9.62dB to 85.64dB, and 86.00dB. .

Tables 3 and 4 respectively summarize the static performance and dynamic performance improvement of the double-sort interval selection proposed in this paper and the median selection proposed in Patent 201910772581.3. In Table 3, the maximum RMS of DNL and the maximum RMS of INL are improved. In Table 4, the average value of SFDR and the average value of SNDR are improved. It can be found that the double sorting interval selection proposed by the present invention is almost the same as the median selection proposed in the patent 201910772581.3 in terms of static and dynamic performance improvement, but the double sorting interval selection proposed by the present invention only needs to be sorted twice, which is much lower than that proposed in the patent 201910772581.3. The six sorts required for median selection of 100% save power and increase the conversion rate.

Compared with the traditional SAR ADC, the capacitance calibration method proposed by the present invention has significantly improved static performance and dynamic performance; compared with the traditional analog and digital calibration algorithms, the adjustment and calibration method proposed by the present invention Only two sortings are required, which makes the operation simpler and greatly saves area and power consumption.

Table 1 DNL and INL 100 times Monte Carlo simulation maximum root mean square summary

Table 2 Summary of 500 Monte Carlo simulations of SFDR and SNDR

Table 3. Comparison of static performance improvement of SAR ADC by double-sort interval selection and median selection (the number of Monte Carlo simulations is 100 times)

Table 4. Comparison of dynamic performance improvement of SAR ADC by double-sort interval selection and median selection (the number of Monte Carlo simulations is 500 times)

Claims (1)

1. A double-sequencing interval selected capacitance correction method applied to an analog-to-digital converter comprises the following steps:

step 1: the unit capacitors are adopted to form a positive capacitor array and a negative capacitor array in the mixed capacitor resistance type successive approximation analog-to-digital converter, the positive capacitor array and the negative capacitor array respectively comprise n unit capacitors, and the unit capacitors are labeled as follows: c_u1、C_u2、C_u3……C_u(n-1)、C_un；

Step 2: carrying out first sequencing: unit capacitance C_uiAre arranged in ascending order according to the capacitance value and are numbered as

Two unit capacitors to be located at the middle positionRespectively as the LSB and Dummy capacitors of the converter; then the rest capacitors are combined end to obtain n/2-1 new capacitor groups C_i：

And

combination is C₁、

And

combination is C₂、And

in combination ofAnd

combination is C_(n/2-1)；

And step 3: and (5) carrying out second sequencing: arranging n/2-1 new capacitor groups in ascending order according to the capacitance values, and numbering the capacitor groups in sequence as follows:

and 4, step 4: for the sorted capacitor banks, from the first capacitor bank

Starting interval selection, and selecting current n/4 capacitor groups as the most significant bit MSB of the converter;

and 5: for the remaining capacitor banks, from the first capacitor bankStarting interval selection, and selecting current n/8 capacitor groups as the second most significant bit MSB-1 of the converter;

step 6: and 5, repeating the step 5, selecting the capacitor groups at intervals from the first capacitor group in the rest capacitor groups, and halving the number of the selected capacitor groups each time to be used as the rest effective bits of the converter: MSB-2, MSB-3 … …, until one capacitor bank remains

As the second least significant bit LSB +1 of the converter;

and 7: and performing analog-to-digital conversion by using the obtained MSB, MSB-1, MSB-2, MSB-3 … … LSB and dummy capacitors as a capacitor array of the successive approximation analog-to-digital converter.

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