CN110707091A

CN110707091A - Three-dimensional memory and forming method thereof

Info

Publication number: CN110707091A
Application number: CN201910808435.1A
Authority: CN
Inventors: 刘慧超; 杨俊铖; 张大伟; 方青春
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2019-08-29
Filing date: 2019-08-29
Publication date: 2020-01-17

Abstract

The invention relates to a three-dimensional memory and a forming method thereof. The three-dimensional memory comprises a substrate and a stacked structure positioned on the substrate, wherein the stacked structure is provided with a virtual area, the virtual area is provided with a plurality of vertical structures penetrating through the stacked structure, each vertical structure comprises an isolation layer and a support body positioned in the isolation layer, and the material of the support body is undoped polysilicon. The three-dimensional memory can relieve the problem of collapse of the step region.

Description

Three-dimensional memory and forming method thereof

Technical Field

The present invention relates to the field of semiconductors, and more particularly, to a vertical three-dimensional memory with a dummy region and a method for forming the same.

Background

With the continuous development of 3D NAND technology, the three-dimensional memory can be stacked vertically with more and more layers, from 24 layers, 32 layers and 64 layers to a high-level stack structure with more than 100 layers, which can greatly increase the storage density and reduce the price of a unit memory cell.

In the formation process of a high-level (e.g. 128-level) three-dimensional memory, a nonfunctional dummy region is defined in a Step region (SS), and some dummy holes or dummy trenches are formed in the dummy region. Typically a virtual Channel hole (DCH). And depositing oxide in the holes or the trenches by using an Atomic Layer Deposition (ALD) method to form a vertical structure. This vertical structure may be formed in some processes all at once in up to, for example, 128 stacked layers. However, in the subsequent processes, the oxide in the holes or trenches of the dummy region shrinks due to the high temperature annealing, and the SS region collapses due to insufficient support of the holes or trenches. After the subsequent filling of the Common Source (ACS) conductive material (e.g., metal tungsten, doped polysilicon), the conductive material will remain in the recess of the SS region. Even if the surface is planarized (e.g., by chemical mechanical polishing), there is still conductive material remaining on the surface of the dielectric filling layer in the step region, which affects the subsequent etching process of the word line contact hole and the electrical connection thereof, thereby affecting the performance of the memory.

Disclosure of Invention

The invention provides a three-dimensional memory with a virtual vertical structure, which can relieve the problem of collapse of a step region, especially under the condition of forming the virtual vertical structure at one time.

The invention adopts the technical scheme that the three-dimensional memory comprises a substrate and a stacked structure positioned on the substrate, wherein the stacked structure is provided with a virtual area, the virtual area is provided with a plurality of vertical structures penetrating through the stacked structure, each vertical structure comprises an isolation layer and a support body positioned in the isolation layer, and the support body is made of undoped polysilicon.

In an embodiment of the invention, the thickness of the isolation layer is 5-7 nm.

In an embodiment of the invention, the support is cylindrical and has a radial dimension of 100 nm and 300 nm.

In an embodiment of the invention, the support body vertically penetrates through the stacked structure.

In an embodiment of the invention, the number of stacked layers of the three-dimensional memory is 96 or more.

In an embodiment of the invention, the plurality of vertical structures are located in a core region and/or a staircase region of the three-dimensional memory.

In an embodiment of the invention, the material of the isolation layer is a dense silicon oxide formed by oxidizing silicon nitride using an in-situ water vapor oxidation process.

The invention also provides a method for forming the three-dimensional memory, which comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure is provided with a substrate and a stacked structure positioned on the substrate, and the stacked structure is provided with a virtual area; forming a plurality of holes or trenches through the stacked structure in the dummy region; forming an isolation layer on the inner wall of the hole or the groove of the virtual area; and filling a support body in the isolation layer, wherein the support body is made of undoped polysilicon.

In an embodiment of the invention, the thickness of the isolation layer is 1-20 nm.

In an embodiment of the present invention, the radial dimension of the support is 100-300 nm.

In an embodiment of the invention, the number of stacked layers of the stacked layers is 96 or more.

In an embodiment of the invention, the dummy region is located in a core region and/or a step region of the semiconductor structure.

In an embodiment of the invention, a method for filling the supporting body is a furnace deposition process.

In an embodiment of the invention, a method of forming the isolation layer includes: forming a silicon nitride layer on the inner wall of the hole or the groove of the virtual area; oxidizing the silicon nitride layer using an in-situ steam oxidation process to form a dense silicon oxide layer as the isolation layer.

By adopting the technical scheme, the support bodies are filled in the holes or the virtual grooves of the virtual area, so that the support effect of the formed vertical structure is enhanced, the collapse phenomenon of the step area can be effectively improved in the high-order manufacturing process of the three-dimensional memory, and the subsequent metal residue is prevented.

Drawings

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:

FIG. 1A is a schematic cross-sectional structure of a three-dimensional memory with a vertical structure provided with dummy regions;

FIG. 1B is a top view of a vertical structure three-dimensional memory provided with dummy regions;

FIGS. 1C-1F are schematic views of the process of collapse of the step region caused by the vertical structure of the dummy region;

FIG. 1G is a cross-sectional view B-B of FIG. 1B;

FIGS. 2A-2C are schematic diagrams of exemplary structures of a three-dimensional memory according to an embodiment of the invention;

FIG. 3 is an exemplary flow chart of a method of forming a three-dimensional memory according to one embodiment of the invention;

FIG. 4A is a cross-sectional view of a dummy trench before filling;

FIGS. 4B and 4C are schematic structural diagrams illustrating the formation of an isolation layer on the inner wall of the hole or trench in the dummy region according to an embodiment of the present invention;

FIG. 4D is a schematic view illustrating filling of a support body in an isolation layer according to an embodiment of the invention;

FIG. 4E is a schematic view of a vertical structure being planarized in accordance with one embodiment of the present invention;

fig. 4F is a schematic view of removing polysilicon on the back side of the substrate in an embodiment of the invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.

As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.

In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary words "below" and "beneath" can encompass both an orientation of up and down. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein should be interpreted accordingly. Further, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.

It will be understood that when an element is referred to as being "on," "connected to," "coupled to" or "contacting" another element, it can be directly on, connected or coupled to, or contacting the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to" or "directly contacting" another element, there are no intervening elements present. Similarly, when a first component is said to be "in electrical contact with" or "electrically coupled to" a second component, there is an electrical path between the first component and the second component that allows current to flow. The electrical path may include capacitors, coupled inductors, and/or other components that allow current to flow even without direct contact between the conductive components.

Fig. 1A is a schematic cross-sectional structure view of a vertical-structured three-dimensional memory provided with a dummy region, fig. 1B is a top view of the vertical-structured three-dimensional memory provided with the dummy region, and fig. 1A is a sectional view a-a of fig. 1B. Referring to fig. 1A and 1B, the three-dimensional memory includes a core array region 110 and a staircase region 120. The core array region 110 and the stepped region 120 include a stacked structure formed on a substrate. The core array region 110 and the staircase region 120 may be separated by a plurality of Gate Line Slits (GLS) 102, thereby forming a plurality of finger storage regions 101. The gate line gap 102 may be filled with a conductive layer electrically connected to an Array Common Source (ACS) at the bottom of the stacked structure. Each finger storage area 101 is formed with a plurality of channel structures 111 penetrating the stacked structure in the core array area 110 to form a memory string. The channel structure 111 may include a memory layer and a channel layer in a cylindrical shape, and may further include an insulating material filled in the channel layer. The memory layer may include a blocking layer, a charge storage layer, and a tunneling layer.

Dummy areas are distributed at some positions of the core array area 110 and the stepped area 120. A plurality of dummy channel structures 112 are formed in the dummy region 110a of the core array region 110 and extend through the stack structure. Dummy channel structures 122 are formed through the stack structure in the dummy region 120a of the step region 120. Here, the dummy channel structure 112 and the dummy channel structure 122 are collectively referred to as a vertical structure. The dummy channel structure 112 may have a cylindrical shape similar to the channel structure 111, but typically does not have a memory layer and a channel layer within the dummy channel structure 112, but is filled with an insulating material as a support. The dummy channel structure 122 may also have a similar shape as the channel structure 111. In other embodiments not shown, the vertical structures may also be in the shape of a rectangular parallelepiped, rather than a channel structure, which extends for a certain length in the X-direction or Y-direction in the figure. It is noted that the distribution of the channel structure 111 and the

dummy channel structures

112, 122 in fig. 1B is exemplary. In an actual structure, the number of the channel structures 111 or the

dummy channel structures

112 and 122 in one column of the adjacent gate line gaps 102 may be more than 2, and may be 3, 4, 5, 6 or more.

Dummy channel structure 112 may be formed with channel structure 111, e.g., by etching holes together, filling the semiconductor layer together, and optionally performing planarization together. Unlike the channel structures 111, bit lines or interconnect lines are not formed on the dummy channel structures 112, and the dummy channel structures 121 do not play a storage role but only play a Mechanical Supporting role (Mechanical Supporting pilars).

Fig. 1C-1F are cross-sectional views a-a of fig. 1B for illustrating a process of collapsing a step region by a vertical structure of a dummy region, and fig. 1G is a cross-sectional view B-B of fig. 1B. As shown in fig. 1B to 1G, in order to replace the gate sacrificial layer in the stacked structure with a metal layer, gate line slits 130 are formed in the core array region 110 and the step region 120. The direction of the gate line slits 130 is identical to the word line direction of the three-dimensional memory. The gate line slit 130 penetrates the stacked structure from top to bottom to the lowermost substrate. The sidewall of the gate line gap 130 is a space insulating Spacer (Spacer), which may be a dielectric layer containing oxide, and the gate line gap 130 may be partially or completely filled with a conductive material, such as tungsten (W), cobalt (Co), ruthenium (Ru) doped polysilicon, etc., behind the Spacer. In the manufacturing process of the three-dimensional memory, the gate line slit 130 is used to replace a gate sacrificial layer in a stacked structure with a gate conductive layer and to divide an entire memory region into a plurality of block memory regions and finger memory regions.

Referring to fig. 1C-1F, during the formation of the gate line gap 130, due to insufficient support of the dummy channel structure 121 in the step region, the top of the step region 120 is collapsed (CMP dispersing) during the gate line gap process, especially during the wafer planarization by Chemical Mechanical Polishing (CMP). After filling the gate conductive material (e.g., tungsten metal), the gate conductive material enters the recess of the SS region. Even after subsequent planarization, such as Chemical Mechanical Polishing (CMP), there is still conductive material remaining in the collapse of the step region 120, which may cause contamination of the tool of the process line, on the one hand, and also may seriously affect the subsequent etching process of the word line contact hole and the electrical connection thereof, thereby affecting the word line connection performance of the memory.

Fig. 2A is an exemplary cross-sectional schematic of a three-dimensional memory according to an embodiment of the invention. Referring to fig. 2A, the three-dimensional memory includes a substrate 201 and a stack structure 230 on the substrate 201. The stacked structure 230 has a plurality of dummy channel structures 240 extending therethrough, each dummy channel structure 240 includes an isolation layer 241 and a support 242 located in the isolation layer 241, and the support 242 is made of undoped polysilicon.

Referring to fig. 2, the substrate 201 of the three-dimensional memory may be a semiconductor substrate wafer, such as a Silicon substrate (Si), a Germanium substrate (Ge), a Silicon Germanium substrate (SiGe), a Silicon On Insulator (SOI), or a Germanium On Insulator (GOI). In some embodiments, the semiconductor substrate may also be a substrate comprising other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC. But also a stacked structure such as Si/SiGe or the like. Other epitaxial structures may also be included, such as Silicon Germanium On Insulator (SGOI) and the like. The substrate 201 may also be an insulating substrate such as a ruby substrate, a sapphire substrate, or a glass substrate.

The stacked structure 230 is a stack in which a first material layer and a second material layer are alternately stacked, similar to the stacked structure of the three-dimensional memory shown in fig. 1A. The first material layer and the second material layer may be selected from materials and include at least one insulating dielectric such as silicon nitride, silicon oxide, amorphous carbon, diamond-like amorphous carbon, germanium oxide, aluminum oxide, and the like, and combinations thereof. The first material layer and the second material layer have a dry etching selectivity ratio of approximately 1, but have different wet etching selectivity (e.g., ≧ 30:1 or even higher). For example, a combination of silicon nitride and silicon oxide, a combination of silicon oxide and undoped polysilicon or amorphous silicon, a combination of silicon oxide or silicon nitride and amorphous carbon, or the like may be used. The deposition method of the first material layer and the second material layer of the stacked structure may include chemical vapor deposition (CVD, PECVD, LPCVD, HDPCVD), Atomic Layer Deposition (ALD), or a physical vapor deposition method such as Molecular Beam Epitaxy (MBE), thermal oxidation, evaporation, sputtering, and the like, and various methods thereof. One of the first material layer and the second material layer may serve as a gate sacrificial layer, such as a silicon nitride layer. The stack serving as the gate sacrificial layer may also be another conductive layer, such as metal tungsten, cobalt, nickel, etc. Another material layer not serving as a gate sacrificial layer may be a dielectric material such as silicon oxide, for example, aluminum oxide, hafnium oxide, tantalum oxide, etc. In the embodiment of the present invention, the stacked structure may be formed by alternately forming a material as a gate sacrificial layer and an oxide layer, or may be formed by alternately forming a gate conductive layer and an oxide layer.

The number of stacked layers (tier) in the stacked structure 230 determines the number of memory cells in the vertical direction, and the number of stacked layers may be, for example, 32 layers, 64 layers, or the like. The more layers, the higher the integration of the three-dimensional memory. In the embodiment of the present invention, the number of stacked layers in the stacked structure 230 is at least 96. Preferably 128 layers.

Referring to fig. 2A and 2B, the three-dimensional memory also includes a core region 210 and a staircase region 220. The core array region 210 and the staircase region 220 may be separated by a plurality of gate line gaps 202, thereby forming a plurality of finger storage regions 201. The gate line gap 202 may be filled with a conductive layer electrically connected to an Array Common Source (ACS) at the bottom of the stacked structure. Dummy areas are distributed at some positions of the core array area 110 and the stepped area 120. A plurality of dummy channel structures 212 are formed in the dummy region 210a of the core array region 210. Dummy channel structures 240 are formed through the stack structure in the dummy region 220a of the step region 120.

The distribution of the dummy channel structures in fig. 2A and 2B is merely an example. In the gate last process, before replacing the gate sacrificial material with the gate conductive material, more than 1 dummy channel structure 240 (e.g., 240b,240c) is required to be disposed on each step of the step region 220 and penetrate through the stacked structure 230. Here, the stepped region 220 may be distributed in multiple steps along the X direction. In addition, the stepped region 220 may also be formed in a plurality of sections having different heights along the Y direction, for example, 3 sections, 6 sections, or 8 sections, thereby increasing the number of steps. On each step, one or more

dummy channel structures

240b,240c may be disposed. There may also be some dummy channel structures 240b located at the interface of the core region 210 and the stepped region 220. There may also be some dummy channel structures 240d located in the core region 210. As shown in fig. 2A and 2B, the dummy channel structure 240a is located at the boundary between the core region 210 and the step region 220, and has a larger number of stacked layers; the dummy channel structure 240b is located in the middle of the step region 220, and the number of layers of the stack penetrated by the dummy channel structure is about half of the total number of layers; dummy channel structure 240c is located at an outer boundary of stepped region 220, which does not substantially pass through the stacks in stack structure 230.

As shown in fig. 2A and 2B, a plurality of channel structures 211 penetrating the stack structure 230 are also formed at the core region 210. These channel structures 211 are used to form memory cells.

In some embodiments, the plurality of channel structures 211 and the plurality of dummy channel structures 240 may be formed by the same photolithography process. For example, the channel structure 211 and the dummy channel structure 240 may be formed by exposing the core region 210 and the step region 220 simultaneously with a photomask, and performing a corresponding etching, cleaning, filling, and other processes, if necessary, by performing a surface planarization process on the wafer by chemical mechanical polishing.

In other embodiments, the plurality of channel structures 211 and the plurality of virtual channel holes 240 may also be formed separately.

The dummy channel structure 240 may have a shape of a cylindrical structure similar to the channel structure 211. In the embodiment of the present invention, the dummy channel structure 240 may be replaced with other vertical structures. The angle shown in fig. 2A is a side cross-sectional view of the three-dimensional memory. The cross-sectional shape of the vertical structure may be, but is not limited to, a rectangle, a circle, an ellipse, a spindle, a dumbbell, etc., if viewed from above the three-dimensional memory downward, as seen on the upper surface of the three-dimensional memory. Fig. 2B illustrates an example in which the cross section of the dummy channel structure 240 is circular. Fig. 2C shows an example of a vertical structure with a cross-section of another shape. Considering that the vertical structure forms and forms are different from the channel structure 211, the dummy channel structure 240 and its variation structure are collectively referred to as a vertical structure.

An isolation layer 241 is formed in an inner wall of each dummy channel structure 240. The isolation layer 240a may be an insulating material, such as an oxide, having a different wet etching selectivity (e.g., ≧ 30:1) than the gate sacrificial material. The process of forming the isolation layer 240a may be, but is not limited to, various methods such as chemical vapor deposition (CVD, PECVD, LPCVD, HDPCVD), Atomic Layer Deposition (ALD), or physical vapor deposition methods. In a preferred embodiment of the present invention, the material of the isolation layer 241 is dense silicon oxide, which may be formed by oxidizing silicon nitride using an in-situ water vapor oxidation process (ISSG).

In some embodiments, the thickness of the isolation layer 241 is 1 to 20 nm.

A support 242 is further formed in the isolation layer 241 of each dummy channel structure 240, and the support 242 substantially fills one end of the dummy channel structure 240 close to the substrate 201, and at one end close to the upper surface of the three-dimensional memory, the support 242 does not fill the inside of the dummy channel structure 240, and a certain gap is left. The material of the supporting body 242 may be polysilicon, preferably undoped polysilicon with high hardness, so as to play a good supporting role and prevent the upper structure of the step region 220 from collapsing in the subsequent process. The method of forming the support 242 may be a furnace deposition process. Under necessary conditions, a high-temperature annealing process can be assisted after the deposition process, so that the support body structure is more compact and the supporting force is stronger.

In some embodiments, the radial dimension of support 242 is 100-300 nm. When the support body 242 is cylindrical, its radial dimension represents the diameter of its cross-section. Referring to fig. 2, the support body 242 has a cross-sectional diameter gradually increasing from an end near the substrate 201 upward. The illustration in fig. 2 is merely an example, and is not intended to limit the specific shape of the supporting body 242 in the embodiment of the present invention.

Referring to fig. 2A, the support 242 penetrates the stack 230. Specifically, for the dummy channel structure 241 located at the boundary between the core region 210 and the step region 220, the number of layers of the stack layer penetrated by the support 242 is greater; for the dummy channel structure 242 located at the middle portion of the step region 220, the number of layers of the stack layer penetrated by the support 242 therein is about half of the total number of layers; for dummy channel structure 240c located at the outer boundary of stepped region 220, support 242 therein does not substantially pass through the stack in stacked structure 230.

Fig. 3 is an exemplary flowchart of a method of forming a three-dimensional memory according to an embodiment of the present invention. Referring to fig. 3, the method includes the steps of:

in step 310, a semiconductor structure is provided, the semiconductor structure having a substrate and a stacked structure on the substrate, the stacked structure having a dummy region.

Fig. 4A is a cross-sectional view of a dummy trench before filling in an embodiment of the invention. Referring to fig. 4A, the semiconductor structure provided in this step 310 has a substrate 410 and a stacked structure 420. The substrate 410 and the stacked structure 420 are similar to the substrate 201 and the stacked structure 230 as shown in fig. 2A. Meanwhile, the stack structure 420 also has a dummy area as shown in fig. 2B.

In the embodiment of the present invention, the number of stacked layers of the stacked structure 420 is 96 or more. Preferably 128 layers. The stack structure 420 may be formed by stacking a plurality of stacks (deck).

At step 320, a plurality of holes or slots are formed through the stacked structure in the dummy area.

With continued reference to fig. 4A, a plurality of holes 430 are formed through stacked structure 420 in the semiconductor structure. An example of only one hole 430 is shown in fig. 4A, but it is understood that the number of holes 430 in the stacked structure 420 is not limited thereto. Referring to fig. 2A, 2B and 4A, since the hole 430 penetrates through several layers of the stacked structure 420, it may be located at the core region 210, the boundary between the core region 210 and the stepped region 220, or the stepped region 220. Preferably, the hole 430 is located in the stepped region 220.

In some embodiments, the plurality of holes 430 may be formed by the same photolithography process as other trench holes in the semiconductor structure, such as a trench hole in the core region. In other embodiments, the plurality of holes 430 may be formed separately.

Wherein the trench hole 411 for the memory cell is formed in a Multi-step etching, one-step or Multi-step filling process to form a stacked structure (Multi-stack); correspondingly, the step of the step region 220 can be etched for multiple times in a segmented manner, or can be continuously etched before or after the process of forming the trench hole 211; as for the hole 430, in view of saving the process cost and reducing the process cycle, in the embodiment of the present invention, the hole 430 is formed after the channel hole and step process by a one-step etching and one-step filling process. The hole 430 may have a similar shape as the channel hole 411, and thus is referred to as a virtual channel hole.

The holes 430 formed in this step may be cylindrical, and the cross-sectional shape thereof may be rectangular, circular, oval, spindle-shaped, dumbbell-shaped, or the like. In other embodiments, the formed may be a groove that extends a certain length in the X direction or the Y direction in fig. 2B.

In step 330, an isolation layer is formed on the inner wall of the hole or the trench in the dummy region.

Fig. 4B and 4C are schematic structural diagrams illustrating isolation layers formed on the inner walls of the dummy trench holes according to an embodiment of the present invention. In some embodiments, step 330 further comprises two steps:

first, as shown in fig. 4B, a silicon nitride layer 431 is formed on the inner wall of the hole 430.

Next, referring to fig. 4C, the silicon nitride layer 431 is oxidized using an in-situ water vapor oxidation process (ISSG) to form a dense silicon oxide layer as an isolation layer 432.

The isolation layer 432 formed by the steps shown in fig. 4B and 4C has a dense oxide structure, which can perform better isolation. In addition, the wet etching rate of the dense oxide layer obtained by the ISSG process is very low, and the isolation layer 432 has a good isolation function.

In other embodiments, an oxide layer may be directly deposited on the inner wall of the hole 430 by ALD, CVD, or the like as the isolation layer 432, the oxide may be silicon dioxide, or a high temperature annealing process may be added after the deposition process to improve the density of the isolation layer, increase the damage resistance in the replacement process of the gate conductive layer in the gate post-process, and simultaneously improve the filling capability of the dummy trench structure support 242, thereby improving the support strength of the support structure to a certain extent.

Step 340, filling a support body in the isolation layer. The support body is made of undoped polysilicon.

As shown in FIG. 4C, the isolation layer 432 formed in the inner wall of the hole 430 is a thin layer, and the thickness thereof may be 1 to 20 nm. After forming the isolation layer 432, the space inside the hole 430 is filled to form the support 433. The support body 433 functions to support the stacked structure 420 around the hole 430.

Fig. 4D is a schematic view illustrating filling of a support body in an isolation layer according to an embodiment of the invention. Similar to the support 242 shown in FIG. 2A, the method of forming the support 433 can be a furnace deposition process. In some embodiments, the radial dimension of the support 433 is 100-300 nm. When the support body 433 is cylindrical, its radial dimension represents the diameter of its cross-section. Referring to fig. 4D, the support 433 has a cross-sectional diameter gradually increasing from an end near the substrate 410 upward. Fig. 4D is only an example, and is not intended to limit the specific shape of the supporting body 433 in the embodiment of the present invention.

As shown in fig. 4D, the support 433 substantially fills the end of the hole 430 near the substrate 410, and at the end near the upper surface of the three-dimensional memory, the support 433 does not fill the inside of the hole 430, and a certain gap is left. Through fig. 4D, a vertical structure 430' is formed.

Flow charts are used herein to illustrate the operations performed by methods according to embodiments of the present invention. It should be understood that the preceding operations are not necessarily performed in the exact order in which they are performed. Rather, various steps may be processed in reverse order or simultaneously. Meanwhile, other operations are added to or removed from these processes.

FIG. 4E is a schematic diagram illustrating a planarization process performed on the vertical structure 430' in an embodiment of the invention. Referring to fig. 4E, after step 340, the support 433 material filled inside the isolation layer 432 of the vertical structure 430 'overflows from the inner space of the vertical structure 430' and also covers the upper surface of the stacked structure 420 around it. The planarization process, such as CMP, is performed on the upper surface of the stacked structure 420 to make the support 433 in the vertical structure 430' and the upper surface of the stacked structure 420 flush, and the material of the support 433 on the upper surface of the stacked structure 420 is removed to facilitate the subsequent processes.

Fig. 4F is a schematic view of removing polysilicon on the back side of the substrate in an embodiment of the invention. Referring to fig. 4F, a portion of the polysilicon film on the back surface of the substrate 410 may be removed by a wet etching method, thereby forming a new substrate 411. The substrate 411 shown in fig. 4F has a reduced thickness compared to the substrate 410 in fig. 4E.

Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, changes and modifications to the above embodiments within the spirit of the invention are intended to fall within the scope of the claims of the present application.

Claims

1. A three-dimensional memory comprises a substrate and a stacked structure positioned on the substrate, wherein the stacked structure is provided with a virtual area, the virtual area is provided with a plurality of vertical structures penetrating through the stacked structure, each vertical structure comprises an isolation layer and a support positioned in the isolation layer, and the material of the support is undoped polysilicon.

2. The three-dimensional memory according to claim 1, wherein the spacer layer has a thickness of 5-7 nm.

3. The three-dimensional memory according to claim 1, wherein the support is cylindrical and has a radial dimension of 100 nm and 300 nm.

4. The three-dimensional memory according to claim 1, wherein the support body extends vertically through the stacked structure.

5. The three-dimensional memory according to claim 1, wherein the number of stacked layers of the three-dimensional memory is 96 or more.

6. The three-dimensional memory of claim 1, wherein the plurality of vertical structures are located in a core region and/or a staircase region of the three-dimensional memory.

7. The three-dimensional memory according to claim 1, wherein the material of the isolation layer is a dense silicon oxide formed by oxidizing silicon nitride using an in-situ water vapor oxidation process.

8. A method of forming a three-dimensional memory, comprising the steps of:

providing a semiconductor structure, wherein the semiconductor structure is provided with a substrate and a stacked structure positioned on the substrate, and the stacked structure is provided with a virtual area;

forming a plurality of holes or trenches through the stacked structure in the dummy region;

forming an isolation layer on the inner wall of the hole or the groove of the virtual area; and

and filling a support body in the isolation layer, wherein the support body is made of undoped polysilicon.

9. The method of claim 8, wherein the spacer layer has a thickness of 1-20 nm.

10. The method of claim 8, wherein the support has a radial dimension of 100 nm and 300 nm.

11. The method according to claim 8, wherein the number of stacked layers is 96 or more.

12. The method of claim 8, wherein the dummy virtual area is located within a core area and/or a staircase area of the semiconductor structure.

13. The method of claim 8, wherein the method of filling the support is a furnace deposition process.

14. The method of claim 8, wherein forming the isolation layer comprises:

forming a silicon nitride layer on the inner wall of the hole or the groove of the virtual area;

oxidizing the silicon nitride layer using an in-situ steam oxidation process to form a dense silicon oxide layer as the isolation layer.