CN110706733A - DRAM memory row disturbance error solution method - Google Patents

Abstract

A DRAM memory row disturbance error resolution method, comprising the following steps: S1: each DRAM memory row adopts a two-digit recent access timer to track its recent passive activation information; S2: when a certain memory row has read-write access , generate an active activation command to its adjacent row according to probability N; S3: after the active activation command is determined to be generated, then according to the latest access timer information of the memory row, determine whether to implement an active activation operation; the advantage of the present invention is: in the storage cost Under the premise of being negligible, the active activation command can be accurately sent to the victim memory line, while avoiding unnecessary active activation commands and minimizing the adverse impact on performance.

Description

A solution to DRAM memory row disturbance error

technical field

Aiming at the problem of row disturbance error of DRAM memory in existing computers, the present invention proposes a solution based on passive activation information of memory rows.

Background technique

DRAM memory is widely used for the main memory of computers. Each memory cell of DRAM memory contains a capacitor, and data is mainly stored in the capacitor in the form of electric charge. A large number of memory cells form a two-dimensional memory array, with horizontal memory cells forming rows and vertical cells forming columns. DRAM memory reads and writes data in row units, and each time the data is read and written, the row where the target data is located needs to be activated. When a data row (row) in the DRAM is frequently activated due to reading and writing, the memory cells of the adjacent data rows above and below it will reduce the threshold voltage due to the coupling effect, the leakage current will increase, and the charge in the memory cell capacitor will rapidly increase. churn, resulting in the loss of stored data. This phenomenon in which memory row data is lost due to frequent activation of adjacent rows is called row perturbation error.

The main reason for the row disturbance error is accelerated charge loss of the row memory cells, so a solution is to perform a refresh operation on the row memory cells in time to supplement the charge and protect the data. A common default data refresh operation cycle for DRAM memory is 64 milliseconds. A row that causes other rows to have data errors due to row perturbation is called a victim row, and a row that has row perturbation errors is called a victim row. If the number of activations of the victim row exceeds a certain threshold within the default refresh cycle, it will cause row disturbance errors in the data of the victim row, and it cannot be protected by the default refresh operation in time. Therefore, once the number of activations of the victim row approaches a certain threshold, active activation operations are required to protect the data of the victim row.

An active activation operation is equivalent to a refresh operation at the circuit level. Corresponding to the active refresh operation is the passive refresh operation, which mainly occurs when the memory row is read and written or the default refresh operation. The passive activation operation and the active activation operation have the same effect of protecting row data and resisting disturbance errors. If the memory row has been passively activated recently, there is no need to initiate an active refresh operation to protect the data. The previous methods for solving row disturbance errors rely on active activation operations, and do not consider the data protection effect of passive activation operations, resulting in too many unnecessary active activation operations and adversely affecting performance.

SUMMARY OF THE INVENTION

In order to overcome the above-mentioned defects of the prior art, the present invention proposes a solution method for DRAM row disturbance errors combined with passive activation information of memory rows. The content and features of the present invention include the following:

S1: Each DRAM memory row uses a two-bit last-access timer to track its most recent passive activation

information;

S2: When a memory row has read and write access, an active activation command is generated for its adjacent row according to probability N;

S3: After the active activation command is determined to be generated, it is determined according to the latest access timer information of the memory row.

Whether to implement active activation operation;

The S1 step is as follows: each memory row is equipped with one or two recent access timers. When a passive activation operation occurs on the memory row (due to operations such as read and write, default refresh, etc.), its corresponding recent access timer is initialized to 11, And it is periodically updated in the order of 11, 10, 01, 00 until it finally becomes 00; the threshold for the number of frequent activations of adjacent rows with disturbance errors in the memory row is R, and the time T required to activate R times determines The latest access timer update period; the update period of the two-digit recent access timer is T/3, so it takes a period T to update from 11 to 00.

The S2 step is specifically: each time a data access occurs, the random number generator in the memory controller generates a random number r between [0, n), and the probability N is equivalent to the value of the random number r in [0, n). rN); if r is less than or equal to nN, it means that an event with probability N occurs, that is, an active activation command to adjacent rows is generated; otherwise, no active activation command is generated.

The step S3 is specifically: after the active activation command is generated, check the value of the most recent access timer of the memory row to be activated, if the value is 00, send the active activation command to the DRAM memory; otherwise, cancel the active activation command.

The advantages of the present invention are: on the premise of negligible storage cost, the active activation command can be accurately sent to the victim memory row, and unnecessary active activation commands are avoided, and the adverse impact on performance is minimized.

Description of drawings

FIG. 1 is a schematic diagram of the DRAM row disturbance error problem described by the method of the present invention.

FIG. 2 is the update process of the most recent access timer of the method of the present invention.

Figure 3 is a main flow chart of the method of the present invention.

Detailed ways

The technical solutions of the method of the present invention will be further described below in conjunction with the accompanying drawings and embodiments.

Figure 1 is a description of the DRAM row disturbance error problem. The memory cells in the DRAM form a two-dimensional array, and the aggressor row is frequently accessed, causing disturbance to the two adjacent victim rows above and below it. , resulting in a row perturbation error for the victim row. R represents the lower limit of the number of times the victim row is activated due to data access when row disturbance errors occur in the victim row. Period T is the time it takes for the harmful line to activate R times. Because the same activation times take different time for different harmful lines of different applications, the final period T can be selected from the minimum value of the currently collected period T. The period T must be less than the default data refresh period, otherwise, the default data refresh operation can resist row disturbance errors and protect data. If the time period is less than the period T, the victim row will not have row disturbance errors; and when the time period is greater than the period T, the victim row may be subject to row disturbance errors, which requires necessary protection.

Each memory line has a two-digit recent access timer, which is used to display whether the current memory line has a passive activation operation recently. Figure 2 shows the update process of the two-digit recent access timer. At time _t1 , when the memory row is passively activated (because of operations such as read and write, default refresh, etc.), the corresponding recent timer is set to 11, and thereafter every The value of the T/3 timer decrements in descending order until 00. According to the value of the timer, it can be judged whether the memory row has been activated in the most recent T period. If the value of the timer is 00, it means that the memory row has not been activated for the last T period; otherwise, there is.

If the value of the most recent access timer is still in the process of decrementing (not to 00), but the memory row is passively activated, the value of the most recent timer is reset to 11, and then decremented at the original default T/3 interval. At this time, the value of the timer cannot indicate that the memory row did not have an activation operation in the past period T, but only indicated that the memory row did not have an activation operation in the past (2/3T, T) period. Because the timing of passive activation cannot be predicted in advance, once it occurs in the process of decreasing the timer in descending order, it will cause the final 00 value of the timer to appear in advance. In Figure 2, a passive activation operation occurs at time _t2 , the timer is reset to ₁₁ , and the timer is set to 00 at time t4. If the timer is set to ₁₁ at time _t2 and no passive activation occurs, the timer is not set to 00 until time t5. _The difference between time t4 and time _t5 is the characterization error introduced by the passive activation operation. The maximum value that characterizes the error is T/3.

The existence of characterization errors makes the value T represented by the recent access timer shorter than the real value, that is, when the harmful line is considered to be shorter than the time period T, R activation operations occur, and active activation operations are initiated in advance. Therefore, characterization errors lead to overprotection of victim rows, and the final period T can be appropriately extended to offset the effects of characterization errors.

Fig. 3 is the main flow chart of the present invention, first generating an active activation command with probability N. When the memory row row[i] has read and write access, a random number r between 0 and n is generated and the values of r and nN are compared. If r is less than nN, it means that an event with probability N occurs, which satisfies the first condition of initiating an active activation command for the victim rows row[i-1] and row[i+1]. The second condition is to check the value of the most recent access timer (RAC) of the victim row row[i+1] and row[i-1], if the value is 00, send an active activation command to the memory; if the value is not 00, It means that the victim row is still in the period T and is protected by the latest passive activation operation, so it is not necessary to send an active activation command.

Generating active refresh commands in a probabilistic manner can avoid the storage cost of recording the access times of each memory row. The disadvantage is that there may be a missed diagnosis rate, that is, an active activation command should be generated but not actually generated. Reasonable selection of the probability value N can control the missed diagnosis rate. The relationship between probability N and missed diagnosis rate P: P=1-(1-e ^N*R ) ^k . Among them, k represents the number of visits to the memory row in the normal working years. According to the normal working time of 10 years, the value of k is 25 billion, and R=32000 times. As long as the value of the probability N is set to 0.2%, the missed diagnosis can be eliminated. The rate was controlled to a negligible level of 4.0×10 ^-18 .

The most recent access timer for each memory row requires only two bits of storage space. Considering 8Gb of DRAM memory and 8Kb of memory rows, all recent access timers occupy only 2M of storage space and are constructed in groups of 512 bits in size. Because the most recent access timer of the memory row needs to be accessed frequently, in order to speed up the access speed, the timer is set in the memory controller. At the same time, expand the memory controller, add a random number generator, so that a random number between [0, n) is generated every time there is data access, and access the latest timer group to determine whether to send an active activation command to the DRAM memory.

The content described in the embodiments of the present specification is only an enumeration of the realization forms of the inventive concept, and the protection scope of the present invention should not be regarded as limited to the specific forms stated in the embodiments, and the protection scope of the present invention also extends to those skilled in the art. Equivalent technical means that can be conceived by a person based on the inventive concept.

Claims (1)

1. A DRAM memory row disturbance error solution method comprises the following steps:

s1, each DRAM memory row adopts a two-bit latest access timer to track the latest passive activation information;

s2, when some memory line has read-write access, it generates active activation command to its adjacent line according to probability N;

s3, after the active activation command is determined to be generated, determining whether to execute the active activation operation according to the latest access timer information of the memory row;

wherein the step of S1 is specifically as follows: each memory row is provided with a two-bit latest access timer, when the memory row is subjected to passive activation operation, the corresponding latest access timer is initialized to 11 and is periodically updated according to the sequence of 11, 10, 01 and 00 until the latest access timer is finally 00; the method comprises the steps that a threshold value of the frequent activation times of adjacent rows with disturbance errors of a memory row is set to be R, and the time T required for activating R times determines the update period of a latest access timer; the update period of the two-bit latest access timer is T/3, so the period T is needed from 11 to 00;

wherein the step of S2 is specifically as follows: each time data access occurs, a random number generator in the memory controller generates a random number r between [0, N), and the value of the probability N equivalent to the random number r is between [0, rN); if r is less than or equal to nN, the event with the probability of N is generated, namely an active activation command for an adjacent row is generated; otherwise, not generating an active activation command;

wherein the step of S3 is specifically as follows: after the active activation command is generated, checking the latest access timer value of the memory row to be activated, and if the value is 00, sending the active activation command to the DRAM; otherwise, the proactive activation command cancels.

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