CN110660845A - Manufacturing method of semiconductor structure - Google Patents

Abstract

A method of fabricating a semiconductor structure includes providing a p-type source/drain epitaxial feature and an n-type source/drain epitaxial feature, forming a layer of semiconductor material over the n-type source/drain epitaxial feature and the p-type source/drain epitaxial feature, treating the layer of semiconductor material with a germanium-containing gas, wherein the processing of the layer of semiconductor material forms a germanium-containing layer over the layer of semiconductor material, etches the germanium-containing layer, wherein the etching of the ge-containing layer removes the ge-containing layer formed over the n-type source/drain epitaxial features and the layer of semiconductor material formed over the p-type source/drain epitaxial features, and forming a first source/drain contact over the layer of semiconductor material remaining over the n-type source/drain epitaxial feature and a second source/drain contact over the p-type source/drain epitaxial feature. The composition of the layer of semiconductor material may be similar to the composition of the n-type source/drain epitaxial features.

Description

Manufacturing method of semiconductor structure

technical field

Embodiments of the present invention relate to semiconductor fabrication techniques, and more particularly, to semiconductor structures with reduced contact resistance source/drain contacts and methods of fabricating the same.

Background technique

The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in integrated circuit materials and design have produced several generations of integrated circuits, each generation having smaller and more complex circuits than the previous generation. Over the course of integrated circuit evolution, functional density (ie, the number of interconnect devices per chip area) typically increases as geometry size (ie, the smallest element (or line) that can be produced using a manufacturing process) shrinks. This scale-down process typically provides some benefits by increasing production efficiency and reducing associated costs. Such scaling also increases the complexity of processing and fabricating integrated circuits.

For example, efforts have been made to fabricate integrated circuit devices with improved performance, including reducing resistance at the interface between source/drain features and contacts formed on the source/drain features. While such methods of reducing resistance are often adequate, they are not satisfactory in all respects. In some cases, these methods often may involve complex processing steps (thus increasing production costs) and may undesirably thermally damage the integrated circuit device. For these and other reasons, improvements in this area are desired.

SUMMARY OF THE INVENTION

According to some embodiments of the present invention, methods of fabricating semiconductor structures are provided. The method includes: providing p-type source/drain epitaxial features and n-type source/drain epitaxial features formed at a first temperature; forming a layer of semiconductor material on the n-type source/drain epitaxial features and at a second temperature over the p-type source/drain epitaxial feature, wherein the composition of the semiconductor material layer is similar to that of the n-type source/drain epitaxial feature, and wherein the second temperature is less than the first temperature; treating the semiconductor material layer with a germanium-containing gas, wherein the processing of the semiconductor material layer forms a germanium-containing layer over the semiconductor material layer; the germanium-containing layer is etched, wherein the etching of the germanium-containing layer removes the germanium-containing layer formed over the n-type source/drain epitaxial features and the germanium-containing layer formed over the p-type a layer of semiconductor material over the source/drain epitaxial feature; and forming a first source/drain contact over the layer of semiconductor material remaining over the n-type source/drain epitaxial feature and over the p-type source/drain A second source/drain contact is formed over the epitaxial feature.

According to further embodiments of the present invention, methods of fabricating semiconductor structures are provided. The method includes forming a first trench and a second trench in the interlayer dielectric layer to expose a first source/drain epitaxial feature formed over the first fin and a first source/drain epitaxial feature formed over the second fin, respectively a second source/drain epitaxial feature, wherein the first source/drain epitaxial feature is n-type and the second source/drain epitaxial feature is p-type; depositing n in the first and second trenches type semiconductor layer; forming a germanium-containing layer over the n-type semiconductor layer; removing the germanium-containing layer from the first trench, wherein the removing step removes the n-type semiconductor layer from the second trench; forming silicide layers over the n-type semiconductor layer and over the second source/drain epitaxial features in the second trenches; and forming source/drain layers over the silicide layers in the first trenches and the second trenches, respectively drain contact.

According to yet other embodiments of the present invention, semiconductor structures are provided. The semiconductor structure includes a first source/drain epitaxial component of a first conductivity type disposed in the semiconductor layer, the first source/drain epitaxial component has a first resistance; a second source/drain electrode of the second conductivity type Epitaxial features are disposed in the semiconductor layer, the second conductivity type is different from the first conductivity type, wherein the first source/drain and the second source/drain epitaxial features are disposed adjacent to the first source/drain and the second The respective metal gate structures of the source/drain epitaxial components; at least one epitaxial semiconductor material layer is disposed above the first source/drain epitaxial component, wherein the at least one epitaxial semiconductor material layer has a second resistance, the second resistance lower than a first resistance; and a first source/drain contact and a second source/drain contact are respectively disposed over the at least one epitaxial semiconductor material layer and over the second source/drain epitaxial component, Wherein the bottom surface of the second source/drain contact is lower than the bottom surface of the first source/drain contact.

Description of drawings

The content of the embodiments of the present invention can be better understood through the following detailed description in conjunction with the accompanying drawings. It is emphasized that, in accordance with standard industry practice, many features are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

1A and 1B are flowcharts of methods of manufacturing different oriented workpieces according to embodiments of the present invention.

2 is a schematic top view of a workpiece with different orientations according to an embodiment of the present invention.

Figures 3, 4, 5, 6A, 7A, 8, 9, 10 and 11 are workpieces taken along dashed lines AA' and BB' of Figure 2 according to different aspects of an embodiment of the present invention Cross-sectional schematic diagram of the intermediate stage of the fabrication method.

6B shows a portion of the workpiece of FIG. 6A during an intermediate stage of a manufacturing method, according to various aspects of an embodiment of the present invention.

6C and 6D illustrate concentration profiles of a portion of the workpiece of FIG. 6A during an intermediate stage of a manufacturing method, according to different aspects of an embodiment of the present invention.

7B shows a portion of the workpiece of FIG. 7A during an intermediate stage of a manufacturing method, according to various aspects of an embodiment of the present invention.

Description of reference numbers:

100 ~ method;

102, 104, 106, 108, 110, 112, 114, 116-block;

200～Workpiece;

202～substrate;

204A, 204B ~ fins;

208～Isolation parts;

210A, 210B ~ installation area;

212～gate spacer;

214, 216 ~ source/drain components;

218, 240 ~ interlayer dielectric layer;

220A, 220B ~ metal gate structure;

222～Interface layer;

224～gate dielectric layer;

226～work function metal layer;

228～block conductive layer;

230 ~ part;

242, 244 ~ groove;

250, 260 ~ gas mixture;

252～n-type semiconductor layer (SiP layer);

254～SiPGe layer;

256 ~ germanium-free region (SiP layer);

262 ~ germanium-containing layer;

270～chlorine gas;

280～metal layer;

282 ~ silicide layer;

292～conductive material;

294 ~ source/drain contacts;

302, 304, 306, 308 ~ concentration profile;

AA', BB'～dotted line;

T _SiP ~ thickness;

X, Y ~ direction.

Detailed ways

The following provides many different embodiments or examples for implementing different components of embodiments of the invention. Specific examples of components and configurations are described below to simplify embodiments of the invention. Of course, these are only examples, and are not intended to limit the embodiments of the present invention. For example, references in the description that the first part is formed on or over the second part may include embodiments in which the first and second parts are in direct contact, and may also include additional parts formed on the first and second parts between, so that the first and second parts are not in direct contact with each other. In addition, the embodiments of the present invention may reuse reference numerals and/or letters in different examples, the repetition is for the purpose of simplicity and clarity, and does not represent a specific relationship between the different embodiments and/or configurations discussed.

Furthermore, embodiments of the present invention may repeat reference numerals and/or letters in different instances. This repetition is for the purpose of simplicity and clarity, and does not in itself represent a relationship between the various embodiments and/or configurations discussed. Additionally, subsequent embodiments of the invention may include forming a component on another component, connecting and/or coupling this component to another component, may include forming embodiments in which these components are in direct contact, or may include forming additional components that are inserted into these components. between components so that these components are not in direct contact. In addition, spatially relative terms such as "lower", "higher", "horizontal", "vertical", "above", "above", "below", "below", "upper", " "Down," "top," "bottom," etc. and their derivatives (eg, "horizontally", "downwardly," "upwardly," etc.) are used to simplify the separation of some components from other components of the relation. Spatially relative terms are used to encompass different orientations of a device containing a component. In addition, when "about," "approximately," and similar terms are used to describe numbers or ranges of numbers, such terms are used to encompass numbers within a reasonable range, including the number described, eg, within +/- 10 of the number described % or other values understood by those skilled in the art to which this disclosure belongs. For example, the term "about 5 nanometers" covers a size range of 4.5 nanometers to 5.5 nanometers.

Embodiments of the present invention generally relate to semiconductor devices and methods of fabricating the same. More specifically, some embodiments relate to forming source and drain (S/D) contacts in field effect transistors (FETs), such as planar or three-dimensional (fin) fields The field effect transistor includes an n-type field effect transistor (n-type FET or NFET) region and a p-type field effect transistor (p-type FET or PFET) region. Additionally, the disclosed method provides a method of forming source/drain contacts with reduced contact resistance by forming a low resistance epitaxial semiconductor between the source/drain features and the source/drain contacts layer, especially in the n-type field effect transistor region. In some embodiments, the n-type epitaxial semiconductor layer is selectively formed over the source/drain features of the n-type field effect transistor and not over the source/drain features of the p-type field effect transistor, the n-type epitaxial semiconductor layer Contains, for example, silicon or silicon carbon doped with phosphorus or arsenic. The n-type epitaxial semiconductor layers disclosed herein can be formed by a process (eg, lower process temperature) that is different from the process used to form the n-type epitaxial source/drain features, resulting in improved electrical properties. In at least some embodiments, by selectively forming n-type epitaxial semiconductor layers using the methods disclosed herein, thermal damage, process complexity, and production costs incurred during device fabrication processes can be reduced, and device performance can be improved.

1A-1B illustrate a flow diagram of a method 100 for fabricating a workpiece (also referred to as a semiconductor structure) 200 having different field effect transistors. The method 100 is described with reference to FIGS. 2 to 11 ; wherein, according to an embodiment of the present invention, FIG. 2 is a schematic top view of the workpiece 200 , and FIGS. 3 to 11 are respectively along the lines passing through the fins 204A in the intermediate stages of the method 100 . A schematic cross-sectional view of workpiece 200 (or portion 230 of workpiece 200 ) through dashed line AA' and dashed line BB' through fin 204B. For illustrative purposes, a device region 210A including a schematic cross-sectional view of fins 204A and a device region 210B including a schematic cross-sectional view of fins 204B are shown side-by-side in FIGS. 3-11 . The method 100 is merely an example, and is not intended to limit embodiments of the invention to what is expressly described herein. Additional steps may be provided before, during, and after method 100 , and for other embodiments of method 100 , some of the steps described herein may be replaced or eliminated.

Referring first to block 102 of FIG. 1 and FIGS. 2-3 , method 100 provides (or is provided in) a workpiece 200 including fins 204A and 204B protruding from substrate 202 and oriented longitudinally in the X direction. The bottoms of fins 204A and 204B are separated by spacer members 208 disposed over substrate 202 . Workpiece 200 also includes metal gate structures 220A and 220B oriented longitudinally in the Y direction, forming different field effect transistors having source/drain features 214 and 216 disposed over fins 204A and 204B, respectively. In the illustrated embodiment, workpiece 200 also includes an interlayer dielectric (ILD) layer 218 disposed over isolation features 208 , fins 204A and 204B, and source/drain features 214 and 216 . Although three-dimensional structures or fins are described for forming active regions of various fin field effect transistors, embodiments of the present invention are not limited thereto. For example, fins 204A and 204B may be referred to as semiconductor layers used to form planar field effect transistors. For illustrative purposes, embodiments of the present invention will continue to use fins 204A and 204B as example active regions. Although not shown here, workpiece 200 may include a number of features, such as contact etch stops disposed over isolation features 208 , fins 204A and 204B, metal gate structures 220A and 220B, and source/drain features 214 and 216 layer (contact etch-stop layer, CESL). The different components of workpiece 200 are discussed in detail below.

The substrate 202 may comprise elemental (single element) semiconductors such as silicon in a crystal structure and/or germanium in a crystal structure; compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and/or Or indium antimonide; alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP; or a combination of the foregoing. The substrate 202 may be a single layer of material having a uniform composition. Alternatively, substrate 202 may comprise multiple layers of materials having similar or different compositions suitable for integrated circuit device fabrication. In one example, the substrate 202 may be a silicon-on-insulator (SOI) substrate having a semiconductor silicon layer formed on a silicon oxide layer.

In some embodiments where substrate 202 includes field effect transistors, various doped regions, such as source/drain regions, are formed in or on substrate 202 . Depending on design requirements, the doped regions may be doped with n-type dopants (eg, phosphorus or arsenic) and/or p-type dopants (eg, boron). The doped regions can be formed directly on the substrate 202, in a p-well structure, in an n-well structure, in a dual-well structure, or using a bump structure. The doped regions can be formed by implanting dopant atoms, in-situ doped epitaxial growth, and/or other suitable techniques.

Device region 210A including fins 204A may be suitable for forming n-type finFETs, and device region 210B including fins 204B may be suitable for forming p-type finFETs. This configuration is for illustrative purposes only, and is not intended to limit embodiments of the present invention. Fins 204A and 204B may be fabricated using suitable processes including lithography and etching processes. The lithography process may include forming a photoresist layer (resist; not shown) overlying the substrate 202, exposing the photoresist to the pattern, performing a post-exposure bake process, and developing the photoresist to form a mask element (not shown) including the photoresist. The recesses are then etched into the substrate 202 using a masking element, leaving the fins 204A and 204B on the substrate 202. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes.

Many other embodiments of methods for forming fins 204A and 204B may be suitable. For example, the fins 204A and 204B may be patterned using a double-patterning or multi-patterning process. Typically, double-patterning or multi-patterning processes combine lithography and self-alignment processes, which, for example, allow patterns to be produced with pitches smaller than that achievable using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the fins can then be patterned using the remaining spacers or mandrels.

Isolation features 208 may include silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), low-k dielectric materials, and/or other suitable insulating materials . The isolation features 208 may be shallow trench isolation (STI) features. In one embodiment, isolation features 208 are formed by etching trenches in substrate 202 during formation of fins 204A and 204B. The trenches may then be filled with the isolation material described above, followed by a chemical mechanical planarization (CMP) process. The isolation features 208 may also use other isolation structures, such as field oxide, local oxidation of silicon (LOCOS), and/or other suitable structures. The isolation feature 208 may comprise a multi-layer structure, for example, with one or more thermal oxide liner layers.

Source/drain features 214 and 216 are disposed in fins 204A and 204B, respectively, each fin 204A and 204B adjacent to metal gate structures 220A and 220B. Although only one source/drain feature 214 and one source/drain feature 216 are shown, multiple source/drain features 214 may be provided adjacent to metal gate structures 220A and 220B in device region 210A and may provide A plurality of source/drain features 216 adjoin metal gate structures 220A and 220B in device region 210B. Each of the source/drain features 214 and 216 may be suitable for use in a p-type finFET device (eg, p-type conductivity type epitaxial material) or an n-type finFET device (eg, n-type conductivity type epitaxial material). Throughout the present embodiments, "p-type" refers to semiconductor materials doped with p-type dopants such as boron, indium, other p-type dopants or combinations of the foregoing, semiconductor materials such as silicon germanium, And "n-type" refers to a semiconductor material doped with n-type dopants such as phosphorus, arsenic, other n-type dopants, or combinations of the foregoing, such as carbon or carbon silicon.

In the illustrated embodiment, the source/drain features 214 are suitable for forming n-type FinFET devices, and the source/drain features 216 are suitable for forming p-type FinFET devices. The n-type epitaxial material may comprise one or more epitaxial layers of silicon (epiSi) or silicon carbon (epi SiC) doped with the n-type dopants described above. The p-type epitaxial material may comprise one or more epitaxial layers of semiconductor material, such as silicon germanium (epi SiGe), silicon germanium carbon (epi SiGeC), germanium (epi Ge), wherein the semiconductor material is doped with the aforementioned p-type dopants . Although the source/drain features 214 and 216 are shown as hexagonal, embodiments of the present invention are not so limited. For example, source/drain features 214 and 216 may take other geometries, such as diamond shapes.

The source/drain features 214 and 216 may be formed by any suitable technique, such as an etching process followed by one or more epitaxy processes. In one example, one or more etching processes are performed to remove portions of fins 204A and 204B to form grooves (not shown) in these portions, respectively. The cleaning process may be performed with a hydrofluoric acid (HF) solution or other suitable solution to clean the grooves. Subsequently, one or more epitaxial growth (eg, doping) processes, such as in-situ doping processes, ion implantation processes, diffusion processes, other processes, or combinations thereof, may be performed to form epitaxial features in the recesses. In some embodiments, a selective epitaxial growth (SEG) process is performed to grow the epitaxial material, which is an in-situ doping process during which a dopant (eg, for n Phosphorus for p-type epitaxial materials or boron for p-type epitaxial materials) is introduced into semiconductor materials such as silicon or silicon germanium (eg, by adding dopants to the source material of a selective epitaxial growth process). The selective epitaxial growth process can be implemented by any deposition technique, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma Chemical vapor deposition (High Density Plasma CVD, HDP-CVD), metal organic chemical vapor deposition (Metal OrganicCVD, MO-CVD), remote plasma chemical vapor deposition (remote plasma CVD, RP-CVD), plasma enhanced chemical vapor deposition Deposition (Plasma Enhanced CVD, PE-CVD), low pressure chemical vapor deposition (low-pressure CVD, LP-CVD), atomic layer chemical vapor deposition (atomic layer CVD, AL-CVD), atmospheric pressure chemical vapor deposition (atmospheric pressure CVD, AP-CVD), vapor-phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (ultra-high vacuum CVD, UHV-CVD), molecular beam epitaxy (molecular beam epitaxy), other suitable methods or the aforementioned combination. The selective epitaxial growth process is performed by introducing gaseous and/or liquid precursors into the source/drain regions of fins 204A or 204B to form source/drain features 214 and 216, respectively. In some embodiments, a patterned mask may be used to aid in the selective epitaxial growth process. In the illustrated embodiment, forming the source/drain features 214 includes introducing a silicon-containing precursor gas (eg, SiH ₄ ) together with a phosphorus-containing gas (eg, PH ₃ ). In a further described embodiment, forming the source/drain features 216 includes introducing a silicon-containing precursor gas (eg, _SiH4 ) and/or a germanium-containing precursor gas (eg, _B2H6 ) with a dopant-containing gas (eg, _B2H6 ). For example GeH ₄ ). One or more annealing processes may be performed to activate the epitaxial material. The annealing process includes rapid thermal annealing (RTA), laser annealing, other suitable annealing processes, or a combination of the foregoing.

As a result, in the illustrated embodiment, source/drain features 214 comprise one or more layers of phosphorous-doped silicon (SiP), and source/drain features 216 comprise one or more layers of boron-doped silicon germanium (SiGeB). In some embodiments, the amount of germanium in the SiGeB ranges from about 10% (eg, atomic percent) to about 50%. In the illustrated embodiment, to achieve desired device performance, the source/drain features 214 and 216 may each be formed with a total thickness of about 35 nanometers to about 60 nanometers, although embodiments of the invention are not limited to this thickness range .

Formation of the source/drain features 214 may be performed in-situ as described above at a growth temperature of about 600 degrees Celsius to about 800 degrees Celsius (eg, by heating the workpiece 200 to about 600 degrees Celsius to about 800 degrees Celsius). doping process. The formed source/drain features 214 may be a single-layer structure or a multi-layer structure, each layer comprising the same epitaxial material SiP but different dopant concentrations (ie, different phosphorus concentrations). In a non-limiting example, the source/drain features 214 comprise three SiP epitaxial layers, each SiP layer having a different phosphorous concentration ranging from about 2×10 ²⁰ cm ⁻³ to about 3×10 ²¹ . cm ^-3 . Wherein, the phosphorus concentration of the uppermost epitaxial layer of the source/drain features 214 is lower than the phosphorus concentration of the lowermost epitaxial layer formed directly above the fin 204A, and the phosphorus concentration of the lowermost epitaxial layer is lower than that of the middle epitaxial layer phosphorus concentration. Of course, the source/drain features 214 are not limited to three layers, and the relative concentration of the dopant P may be different from the relative concentration of the dopant P described herein.

In some embodiments, workpiece 200 also includes a silicon germanium layer (doped or undoped; not shown) disposed over source/drain features 216 having a thickness of about 1 nanometer to about 10 nanometers, wherein The germanium content in the silicon germanium layer is greater than the germanium content in the SiGeB of the source/drain features 216 . In one example, the germanium content in the silicon germanium layer is greater than about 50% and less than about 90%. Alternatively, workpiece 200 may include a pure germanium layer (ie, having a germanium content greater than about 99%; not shown) disposed over source/drain features 216 having a thickness of about 1 nanometer to about 10 nanometers. In many embodiments, having an additional layer of silicon germanium or pure germanium disposed over source/drain features 216 increases the amount of germanium present in device region 210B, which may be adapted to accommodate subsequent processing of method 100 discussed in detail below step. In this regard, the silicon germanium layer and/or the pure germanium layer acts as a sacrificial layer and thus can be formed to a thickness much smaller than the thickness of the source/drain features 216 (eg, about 35 nanometers to about 40 nanometers).

Metal gate structures 220A and 220B each include an interface layer 222 , a gate dielectric layer 224 , a work function metal layer 226 and a bulk conductive layer 228 . The interface layer 222 may comprise silicon oxide (SiO ₂ ), silicon oxynitride (SiON), germanium oxide (GeO ₂ ), other suitable materials, or a combination of the foregoing. The step of forming the interface layer 222 on the fins 204A and 204B may be by any suitable method, such as chemical oxidation, thermal oxidation, or deposition processes by chemical vapor deposition or atomic layer deposition, other suitable methods, or combinations of the foregoing. In some embodiments, the interface layer 222 may be omitted.

The gate dielectric layer 224 may include silicon oxide (SiO ₂ ), silicon oxynitride (SiON), aluminum oxide silicon (AlSiO), high-k dielectric materials such as hafnium oxide (HfO ₂ ), Zirconium oxide (ZrO ₂ ), lanthanum oxide (La ₂ O ₃ ), titanium oxide (TiO ₂ ), yttrium oxide (Y ₂ O ₃ ), strontium titanate (SrTiO ₃ ), other suitable metal oxides, or combinations of the foregoing . In the illustrated embodiment, the gate dielectric layer 224 comprises a high-k dielectric material having a dielectric constant greater than that of silicon oxide. The gate dielectric layer 224 may be deposited by chemical oxidation, thermal oxidation, chemical vapor deposition, atomic layer deposition, or other suitable methods.

The work function metal layer 226 may be a p-type or n-type work function layer, which are used for p-type FinFETs and n-type FinFETs, respectively. The p-type work function layer includes metals such as titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten (W), platinum (Pt), or a combination of the foregoing. The n-type work function layer includes metals such as titanium (Ti), aluminum (Al), tantalum carbide (TaC), tantalum carbide nitride (TaCN), tantalum silicon nitride (TaSiN), or a combination of the foregoing. In some embodiments, metal gate structures 220A and 220B each comprise more than one work function metal layer, which may be of similar or different types. The bulk conductive layer 228 may include aluminum (Al), tungsten (W), cobalt (Co), copper (Cu), ruthenium (Ru), and/or other suitable materials. Although not shown, the metal gate structures 220A and 220B may each include suitable film layers, such as barrier layers and capping layers.

In many embodiments, before forming the source/drain features 214 and 216, a dummy gate structure (not shown) is formed at the location of the metal gate structures 220A and 220B, the dummy gate structure including the interface layer 222, A dummy gate electrode (including, for example, polysilicon) and, in some examples, a gate dielectric layer. Then, as described above, in a gate replacement process, at least part of the dummy gate structures are replaced with metal gate structures 220A and 220B. To complete the gate replacement, an interlayer dielectric layer 218 (and in some examples a contact etch stop) is first formed over the fins 204A and 204B, the source/drain features 214 and 216, the dummy gate structure, and the isolation features 208 layer (not shown)). The dummy gate electrode and gate dielectric layer can then be completely removed and metal gate structures 220A and 220B formed at these locations in a "high-k last" gate replacement process . Alternatively, after the dummy gate electrode is removed, the gate dielectric layer of the dummy gate structure is left, and the gate dielectric layer becomes the gate dielectric layer 224 and a metal is formed over the gate dielectric layer 224 Various material layers of the gate structures 220A and 220B to complete the "high-k pre-made" gate replacement process. The layers of various materials may be formed by any suitable deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, other suitable processes, or combinations of the foregoing. Then, one or more chemical mechanical planarization processes may be performed to planarize the top surfaces of the metal gate structures 220A and 220B and the top surface of the interlayer dielectric layer 218 .

Additionally, workpiece 200 may include gate spacers 212 disposed along sidewalls of metal gate structures 220A and 220B. The gate spacers 212 may include dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, and/or other suitable dielectric materials. The gate spacer 212 may be a single-layer structure or a multi-layer structure. Formation of gate spacers 212 may be performed by first depositing a blanket layer of spacer material over workpiece 200, followed by anisotropic ( anisotropic) etching process to remove portions of the spacer material to form gate spacers 212 along the sidewalls of the dummy gate structures. During the gate replacement process as previously described, gate spacers 212 are left as part of workpiece 200 .

For embodiments in which workpiece 200 includes a contact etch stop layer, the contact etch stop layer may include silicon nitride, silicon oxynitride, silicon oxycarbonitride, and/or other suitable materials, and the contact etch stop layer may be formed by chemical vapor deposition , physical vapor deposition, atomic layer deposition, other suitable methods, or a combination of the foregoing. The interlayer dielectric layer 218 may comprise a dielectric material, such as tetraethylorthosilicate (TEOS), undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (borophosphosilicate glass, BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable media electrical material. The interlayer dielectric layer 218 may comprise a multi-layered structure having various dielectric materials. The interlayer dielectric layer 218 may be formed by a deposition process such as chemical vapor deposition, physical vapor deposition, flowable chemical vapor deposition (FCVD) prior to the gate replacement process as previously described , spin-on glass (SOG), other suitable processes, or a combination of the foregoing. After the formation of the interlayer dielectric layer 218, a planarization process, such as chemical mechanical planarization, may be performed to expose the top of the dummy gate structure, allowing the gate replacement process as previously described to be completed.

Referring now to block 104 and FIG. 4 of FIG. 1A , method 100 forms trenches 242 over source/drain features 214 in device region 210A and trenches over source/drain features 216 in device region 210B Slot 244. For simplicity, the following description is provided with reference to a portion 230 of workpiece 200 as shown in FIG. 3 . To form trenches 242 and 244, method 100 begins by forming an interlayer dielectric layer 240 similar to interlayer dielectric layer 218 described above over workpiece 200 (or portion 230). Method 100 then patterns and etchs interlayer dielectric layers 240 and 218 to form trenches 242 and 244 . Specifically, the method 100 may first form a mask element (not shown) including a resist (eg, photoresist) layer, a hard mask layer, and/or a bottom layer (eg, a bottom layer) over the workpiece 200 anti-reflective coating). The method 100 then proceeds to pattern the photoresist layer, thereby forming openings (not shown) in the mask element. The interlayer dielectric layers 240 and 218 are then etched using the patterned photoresist layer as an etch mask to form trenches 242 and 244 that expose the source/drain features 214 and 216, respectively. The etching of the interlayer dielectric layers 240 and 218 may be performed by any suitable process, including dry etching, wet etching, reactive ion etching, other suitable processes, or a combination of the foregoing. The mask element is then removed by any suitable method, such as photoresist stripping or plasma ashing.

Referring to block 106 of FIG. 1 and FIG. 5 , method 100 forms n-type semiconductor layer 252 in trenches 242 and 244 and over the top surface of interlayer dielectric layer 240 . Notably, n-type semiconductor layer 252 is deposited over the epitaxial crystalline material of source/drain features 214 and 216 and dielectric features such as interlayer dielectric layer 240 and gate spacer 212 . Portions of n-type semiconductor layer 252 formed over source/drain features 214 and 216 are crystalline and epitaxially grown, similar in composition to the epitaxial material contained in source/drain features 214, while in dielectric Portions of n-type semiconductor layer 252 formed over features (eg, interlayer dielectric layer 240, gate spacer 212, etc.) are amorphous. As discussed below, a subsequent etch process will selectively remove amorphous portions of n-type semiconductor layer 252 from the dielectric features and will leave n-type semiconductor disposed over source/drain features 214 and 216 The crystalline portion of layer 252.

The n-type semiconductor layer 252 may comprise any suitable n-type semiconductor material, such as, for example, silicon doped with phosphorus (SiP), silicon doped with arsenic (SiAs), silicon doped with phosphorus (SiPC), doped silicon Arsenic on silicon carbon (SiAsC), other n-type semiconductor materials, or combinations of the foregoing. Accordingly, although the following disclosure refers to n-type semiconductor layer 252 as a SiP layer, this is merely an exemplary embodiment, and thus does not limit n-type semiconductor layer 252 to include only SiP. In many embodiments, method 100 comprises depositing a silicon-containing gas (eg, by heating workpiece 200 to a temperature of about 300 degrees Celsius to about 500 degrees Celsius) at a temperature of about 300 degrees Celsius to about 500 degrees Celsius A gas mixture 250 of SiH ₄ ) and a phosphorus-containing gas (eg, PH ₃ ) to form a SiP layer (also referred to as an n-type semiconductor layer) 252 . In an exemplary embodiment, the phosphorus concentration in SiP layer 252 is about 2×10 ²¹ cm ⁻³ .

Conversely, the epitaxy of the source/drain features 214 is formed at a higher temperature (eg, about 600 degrees Celsius to about 800 degrees Celsius as described above) than the crystalline portion of the SiP layer 252 as described above. SiP. Additionally, the resistivity of the crystalline portion of SiP layer 252 is less than about 1/1/2 the resistivity of the epitaxial SiP of source/drain features 214 when compared at similar doping levels (ie, with similar phosphorus concentrations). 2. As an illustrative example, the resistivity of source/drain features 214 may be about 0.6 milliOhm·cm (mΩ·cm) to about 0.8 mΩ·cm, and the resistivity of SiP layer 252 may be about 0.2 mΩ·cm to about 0.4 mΩ·cm. Such a decrease in resistivity can be attributed to the lower concentration of point defects present in SiP layer 252 due to the lower process temperature than SiP layer 252 in source/drain features 214 formed at higher process temperatures. In this regard, the process temperature for forming the SiP layer 252 may be controlled at about 300 degrees Celsius to about 500 degrees Celsius so that the resistivity of the SiP is lower than the resistivity of the SiP of the source/drain features 214 . On the one hand, if the process temperature is below about 300 degrees Celsius, the growth of SiP can be amorphous or polycrystalline, rather than single crystal, which makes the resistivity lower than that of amorphous or polycrystalline SiP. In addition, when the process temperature is lower than about 300 degrees Celsius, the growth rate of SiP is also reduced, extending the process time. Furthermore, at lower processing temperatures, higher carbon number _silane precursors, such as _Si4H10 and _Si5H12 , may be required, which may increase the associated cost _of the production process. On the other hand, if the process temperature is above about 500 degrees Celsius, components of the metal gate structures 220A and 220B may suffer unwanted thermal damage. In embodiments of the present invention, reducing the resistivity of the SiP layer 252 formed over the source/drain features 214 is used to reduce the source/drain features 214 and subsequent sources formed over the source/drain features 214 The contact resistance at the interface between the /drain contacts 294 (see FIG. 3 ), thereby improving the performance of the FinFET formed in the workpiece 200 .

In many embodiments, _SiP layer 252 is formed to a thickness tSiP of about 0.5 nanometers to about 1.5 nanometers. As discussed below, since subsequent process steps may remove a portion of SiP layer 252, if _tSiP is less than about 0.5 nanometers, there is not enough SiP to remain in workpiece 200 to achieve a reduction in contact resistance. However, if _tSiP is greater than about 1.5 nanometers, portions of the layer of semiconductor material formed over the dielectric features (eg, interlayer dielectric layer 240 and gate spacer 212 ) may become too thick for subsequent etching processes removed in .

Referring to block 108 of FIG. 1A and FIG. 6A , method 100 processes workpiece 200 whereby germanium-containing layer 262 is formed on crystalline portions of SiP layer 252 in trenches 242 and 244 . The method 100 begins by applying a gas mixture 260 to the workpiece 200, comprising a germanium-containing gas, such as _GeH4 , and a chlorine (Cl)-containing gas, such as HCl, Cl2, other suitable chlorine _- containing gas, or a combination thereof. In an embodiment of the invention, the germanium-containing gas is formed on the germanium-containing layer 262 over the crystalline portion of the SiP layer 252, and the amorphous portion of the SiP layer 252 is removed by the chlorine-containing gas. Details of processing are discussed below.

In many embodiments, the germanium-containing gas deposits germanium atoms over the crystalline and amorphous portions of the SiP layer 252 , dynamically forming Si-Ge bonds throughout the top surface of the SiP layer 252 . The germanium atoms diffuse into the amorphous portion of the amorphous SiP layer 252 at a rate greater than the crystalline portion of the SiP layer 252 and form an amorphous germanium-containing SiP layer. In contrast, germanium atoms diffuse limitedly into the crystalline portion of SiP layer 252 and form a germanium-containing layer 262 thereon (ie, a pure germanium residual layer with a germanium concentration of about 100%). Because the energy of Ge-Si bonds is less than that of covalent Si-Si bonds, the etch selectivity of the chlorine-containing gas to the SiP layer containing amorphous germanium is enhanced relative to other components of the workpiece 200 . In other words, the amorphous portion of the SiP layer 252 is etched at a greater rate than the crystalline portion of the SiP layer 252 that is not etched or is only minimally etched. As a result, the germanium-containing layer 262 remains over the crystalline portion of the SiP layer 252 . In some embodiments, the germanium-containing layer 262 has a thickness of about 0.5 nanometers to about 2 nanometers when formed using the methods provided herein. In some embodiments, the chlorine-containing gas is omitted from the gaseous mixture 260 and only the germanium-containing gas is used to process the workpiece 200 . As such, the amorphous portion of SiP layer 252 formed over the dielectric features may be removed in a subsequent etch process.

The partial pressure ratio of the chlorine-containing gas to the germanium-containing gas can be adjusted to control the removal of the amorphous portion of the SiP layer 252 and the formation of the germanium-containing layer 262 . If the ratio is too small, that is, if the partial pressure of the germanium-containing gas is significantly greater than the partial pressure of the chlorine-containing gas, excessive accumulation of the germanium-containing layer 262 may occur on the crystalline portion of the SiP layer 252, making it difficult for subsequent removed during the manufacturing step. On the other hand, if the ratio is too large, that is, if the partial pressure of the chlorine-containing gas is significantly greater than that of the germanium-containing gas, the etching rate of the amorphous portion of the SiP layer 252 will be significantly reduced. In an exemplary embodiment, the above ratio is from about 22 to about 100.

In device region 210B, germanium atoms diffuse from the top and bottom to the SiP layer because a concentration gradient of germanium exists between the germanium-containing layer 262 and the SiP layer 252 and between the source/drain features 216 and the SiP layer 252 252 , thereby converting the SiP layer 252 into a SiPGe layer 254 . Similarly, the concentration gradient of germanium between germanium-containing layer 262 and SiP layer 252 drives the germanium atoms to diffuse to a lesser extent into SiP layer 252 in device region 210A. Therefore, the germanium concentration in SiPGe layer 254 is greater than the germanium concentration in SiP layer 252 . In some embodiments, the thickness of SiPGe layer 254 is less than the thickness of germanium-containing layer 262 . For example, the ratio of the thicknesses of the SiPGe layer 254 to the germanium-containing layer 262 is about 0.5 to about 1.0, but the embodiment of the present invention is not limited thereto. 6B shows an exemplary embodiment of germanium diffusing from germanium-containing layer 262 and source/drain features 216 to SiPGe layer 254, with arrows indicating the direction of germanium diffusion. Notably, once diffusion equilibrium is reached between the three layers, the amount of germanium in SiPGe layer 254 is at least 10% (wt %) to allow for desired etch selectivity in subsequent fabrication steps.

In an exemplary embodiment, referring to FIG. 6C , an exemplary concentration profile 304 of germanium in SiPGe layer 254 varies throughout the thickness of device region 210B. In the example shown, germanium-containing layer 262 contains about 100% germanium, and source/drain features 216 contain about 50% germanium; of course, the present disclosure is not limited to these compositions as long as the germanium in germanium-containing layer 262 is The content is greater than the germanium content in the source/drain features 216 . The germanium profile 302 from germanium diffusing from the germanium-containing layer 262 to the SiPGe layer 254 and from germanium diffusing from the source/drain features 216 to the SiPGe layer 254 form the concentration profile 306 of the SiPGe layer 254 . Specifically, the top portion of SiPGe layer 254 contains the highest germanium content due to its proximity to germanium-containing layer 262 . The bottom portion of SiPGe layer 254 contains less germanium than the top portion of SiPGe layer 254 due to the diffusion of germanium from source/drain features 216 , but more than the middle portion of SiPGe layer 254 . Referring to Figure 6D, an exemplary concentration profile 308 of germanium in SiP layer 252 in device region 210A is shown. Notably, while the top of SiP layer 252 contains a limited amount of germanium due to germanium diffusing from germanium-containing layer 262 , the concentration at the bottom of SiP layer 252 near source/drain features 214 is depleted. In fact, the SiP layer 252 includes a Ge-free or substantially germanium-free region 256 (hereinafter referred to as the SiP layer 256) having a germanium content of less than about 10%. As will be discussed in detail below, since the selective etch process uses one or more chlorine-containing gases, only regions with germanium content greater than about 10% are removed.

Referring to block 110 of FIG. 1B and FIG. 7A , method 100 etches germanium-containing layer 262 from device regions 210A and 210B and a portion of SiPGe layer 254 in device region 210B and SiP layer 252 in device region 210A. The method 100 implements a dry etch process that utilizes a chlorine-containing gas 270 , similar to the gaseous mixture 260 containing the chlorine-containing gas implemented at block 108 , to remove the germanium-containing layer 262 and the SiPGe layer 254 . In some examples, the chlorine-containing gas 270 may be HCl, Cl2, other chlorine _- containing gases, or a combination of the foregoing. In many embodiments, chlorine-containing gas 270 selectively etches germanium at a rate higher than other components present in workpiece 200 . In other words, a layer of material containing germanium is etched at a higher rate than a layer of material containing no germanium, and a layer containing a higher amount of germanium is etched at a higher rate than a layer of material containing less germanium. In the illustrated embodiment, while SiP layer 252 in device region 210A includes a small amount of Ge diffused from germanium-containing layer 262 (refer to concentration profile 308 in FIG. 6D ), SiPGe layer 254 includes a comparatively larger amount Germanium (at least 10% as described above) is thus etched at a higher rate than SiP layer 252 .

7B , which is an enlarged view of a portion of the workpiece 200 of FIG. 7A , the dry etch process of block 110 may completely remove the germanium-containing layer 262 and the SiPGe layer 254 from the device region 210B, and partially from the device Region 210A removes SiP layer 252 to form SiP layer 256 . In some examples, block 110 of method 100 may remove up to about 75% of tSiP of _SiP layer 252 such that _SiP layer 256 has a thickness _t'SiP of at least about 25% of tSiP. However, embodiments of the present invention contemplate embodiments in which smaller thicknesses may be removed by a dry etch process. Thus, the dry etch process of block 110 exposes the top surfaces of source/drain features 216 in trenches 244 with SiP layer 256 disposed over source/drain features 214 . For some embodiments, where an additional layer of SiGe or pure germanium is formed over source/drain features 216 prior to block 106 of method 100, the etch process of block 110 may remove the additional layer of SiGe or A portion of the pure germanium layer to prevent depletion of source/drain features 216 . Thus, a thin layer (eg, less than about 10 nanometers) of the SiGe or pure germanium layer may remain over the source/drain features 216 after the etch process of block 110 .

Referring now to FIGS. 1B and 8 , if the desired thickness T _SiP of the plurality of SiP layers 256 has not been reached, the method 100 may repeat the process cycle of blocks 106 , 108 and 110 to form multiple layers that overlap each other in the device region 210A SiP layer 256 . However, if the desired thickness T _SiP has been reached, the method proceeds to block 112 . Depending on the desired design requirements, the desired thickness _TSiP may be about 4 nanometers and about 6 nanometers. Because the deposition of each SiP layer 252 is carried out at elevated temperatures (from about 300 degrees Celsius to about 500 degrees Celsius), the number of cycles (corresponding to the size of T _SiP ) may be limited by inclusion in the metal gate structures 220A and 220B The thermal budget (ie tolerance) limit of the various material layers in the . Accordingly, method 100 is configured to maximize the amount of T _SiP within the scope discussed herein without compromising the integrity of metal gate structures 220A and 220B. For example, if the desired thickness _TSiP exceeds about 6 nanometers, repeating the process cycles at blocks 106, 108, and 110 may undesirably damage the structure and performance of nearby device components (eg, metal gate structures). On the other hand, if the desired thickness _TSiP is less than about 4 nanometers, the SiP layer 252 provided is insufficient to reduce the contact resistance between the source/drain features 214 and subsequently formed source/drain contacts. Notably, as depicted and discussed with reference to FIGS. 6 and 7 , due to repeated removal of germanium-containing layer 262 and SiPGe layer 254 from trench 244 , the SiP layer does not remain on source/drain features 216 .

Referring now to block 112 of FIG. 1B and to FIG. 9 , method 100 forms a silicide layer 282 over SiP layer 256 in trench 242 and over source/drain features 216 in trench 244 . In the illustrated embodiment, silicide layer 282 is disposed over SiP layer 256 and source/drain features 216 . The suicide layer 282 may comprise nickel suicide, cobalt suicide, tungsten suicide, tantalum suicide, titanium suicide, platinum suicide, erbium suicide, palladium suicide, other suitable suicides, or a combination of the foregoing. The silicide layer 282 may be formed through a series of processes. First, metal layer 280 may be deposited over SiP layer 256 and source/drain features 216 by a deposition process such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, other suitable processes, or combinations of the foregoing. The metal layer may comprise nickel, cobalt, tungsten, tantalum, titanium, platinum, erbium, palladium, other suitable metals, or combinations of the foregoing. The workpiece 200 is then annealed to allow the metal layer and the semiconductor material of the SiP layer 256 and source/drain features 216 to react. Then, the unreacted metal layer is removed, leaving silicide layer 282 over SiP layer 256 and source/drain features 216 .

Referring to block 114 of FIG. 1 and FIG. 10 , method 100 deposits conductive material 292 in trenches 242 and 244 such that conductive material 292 contacts interlayer dielectric layer 240 , gate spacer 212 and silicide layer 282 . Conductive material 292 may comprise any suitable material, such as copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), aluminum (Al), other suitable conductive materials, or combinations of the foregoing. Then, referring to FIG. 11, which shows an exemplary embodiment of workpiece 200, method 100 performs one or more chemical mechanical planarization processes to remove excess conductive material 292 and to form source/s in device regions 210A and 210B. Drain contact 294 . Notably, the bottom surfaces of source/drain contacts 294 in device region 210B are lower than the bottom surfaces of source/drain contacts 294 in device region 210A.

Referring to block 116 , the method 100 performs additional process steps on the workpiece 200 . For example, method 100 may proceed by forming interconnect structures to couple various devices to the integrated circuit. The interconnect structure includes metal lines in multiple metal layers for horizontal coupling and vias/contacts for vertical coupling (eg, connecting the metal gate structures 220A and 220B to the source/drain of the bottom metal layer) contacts), vias/contacts are used between the bottom metal layer and device components formed on substrate 202, between the bottom metal layer and source/drain contacts 294, or between adjacent metal layers. The interconnect structure includes one or more suitable conductive materials, such as copper (Cu), cobalt (Co), ruthenium (Ru), aluminum (Al), tungsten (W), or other suitable conductive materials. The interconnect structure can be formed by a damascene process, such as a single damascene process or a dual damascene process, which includes lithographic patterning, etch deposition, and chemical mechanical planarization. For example, the conductive material may be deposited using a suitable process, such as chemical vapor deposition, physical vapor deposition, electroplating, and/or other suitable processes. The illustrated workpiece 200 is merely an example of some embodiments of the method 100 . Method 100 may encompass various other embodiments without departing from the scope of embodiments of the present invention.

Furthermore, workpiece 200 as shown above may be or be part of an intermediate device fabricated during integrated circuit fabrication, which may include static random access memory (SRAM) and/or logic circuits, passive components , such as resistors, capacitors and inductors, and active components such as p-type field effect transistors, n-type field effect transistors, multi-gate field effect transistors, such as fin field effect transistors, metal oxide semiconductors Metal-oxide semiconductor field effect transistors (MOSFET), complementary metal-oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, other memory devices units and combinations of the foregoing.

Embodiments of the present invention provide a semiconductor structure and a method for fabricating the same. Embodiments of the present invention include selectively forming an n-type epitaxial semiconductor layer comprising silicon and phosphorous (SiP) over the n-type FET source/drain features, rather than over the p-FET source/drain features . Compared to source/drain features formed at higher process temperatures, the n-type epitaxial semiconductor layers of embodiments of the present invention may be formed at lower process temperatures, thereby reducing the resistivity of SiP. Embodiments of the invention provide various advantages, but not all embodiments require a particular advantage. In at least some embodiments, by selectively forming n-type epitaxial semiconductor layers using the methods of embodiments of the present invention, thermal damage, process complexity, and production costs incurred during device production processes can be reduced, and device performance can be improved.

In one aspect, embodiments of the present invention provide a method comprising: providing a p-type source/drain epitaxial feature and an n-type source/drain epitaxial feature, where the n-type source/drain epitaxial feature and the p-type source/drain epitaxial feature are provided. Forming a layer of semiconductor material over the source/drain epitaxial component, treating the layer of semiconductor material with a germanium-containing gas, wherein the treatment of the layer of semiconductor material forms a layer of germanium over the layer of semiconductor material, etching the layer of germanium, wherein etching of the germanium-containing layer removing the germanium-containing layer formed over the n-type source/drain epitaxial features and the semiconductor material layer formed over the p-type source/drain epitaxial features, and the remaining layers over the n-type source/drain epitaxial features A first source/drain contact is formed over the layer of semiconductor material, and a second source/drain contact is formed over the p-type source/drain epitaxial feature. In some embodiments, the n-type source/drain epitaxial features are formed at a first temperature, and the semiconductor material layer is formed at a second temperature, wherein the second temperature is lower than the first temperature. In some embodiments, the method further includes, prior to forming the first and second source/drain contacts, over the layer of semiconductor material remaining over the n-type source/drain epitaxial features and over the p-type source A silicide layer is formed over the /drain epitaxial features, respectively.

In some embodiments, the composition of the semiconductor material layer is similar to the composition of the n-type source/drain epitaxial features. In some embodiments, the composition of the semiconductor material layer is the same as the composition of the n-type source/drain epitaxial features. In some embodiments, the layer of semiconductor material includes silicon and phosphorous. In further embodiments, the resistivity of the layer of semiconductor material is lower than the resistivity of the n-type source/drain epitaxial features.

In some embodiments, after the germanium-containing layer is formed, the concentration of germanium in the layer of semiconductor material formed over the p-type source/drain epitaxial features is greater than that of the layer of semiconductor material formed over the n-type source/drain epitaxial features Germanium concentration in .

In some embodiments, the processing of the layer of semiconductor material includes performing an etching process. In a further embodiment, the etching process is performed with a chlorine-containing gas.

In another aspect, embodiments of the present invention provide a method including forming a first trench and a second trench in an interlayer dielectric layer to respectively expose a first source formed over a first fin /Drain epitaxial feature and forming a second source/drain epitaxial feature over the second fin, depositing an n-type semiconductor layer in the first trench and the second trench, forming a germanium-containing layer over the n-type semiconductor layer , removing the germanium-containing layer from the first trench, wherein the removal step removes the n-type semiconductor layer from the second trench, over the n-type semiconductor layer in the first trench and in the second trench A silicide layer is formed over the second source/drain epitaxial features in the first and second trenches, and source/drain contacts are formed over the silicide layers in the first and second trenches, respectively. In some embodiments, the first source/drain epitaxial feature is n-type and the second source/drain epitaxial feature is p-type.

In some embodiments, after the germanium-containing layer is formed, the n-type semiconductor layer in the second trench includes germanium.

In some embodiments, wherein the germanium-containing layer is a first germanium-containing layer and the second source/drain epitaxial feature includes a silicon germanium semiconductor layer, the method further includes, prior to depositing the n-type semiconductor layer, in the second source/drain A second germanium-containing layer is deposited over the drain epitaxial feature such that the germanium concentration in the second germanium-containing layer is higher than the germanium concentration in the second source/drain epitaxial feature. In further embodiments, the first germanium-containing layer comprises silicon germanium, and the second germanium-containing layer comprises silicon germanium, pure germanium, or a combination thereof.

In some embodiments, wherein the n-type semiconductor layer is the n-type first semiconductor layer and the germanium-containing layer is the first germanium-containing layer, the method further includes, prior to forming the silicide layer, a first trench in the first trench depositing a second n-type semiconductor layer over the semiconductor layer and over the second source/drain epitaxial feature in the second trench, forming a second germanium-containing layer over the second n-type semiconductor layer, and from the first trench and the second trench to remove the second germanium-containing layer, wherein the removing step removes the second n-type semiconductor layer from the second trench.

In some embodiments, wherein the semiconductor layer comprises silicon phosphorus (SiP), the deposition of the n-type semiconductor layer forms an amorphous SiP layer over the interlayer dielectric layer. In a further embodiment, the formation of the germanium-containing layer removes the amorphous SiP layer from the interlayer dielectric layer.

In yet another aspect, embodiments of the present invention provide a semiconductor structure including a first source/drain epitaxial feature of a first conductivity type disposed in a semiconductor layer, wherein the first source/drain epitaxial feature has A first resistivity, a second source/drain epitaxial feature of a second conductivity type is disposed in the semiconductor layer, the second conductivity type is different from the first conductivity type, wherein the first source/drain and the second source/drain Drain epitaxial features are disposed adjacent to their respective metal gate structures, at least one layer of epitaxial semiconductor material is disposed over the first source/drain epitaxial features, and first source/drain contacts and second source/drain contacts Drain contacts are disposed over the epitaxial semiconductor material layer and over the second source/drain epitaxial features, respectively. In some embodiments, the layer of epitaxial semiconductor material has a second resistivity lower than the first resistivity. In some embodiments, the bottom surface of the second source/drain contact is lower than the bottom surface of the first source/drain contact. In some embodiments, the first conductivity type is n-type and the second conductivity type is p-type.

In some embodiments, the n-type source/drain epitaxial features and epitaxial semiconductor material layers comprise silicon and phosphorous. In further embodiments, the phosphorus concentration in the n-type source/drain epitaxial features is similar to the phosphorus concentration in the at least one epitaxial semiconductor material layer.

In some embodiments, the p-type source/drain epitaxial feature includes silicon germanium, and the semiconductor structure further includes a germanium-containing layer disposed over the p-type source/drain epitaxial feature, wherein the germanium-containing layer has a germanium concentration Greater than the germanium concentration in the p-type source/drain epitaxial features.

In some embodiments, the semiconductor structure further includes a p-type source/drain epitaxial feature and a second source/drain disposed between the at least one layer of epitaxial semiconductor material and the first source/drain contact silicide layer between pole contacts.

The components of several embodiments are outlined above so that those skilled in the art to which the present disclosure pertains may better understand aspects of the embodiments of the present invention. Those skilled in the art to which this disclosure pertains should appreciate that they can, based on the embodiments of the present invention, design or modify other processes and structures to achieve the same objectives and/or advantages of the embodiments described herein. Those skilled in the art to which the present disclosure pertains should also appreciate that such equivalent structures do not depart from the spirit and scope of the present disclosure, and they can make various modifications without departing from the spirit and scope of the present disclosure. Alteration, substitution and substitution.

Claims (1)

1. A method of manufacturing a semiconductor structure, comprising: providing a p-type source/drain epitaxial feature and an n-type source/drain epitaxial feature formed at a first temperature; forming a layer of semiconductor material over the n-type source/drain epitaxial feature and the p-type source/drain epitaxial feature at a second temperature, wherein the composition of the semiconductor material layer is similar to the n-type source/drain the composition of an extremely epitaxial component, and wherein the second temperature is less than the first temperature; treating the semiconductor material layer with a germanium-containing gas, wherein the treatment of the semiconductor material layer forms a germanium-containing layer over the semiconductor material layer; Etching the germanium-containing layer, wherein the etching of the germanium-containing layer removes the germanium-containing layer formed over the n-type source/drain epitaxial feature and the semiconductor formed over the p-type source/drain epitaxial feature material layers; and A first source/drain contact is formed over the layer of semiconductor material remaining over the n-type source/drain epitaxial feature and a second source/drain contact is formed over the p-type source/drain epitaxial feature drain contact.

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