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CN110648995B - 三维集成电路结构 - Google Patents

三维集成电路结构 Download PDF

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Publication number
CN110648995B
CN110648995B CN201811093086.1A CN201811093086A CN110648995B CN 110648995 B CN110648995 B CN 110648995B CN 201811093086 A CN201811093086 A CN 201811093086A CN 110648995 B CN110648995 B CN 110648995B
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Prior art keywords
die
circuit structure
layer
top surface
integrated circuit
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CN201811093086.1A
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CN110648995A (zh
Inventor
陈宪伟
杨庆荣
陈明发
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种三维集成电路结构，包括管芯堆叠结构、金属电路结构及保护结构。管芯堆叠结构包括面对面接合在一起的第一管芯与第二管芯。金属电路结构设置在第二管芯的后侧之上。保护结构设置在第二管芯的后侧内且分隔第二管芯的多个衬底穿孔中的一者与金属电路结构。

Description

三维集成电路结构
技术领域
本发明实施例涉及一种三维集成电路结构。
背景技术
近年来，由于各种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度持续提高，半导体行业已经历了快速成长。集成密度的此种改进来自于最小特征尺寸(minimum feature size)的一再减小，以允许更多的较小的组件能够集成在一定的面积中。
与先前的封装体相比，这些较小的电子组件也需要利用较小面积的较小的封装体。半导体封装体的示例性类型包括四面扁平封装(quad flat package，QFP)、针栅数组(pin grid array，PGA)、球栅数组(ball grid array，BGA)、倒装芯片(flip chip，FC)、三维集成电路(three dimensional integrated circuit，3DIC)、晶圆级封装体(waferlevel package，WLP)及叠层封装体(package on package，PoP)装置。一些三维集成电路是通过将芯片(chip)放置在半导体晶圆级上的芯片上方制备而成。由于堆叠芯片之间的内连线的长度减小，因此三维集成电路提供更高的集成密度及其他优点，例如更快的速度及更高的带宽。然而，对于三维集成电路技术来说仍存在很多待处理的挑战。
发明内容
本发明实施例提供一种三维集成电路结构，包括管芯堆叠结构、金属电路结构及保护结构。管芯堆叠结构包括面对面接合在一起的第一管芯与第二管芯。金属电路结构设置在第二管芯的后侧之上。保护结构设置在第二管芯的后侧内且分隔第二管芯的多个衬底穿孔中的一者与金属电路结构。
附图说明
结合附图阅读以下详细说明，会最好地理解本发明的各个方面。应注意，根据本行业中的标准惯例，各种特征并非按比例绘制。事实上，为论述清晰起见，可任意增大或减小各种特征的尺寸。
图1A到图1E是根据第一实施例的形成三维集成电路(3DIC)结构的方法的剖视图。
图2是根据第二实施例的三维集成电路结构的剖视图。
图3是根据第三实施例的三维集成电路结构的剖视图。
图4是根据一些实施例的封装体的剖视图。
具体实施方式
以下揭露内容提供用于实施所提供的目标的不同特征的许多不同实施例或实例。以下所描述的构件及配置的具体实例是为了以简化的方式传达本揭露为目的。当然，这些仅仅为实例而非用以限制。举例来说，在以下描述中，在第二特征上方或在第二特征上形成第一特征可包括第一特征与第二特征形成为直接接触的实施例，且也可包括第一特征与第二特征之间可形成有额外特征，使得第一特征与第二特征可不直接接触的实施例。此外，本揭露在各种实例中可重复使用参考编号及/或字母。参考编号的重复使用是为了简单及清楚起见，且并不表示所欲讨论的各个实施例及/或配置本身之间的关系。
此外，为易于说明，本文中可能使用例如“在...下方(beneath)”、“在...下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空间相对术语来阐述图中所示的一个元件或特征与另一(些)元件或特征的关系。所述空间相对术语意欲涵盖组件在使用或操作时的不同定向。设备可被另外定向(旋转90度或在其他定向)，而本文所用的空间相对术语相应地作出解释。
还可包括其他特征及工艺。举例来说，可包括测试结构以帮助进行三维(3D)封装体或三维集成电路装置的验证测试。测试结构可包括例如形成于重布线层中或衬底上的测试垫，所述测试垫使得能够测试3D封装体或3DIC、使用探针(probe)及/或探针卡(probecard)等。可对中间结构及最终结构执行验证测试。另外，本文中所公开的结构及方法可接合包括对已知良好管芯(known good dies)的中间验证的测试方法一起使用，以提高良率(yield)及降低成本。
图1A到图1E是根据第一实施例的形成三维集成电路结构的方法的剖视图。
参照图1A，形成管芯堆叠结构10。具体来说，管芯堆叠结构10包括第一管芯100、第二管芯200及混合接合结构250。第一管芯100与第二管芯200通过混合接合结构250混合接合在一起。管芯堆叠结构10根据例如以下步骤形成。
如图1A所示，提供包括第一半导体衬底102、第一装置层103、第一内连结构104及第一钝化层110的第一管芯100。
在一些实施例中，半导体衬底102可包括硅或其他半导体材料。另外或额外的，第一半导体衬底102可包括其他元素半导体材料，例如锗。在一些实施例中，第一半导体衬底102是由例如碳化硅、砷化镓、砷化铟及磷化铟等化合物半导体制成。在一些实施例中，第一半导体衬底102是由例如硅锗、碳化硅锗、磷化镓砷或磷化镓铟等合金半导体制成。在一些实施例中，第一半导体衬底102包括外延层。举例来说，第一半导体衬底102具有上覆在块状半导体上的外延层。
在一些实施例中，第一装置层103是在前段(front-end-of-line，FEOL)工艺中形成在第一半导体衬底102之上。第一装置层103包括各种各样的装置。在一些实施例中，所述装置包括有源组件、无源组件或它们的组合。在一些实施例中，所述装置可包括集成电路装置。所述装置是例如晶体管、电容器、电阻器、二极管、光电二极管、熔丝装置或其他类似装置。在一些实施例中，第一装置层103包括栅极结构、源极区及漏极区、以及隔离结构，例如浅沟槽隔离(shallow trench isolation，STI)结构(图中未示出)。在第一装置层103中，可形成且内连各种N型金属氧化物半导体(NMOS)和/或P型金属氧化物半导体(PMOS)装置(例如晶体管或存储器等)来执行一个或多个功能。也可在第一半导体衬底102之上形成其他装置，例如电容器、电阻器、二极管、光电二极管、熔丝等。所述装置的功能可包括存储器、处理器、传感器、放大器、功率分配、输入/输出电路等。
参照图1A，第一内连结构104形成在第一装置层103之上。详细来说，第一内连结构104包括第一绝缘材料106及多个第一金属特征108。第一金属特征108形成在第一绝缘材料106中且电连接到第一装置层103。第一金属特征108的一部分(例如顶部金属特征108a及108b)被第一绝缘材料106暴露出。在一些实施例中，第一绝缘材料106包括位于第一装置层103上的层间介电(inner-layer dielectric，ILD)层以及位于层间介电层之上的至少一个金属间介电(inter-metal dielectric，IMD)层。在一些实施例中，第一绝缘材料106包括氧化硅、氮氧化硅、氮化硅、低介电常数(低k)材料或它们的组合。在一些替代实施例中，第一绝缘材料106可以是单层或多层。在一些实施例中，第一金属特征108包括插塞及金属线。所述插塞可包括形成在层间介电层中的接触窗(contacts)以及形成在金属间介电层中的通孔(vias)。所述接触窗形成在第一装置层103与底部金属线之间且与第一装置层103及底部金属线连接。所述通孔形成在两条金属线之间且与所述两条金属线连接。第一金属特征108可由钨(W)、铜(Cu)、铜合金、铝(Al)、铝合金或它们的组合制成。在一些替代实施例中，可在第一金属特征108与第一绝缘材料106之间形成障壁层(图中未示出)，以防止第一金属特征108的材料迁移或扩散到第一装置层103。障壁层的材料包括例如钽、氮化钽、钛、氮化钛、钴-钨(CoW)或它们的组合。
参照图1A，第一钝化层110形成在第一内连结构104之上。第一钝化层110覆盖第一绝缘材料106和顶部金属特征108a及108b的一些部分。在一些实施例中，第一钝化层110包括氧化硅、氮化硅、苯并环丁烯(benzocyclobutene，BCB)聚合物、聚酰亚胺(polyimide，PI)、聚苯并恶唑(polybenzoxazole，PBO)或它们的组合，且通过诸如旋涂、化学气相沉积等合适的工艺形成。将第一钝化层110形成在第一内连结构104之上之后，第一管芯100便已完成。如图1A所示，第一管芯100具有彼此相对的前侧100a与后侧100b。本文中，第一管芯100的前侧100a面朝上，而第一管芯100的后侧100b面朝下。在一些实施例中，第一管芯100的前侧100a被称为有源表面。
参照图1A，在第一管芯100的前侧100a之上形成第一接合结构114。详细来说，第一接合结构114包括第一接合介电层116和多个第一接合金属层118及120。在一些实施例中，第一接合金属层118及120形成在第一接合介电层116中。第一接合金属层118包括通孔插塞118a及设置在通孔插塞118a之上的金属特征118b，而第一接合金属层120包括通孔插塞120a及设置在通孔插塞120a之上的金属特征120b。如图1A所示，通孔插塞118a贯穿第一钝化层110且与第一金属特征108a连接，而通孔插塞120a贯穿第一钝化层110且与第一金属特征108b连接。
在一些实施例中，第一接合金属层118及120可包括铜、铜合金、镍、铝、钨、它们的组合。在一些实施例中，第一接合金属层118及120可使用相同的材料且同时形成。在一些其他实施例中，第一接合金属层118及120可使用不同的材料且依次形成。第一接合金属层118及120可通过下述方式形成：在第一接合介电层116中的沟槽及通孔开口(图中未示出)中沉积导电材料，然后通过平坦化工艺(例如化学机械抛光工艺)移除第一接合介电层116的顶表面之上的导电材料。在平坦化工艺之后，第一接合介电层116的顶表面与第一接合金属层118及120的顶表面实质上共面。
参照图1A，第二管芯200与第二管芯100类似。即，第二管芯200包括第二半导体衬底202、第二装置层203、第二内连结构204、第二绝缘材料206及第二钝化层210。第二管芯200的配置、材料及形成方法与第一管芯100的配置、材料及形成方法类似。因此，这里省略其细节。在一些实施例中，第二管芯200的尺寸小于第一管芯的100的尺寸。本文中，用语“尺寸(size)”是指长度、宽度或面积。举例来说，如图1A所示，第二管芯200的长度小于第一管芯100的长度。
在一些实施例中，第一管芯100及第二管芯200中的一者可以是例如应用专用集成电路(application-specific integrated circuit，ASIC)芯片、模拟芯片、传感器芯片、无线及射频芯片、调压器芯片或存储器芯片。在一些替代实施例中，第一管芯100及第二管芯200可包括相同的功能或不同的功能。图1A所示的管芯堆叠结构10是晶片上芯片(chip-on-wafer，CoW)结构。举例来说，第二管芯200可以是管芯(die)，第一管芯100可以是晶片(wafer)，且管芯200设置在晶片100之上。然而，本发明的实施例并不仅限于此。在其他实施例中，管芯堆叠结构10包括芯片上芯片结构(chip-on-chip structure)、管芯上管芯结构(die-on-die structure)或它们的组合。
参照图1A，在第二管芯200的前侧200a之上形成第二接合结构214。详细来说，第二接合结构214包括第二接合介电层216及第二接合金属层218。在一些实施例中，第二接合金属层218形成在第二接合介电层216中。第二接合金属层218包括通孔插塞218a及金属特征218b。如图1A所示，通孔插塞218a贯穿第二钝化层210且与第二内连结构204的第二金属特征208连接。金属特征218b通过通孔插塞218a电连接到第二金属特征208。
在一些实施例中，第二接合金属层218可包括铜、铜合金、镍、铝、钨、它们的组合。第二接合金属层218可通过下述方式形成：在第二接合介电层216中的沟槽及通孔开口(图中未示出)中沉积导电材料，然后通过平坦化工艺(例如化学机械抛光工艺)移除第二接合介电层216的顶表面之上的导电材料。在平坦化工艺之后，第二接合介电层216的顶表面与第二接合金属层218的顶表面实质上共面。
参照图1A，将第二管芯200进一步上下颠倒且安装到第一管芯100上。详细来说，第一管芯100与第二管芯200通过第一接合结构114及第二接合结构214面对面(face-to-face)接合在一起。在一些实施例中，在将第二管芯200接合到第一管芯100之前，将第一接合结构114与第二接合结构214对齐，以使第二接合金属层218可接合到第一接合金属层118，且第一接合介电层116可接合到第二接合介电层216。在一些实施例中，第一接合结构114与第二接合结构214的对齐可通过使用光学感测方法来实现。在实现对齐之后，第一接合结构114与第二接合结构214通过混合接合法(hybrid bonding)接合在一起，以形成混合接合结构250。
第一接合结构114与第二接合结构214通过施加压力及热而混合接合在一起。应注意，混合接合法涉及至少两种类型的接合法，包括金属对金属接合法及非金属对非金属接合法(例如介电质对介电质接合法或熔融接合法)。如图1A所示，混合接合结构250包括通过金属对金属接合法接合在一起的第一接合金属层118与第二接合金属层218和通过非金属对非金属接合法接合在一起的第一接合介电层116与第二接合介电层216。然而，本发明的实施例并不仅限于此。在其他实施例中，第一接合结构114与第二接合结构214可通过其他接合法(例如熔融接合法(fusion bonding))接合在一起。
另外，如图1A所示，第二管芯200还包括多个衬底穿孔(through-substrate vias，TSV)205。在一些实施例中，衬底穿孔205形成在第二半导体衬底202中以电连接到第二内连结构204。在一些实施例中，衬底穿孔205中的一者包括导电通孔及环绕导电通孔的侧壁及底表面的衬层(图中未示出)。导电通孔可包括铜、铜合金、铝、铝合金、Ta、TaN、Ti、TiN、CoW或它们的组合。衬层可包括介电材料，例如氧化硅。在一些实施例中，衬底穿孔205在开始时不会穿透过第二半导体衬底202，且衬底穿孔205的底表面仍然被第二半导体衬底202覆盖。在后续的工艺中，对第二半导体衬底202的后表面202b执行薄化工艺，以暴露出衬底穿孔205的顶表面205s，且衬底穿孔205可连接到其他组件。在一些实施例中，薄化工艺可包括研磨工艺或化学机械抛光(CMP)工艺。
在执行薄化工艺之后，第二半导体衬底202的后表面202b低于衬底穿孔205的顶表面205s，以确保衬底穿孔205能够连接到待形成的金属电路结构400(如图1E所示)。在暴露出衬底穿孔205的顶表面205s之后，在第二管芯200之上形成氮化物层220(例如，氮化硅层)。氮化物层220共形地覆盖被第二半导体衬底202暴露出的衬底穿孔205的表面、第二半导体衬底202的后表面202b、第二管芯200的侧壁及未接合到第二接合结构214的第一接合结构114的顶表面。氧化物层222(例如，氧化硅层)共形地形成在氮化物层220之上。氮化物层224(例如，氮化硅层)共形地形成在氧化物层222之上。介电层226(例如，间隙填充介电层(gap-fill dielectric layer))形成在第一管芯100之上且包封第二管芯200。即，介电层226覆盖第二管芯200的侧壁及第二半导体衬底202的底表面202a。在一些实施例中，介电层226可包括氧化物(例如氧化硅)、氮化物(例如氮化硅)、氮氧化物(例如氮氧化硅)、模塑化合物、模塑底部填充胶(molding underfill)、树脂(例如环氧树脂)、它们的组合等。
然后执行平坦化工艺(或称为第一平坦化工艺)。在一些实施例中，平坦化工艺是化学机械抛光工艺。在执行平坦工艺之后，移除过量的介电层226、过量的氮化物层224、过量的氧化物层222及过量的氮化物层220，以暴露出衬底穿孔205的顶表面205s及剩余氧化物层222的顶表面222t，如图1A所示。剩余氧化物层222在侧向上包封衬底穿孔205的一部分。剩余介电层226则在侧向上包封第二管芯200，以分隔第二管芯200与接合在第一管芯100之上的另一管芯(图中未示出)。在执行平坦化工艺之后，完成管芯堆叠结构10。在这种情况下，剩余氧化物层222的顶表面222t可称为第二管芯200的后侧200b。在执行平坦化工艺之后，第二管芯200的后侧200b、衬底穿孔205的顶表面205s及剩余介电层226的顶表面226t处于实质上相同的水平高度。本文中，当元件被阐述为“处于实质上相同的水平高度(at substantially the same level)”时，这些元件是在相同的层中形成实质上相同的高度，或者嵌置在相同的层中的相同的位置。在一些实施例中，处于实质上相同的水平高度的元件是使用相同的工艺步骤且由相同的材料形成。在一些实施例中，处于实质上相同的水平高度的元件的顶部实质上共面。举例来说，如图1A所示，第二管芯200的后侧200b、衬底穿孔205的顶表面205s以及剩余介电层226的顶表面226t实质上共面。
应注意，在执行平坦化工艺(或称为第一平坦化工艺)或薄化工艺之后，在第二管芯200的后侧200b中形成凹槽R1。凹槽R1可以是各种缺陷，例如裂缝(cracks)、尖锐形态(sharp morphology)、隆起(bulge)等。形成凹槽R1是因为一些不期望的颗粒可能会落在待研磨表面上，然后执行平坦化工艺或薄化工艺会损坏第二管芯200的后侧200b。如图1A所示，凹槽R1沿着从第二管芯200的后侧200b朝混合接合结构250的方向D1延伸。凹槽R1使第二管芯200的衬底穿孔205b凹陷，以使得衬底穿孔205b的顶表面205s’低于衬底穿孔205a的顶表面205s。另外，衬底穿孔205b的顶表面205s’具有不平坦表面或尖锐形态。相比之下，没有受到缺陷的损坏的衬底穿孔205a的顶表面205s具有光滑的表面或平整的表面。
参照图1B，在执行平坦化工艺之后，在管芯堆叠结构10之上形成共形层305。共形层305共形地覆盖第二管芯200的后侧200b、衬底穿孔205的顶表面205s及剩余介电层226的顶表面226t。另外，共形层305也共形地且完全地覆盖凹槽R1的表面(或衬底穿孔205b的顶表面205s’)，以防止在后续的图案化期间出现等离子体刻蚀电弧放电(plasma etchingarcing)。在一些实施例中，当检测到凹槽R1时，可形成共形层305来覆盖凹槽R1的表面。在一些替代实施例中，当凹槽R1太轻微而不能被检测到时，仍可形成共形层305来覆盖凹槽R1的表面。共形层305通过例如原子层沉积(atomic layer deposition，ALD)工艺形成。在一些实施例中，共形层305可包括氧化硅、氮化硅、氮氧化硅或它们的组合。在替代实施例中，共形层305可以是单层结构、双层结构或多层结构。在其他实施例中，共形层305的厚度为到在本文中，所谓共形层可视为具有均匀厚度的层，且所述层具有小于(举例来说 )的厚度差。
另外，在一些实施例中，在形成共形层305之前，在第二管芯200上形成氮化物层304(例如，氮化硅层)。在一些实施例中，氮化物层304通过合适的沉积工艺(例如化学气相沉积工艺或原子层沉积工艺)形成，且氮化物层304的厚度为到在替代实施例中，共形层305的厚度大于氮化物层304的厚度。在其他实施例中，氮化物层304与共形层305包括相同的材料或不同的材料。
参照图1C，执行化学气相沉积工艺以在共形层305之上形成填充层306。在一些实施例中，填充层306可包括氧化硅、氮化硅、氮氧化硅、或它们的组合。在其他实施例中，填充层306的厚度为到由于共形层305具有比填充层306更好的阶梯覆盖性(stepcoverage)，因此共形层305能够完全覆盖具有尖锐形态的凹槽R1的表面。在一些实施例中，共形层305与填充层306具有相同的材料或不同的材料。在一些替代实施例中，填充层306的厚度大于或等于共形层305的厚度。然而，本发明的实施例并不仅限于此。
在形成填充层306之后，在填充层306之上形成掩模图案307。在一些实施例中，掩模图案307包括光刻胶且通过合适的工艺(例如旋涂及光刻工艺)形成。在形成掩模图案307之后，通过使用掩模图案307作为刻蚀掩模来执行刻蚀工艺，以移除填充层306、共形层305、氮化物层304、介电层226、氮化物层224、氧化物层222及氮化物层220的一些部分，从而形成开口308。如图1C所示，开口308暴露出第一接合金属层120。在形成开口308之后，移除掩模图案307。
参照图1C及图1D，形成导电材料(图中未示出)以填充在开口308中，并使所述导电材料延伸以覆盖填充层306。执行平坦化工艺(或称为第二平坦化工艺)，以移除导电材料、填充层306、共形层305及氮化物层304的一些部分并暴露出衬底穿孔205的顶表面205s。在执行平坦化工艺之后，介电层穿孔(through dielectric via，TDV)310形成在介电层226中，且保护结构300形成在第二管芯200的后侧200b中，如图1D所示。介电层穿孔310形成在介电层226中，以电连接到第一接合金属层120及待形成的金属电路结构400(如图1E所示)。
参照图1D，在一些实施例中，保护结构300包括填充在凹槽R1中的氮化物层304、共形层305及填充层306。共形层305形成在氮化物层304与填充层306之间。图1D所示的保护结构300是三层结构，然而，本发明的实施例并不仅限于此。在其他实施例中，保护结构300可包括单层结构、双层结构或多层(即，多于三层)结构。举例来说，保护结构300可由仅共形层305制成，或仅氮化物层304与共形层305制成，或仅共形层305与填充层306制成。在执行平坦化工艺之后，保护结构300的顶表面300t、第二管芯200的后侧200b、衬底穿孔205的顶表面205s、介电层226的顶表面226t与介电层穿孔310的顶表面310t实质上共面。尽管图1D中仅示出一个介电层穿孔310，但可形成多于一个介电层穿孔310。
参照图1E，以后段(back-end-of-line，BEOL)工艺在第二管芯200的后侧200b之上形成金属电路结构400。在形成金属电路结构400之后，三维集成电路结构1便已形成。详细来说，在第二管芯200的后侧200b及介电层226的顶表面226t之上形成介电层402。通过图案化工艺及合适的沉积工艺(例如镀覆工艺)在介电层402中形成金属特征404。金属特征404电连接到未被保护结构300覆盖的介电层穿孔310及衬底穿孔205a。在一些实施例中，介电层402包括氧化硅、氮氧化硅、氮化硅、低介电常数(低k)材料或它们的组合。在一些替代实施例中，介电层402可以是单层或多层。在一些实施例中，金属特征404包括插塞及金属线。插塞形成在两条金属线之间且与所述两条金属线连接。金属特征404可由钨(W)、铜(Cu)、铜合金、铝(Al)、铝合金或它们的组合制成。
在形成金属特征404之后，形成钝化层406以覆盖介电层402并暴露出金属特征404的一部分。在一些实施例中，钝化层406包括氧化硅、氮化硅、苯并环丁烯(BCB)聚合物、聚酰亚胺(PI)、聚苯并恶唑(PBO)或它们的组合且通过合适的工艺(例如旋涂、化学气相沉积等)形成。在钝化层406之上形成接合垫408，且接合垫408延伸以覆盖金属特征404。接合垫408的材料不同于第一金属特征404的材料。在一些实施例中，接合垫408的材料比第一金属特征404的材料软。在一些实施例中，接合垫408包括金属材料，例如铝、铜、镍、金、银、钨或它们的组合。接合垫408可通过下述方式形成：通过合适的工艺(例如电化学镀覆工艺、化学气相沉积、原子层沉积(ALD)、物理气相沉积等)来沉积金属材料层，然后图案化金属材料层。
应注意，填充在凹槽R1中的保护结构300设置在第二管芯200的衬底穿孔205b与金属电路结构400的金属特征404之间，以分隔或电隔离第二管芯200的衬底穿孔205b与金属电路结构400的金属特征404。如图1E所示，保护结构300完全覆盖第二管芯200的衬底穿孔205b，因此，在金属电路结构400的图案化工艺期间，具有尖锐形态的衬底穿孔205b不会引起等离子体刻蚀电弧放电。也就是说，三维集成电路结构1的可靠性及良率相应地得到改善。另一方面，尽管衬底穿孔205b与金属电路结构400电隔离，但位于衬底穿孔205b下方的第二装置层203的信号还是能够通过其他衬底穿孔(例如，衬底穿孔205a)传送到金属电路结构400。尽管图1E中仅示出两个衬底穿孔205a及205b，但可形成多于两个衬底穿孔205a及205b。也就是说，多于一个保护结构300完全覆盖多于一个衬底穿孔205b。
图2是根据第二实施例的三维集成电路结构的剖视图。
参照图2，第二实施例的三维集成电路结构2与图1E所示第一实施例的三维集成电路结构1类似。它们之间的不同之处在于，三维集成电路结构2的保护结构300的数目是多个。保护结构300包括保护结构301及302。如图2所示，保护结构301及302形成在第二半导体衬底202之上且都沿着从第二管芯200的后侧200b朝混合接合结构250的方向D1延伸。保护结构301覆盖第二管芯200的衬底穿孔205b，而保护结构302不覆盖第二管芯200的任何衬底穿孔205(包括衬底穿孔205a及205b)。具体来说，通过平坦化工艺或薄化工艺得到的凹槽R2可形成在没有形成任何衬底穿孔205的区域中。共形层305沉积在凹槽R1及R2二者中以同时形成保护结构301及302。尽管图1E仅示出两个保护结构301及302，但可形成多于两个保护结构301及302。
图3是根据第三实施例的三维集成电路结构的剖视图。
参照图3，第三实施例的三维集成电路结构3与图1E所示第一实施例的三维集成电路结构1类似。它们之间的不同之处在于，三维集成电路结构3包括从第二管芯200的后侧200b延伸到混合接合结构250中的保护结构303。在执行平坦化工艺或薄化工艺之后，形成凹槽R3。凹槽R3是深的且具有尖锐形态，因此共形层305能够完全覆盖凹槽R3及凹槽R1的不平坦及尖锐的表面以防止在金属电路结构400的图案化工艺期间出现等离子体刻蚀电弧放电。在一些实施例中，保护结构303从第二管芯200的后侧200b延伸到位于第一管芯100的第一接合结构114与第二管芯200的第二接合结构214之间的界面15。
图4是根据一些实施例的封装体的剖视图。
参照图4，三维集成电路结构4通过粘合剂层21安装在介电层11之上。在一些实施例中，三维集成电路结构4可以是上述三维集成电路结构1、2及3中的一者。三维集成电路结构4包括在第一管芯100之上平行地排列的多个第二管芯201a及201b。第二管芯201a及201b与第一管芯100面对面接合在一起。第二管芯201a及201b的数目在本公开中不受限制。
在本实施例中，三维集成电路结构4还包括多个连接件18及钝化层19。连接件18形成在未被钝化层410覆盖的接合垫408之上且电连接到未被钝化层410覆盖的接合垫408。出于清楚的目的，图4中未示出接合垫408下方的其他组件，例如图1E所示的介电层402及金属特征404。连接件18包括焊料凸块、金凸块、铜凸块、铜柱、铜支柱等。钝化层19形成在钝化层410之上及连接件18旁，以覆盖连接件18的侧壁。
参照图4，在三维集成电路结构4旁形成绝缘包封体22，以包封三维集成电路结构4。在绝缘包封体22中形成多个导电柱14，且所述多个导电柱14环绕三维集成电路结构4。在三维集成电路结构4及导电柱14之上形成重布线层(redistribution layer，RDL)结构23，且所述重布线层结构23电连接到三维集成电路结构4及导电柱14。在一些实施例中，重布线层结构23包括交替堆叠的多个聚合物层PM1、PM2、PM3及PM4和多个重布线层RDL1、RDL2、RDL3及RDL4。聚合物层或重布线层的数目不受本公开的限制。
换句话说，重布线层RDL1贯穿聚合物层PM1且电连接到三维集成电路结构4的连接件18及导电柱14。重布线层RDL2贯穿聚合物层PM2且电连接到重布线层RDL1。重布线层RDL3贯穿聚合物层PM3且电连接到重布线层RDL2。重布线层RDL4贯穿聚合物层PM4且电连接到重布线层RDL3。在一些实施例中，聚合物层PM1、PM2、PM3及PM4中的每一者包括感光性材料，例如聚苯并恶唑(PBO)、聚酰亚胺(PI)、苯并环丁烯(PCB)、它们的组合等。在一些实施例中，重布线层RLD1、RDL2、RDL3及RDL4中的每一者包括导电材料。导电材料包括金属(例如铜、镍、钛、它们的组合等)，且通过电镀工艺形成。在一些实施例中，重布线层RDL1、RDL2、RDL3及RDL4分别包括晶种层(图中未示出)及形成在晶种层上的金属层(图中未示出)。晶种层可以是金属晶种层，例如铜晶种层。在一些实施例中，晶种层包括第一金属层(例如钛层)及位于第一金属层之上的第二金属层(例如铜层)。金属层可以是铜或其他合适的金属。在一些实施例中，重布线层RDL1、RDL2、RDL3及RDL4分别包括彼此连接的多个通孔及多条迹线。通孔连接迹线，且迹线分别位于聚合物层PM1、PM2、PM3及PM4上，且分别在聚合物层PM1、PM2、PM3及PM4的顶表面上延伸。
在一些实施例中，最顶部的重布线层RDL4包括RDL4a及RDL4b。重布线层RDL4a也被称为用于球安装的球下金属(under-ball metallurgy，UBM)层。重布线层RDL4b可以是用于连接到在后续工艺中形成的集成无源装置(integrated passive device，IPD)26的微凸块。
然后，在重布线层结构23的重布线层RDL4a之上形成多个连接件24，且所述多个连接件24电连接到重布线层结构23的重布线层RDL4a。在一些实施例中，连接件24由具有低电阻率的导电材料(例如Sn、Pb、Ag、Cu、Ni、Bi或它们的合金)制成，且通过合适的工艺(例如蒸镀、镀覆、球滴或丝网印刷)形成。集成无源装置26形成在重布线层结构23的重布线层RDL4b之上且通过焊料凸块28电连接到重布线层结构23的重布线层RDL4b。集成无源装置26可以是电容器、电阻器、电感器等、或它们的组合。集成无源装置26的数目并不仅限于图4所示的数目，而是可根据产品的设计进行调整。底部填充胶层27形成在集成无源装置26与聚合物层PM4之间，且环绕并覆盖暴露出的RDL4b、焊料凸块28及集成无源装置26的底表面。
如图4所示，然后将介电层11图案化，使得导电柱14的底表面被介电层11暴露出。在导电端子30分别形成在导电柱14的底表面之上之后，具有双侧端子的集成扇出型封装体P1便已完成。然后提供另一封装体P2。在一些实施例中，封装体P2是例如存储器装置。封装体P2堆叠在集成扇出型封装体P1之上且通过导电端子30电连接到集成扇出型封装体P1，从而制成叠层封装体(PoP)结构。
根据一些实施例，一种三维集成电路(3DIC)结构包括管芯堆叠结构、金属电路结构及第一保护结构。所述第一管芯具有前侧及后侧，且第二管芯具有前侧及后侧。所述第一管芯的所述前侧接合到所述第二管芯的所述前侧。所述第二管芯包括多个衬底穿孔(TSV)。所述金属电路结构设置在所述第二管芯的所述后侧之上。所述保护结构设置在所述第二管芯的所述后侧内且分隔所述多个衬底穿孔中的一者与所述金属电路结构。
在一些实施例中，所述第一保护结构的顶表面与所述第二管芯的所述后侧实质上共面。
在一些实施例中，所述第一保护结构包括共形层或复合结构，所述复合结构包括共形层及设置在所述共形层之上的填充层。
在一些实施例中，所述共形层及所述填充层是由不同的材料形成。
在一些实施例中，所述管芯堆叠结构还包括设置在所述第一管芯与所述第二管芯之间的混合接合结构。
在一些实施例中，所述三维集成电路结构还包括设置在所述第二管芯的所述后侧内的第二保护结构，其中所述第一保护结构直接接触所述多个衬底穿孔中的一者，而所述第二保护结构与所述多个衬底穿孔间隔开。
在一些实施例中，所述第一保护结构从所述第二管芯的所述后侧延伸到所述混合接合结构内。
在一些实施例中，所述多个衬底穿孔中的另一者电连接到所述金属电路结构，且所述第二管芯的所述多个衬底穿孔中的所述一者的顶表面低于所述第二管芯的所述多个衬底穿孔中的所述另一者的顶表面。
在一些实施例中，所述三维集成电路结构还包括：介电层以及介电层穿孔(TDV)。介电层在侧向上包封所述第二管芯。介电层穿孔设置在所述介电层中且电连接到所述第一管芯及所述金属电路结构。
在一些实施例中，所述介电层的顶表面、所述介电层穿孔的顶表面、所述第一保护结构的所述顶表面及所述第二管芯的所述后侧实质上共面。
在一些实施例中，所述管芯堆叠结构包括晶片上芯片(CoW)结构、芯片上芯片结构、管芯上管芯结构或它们的组合。
根据一些实施例，一种制造三维集成电路结构的方法包括以下步骤。形成包括面对面接合在一起的第一管芯与第二管芯的管芯堆叠结构。执行第一平坦化工艺以在所述第二管芯的后侧暴露出所述第二管芯的多个衬底穿孔(TSV)。所述第二管芯具有延伸到所述第二管芯的所述多个衬底穿孔中的一者中的凹槽。以共形层的方式将保护结构填入所述第一凹槽中。在所述第二管芯的所述后侧之上形成金属电路结构，以通过所述多个衬底穿孔中的另一者电连接到所述管芯堆叠结构。
在一些实施例中，所述将所述保护结构填入所述第一凹槽中包括：执行原子层沉积(ALD)工艺以在所述第二管芯的所述后侧上形成所述共形层，其中所述共形层完全覆盖所述第一凹槽的表面；执行化学气相沉积(CVD)工艺以在所述共形层之上形成填充层；以及执行第二平坦化工艺，以暴露出所述第二管芯的所述多个衬底穿孔中的所述另一者。
在一些实施例中，所述形成所述管芯堆叠结构包括：提供所述第一管芯及所述第二管芯；以及在所述第一管芯与所述第二管芯之间形成混合接合结构，以接合所述第一管芯与所述第二管芯。
在一些实施例中，在执行所述第一平坦化工艺之后所述第二管芯的所述后侧包括第二凹槽，所述第一凹槽及所述第二凹槽沿着从所述第二管芯的所述后侧朝所述混合接合结构的方向延伸，且所述第二凹槽与所述第二管芯的所述多个衬底穿孔间隔开。
在一些实施例中，在执行所述第一平坦化工艺后，所述第一凹槽从所述第二管芯的所述后侧延伸到所述混合接合结构中。
在一些实施例中，在执行所述第一平坦化工艺后，所述第二管芯的所述多个衬底穿孔中的所述一者的顶表面低于所述第二管芯的所述多个衬底穿孔中的所述另一者的顶表面。
在一些实施例中，在执行所述第二平坦化工艺后，所述保护结构的顶表面与所述第二管芯的所述后侧实质上共面。
根据一些实施例，一种封装体包括三维集成电路结构、绝缘包封体、重布线层(RDL)结构及多个连接件。所述三维集成电路结构包括管芯堆叠结构、金属电路结构及位于所述管芯堆叠结构与所述金属电路结构之间的保护结构。所述金属电路结构通过所述管芯堆叠结构的多个衬底穿孔(TSV)中的一者电连接到所述管芯堆叠结构。所述保护结构分隔及电隔离所述管芯堆叠结构的衬底穿孔中的另一者与所述金属电路结构。所述绝缘包封体在侧向上包封所述三维集成电路结构。所述重布线层结构设置在所述三维集成电路结构及所述绝缘包封体之上。所述多个连接件设置在所述三维集成电路结构之上且通过所述重布线层结构电连接到所述三维集成电路结构。
在一些实施例中，所述管芯堆叠结构包括第一管芯及在所述第一管芯之上平行地排列的多个第二管芯。
以上概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解本公开的各个方面。所属领域中的技术人员应理解，其可容易地使用本公开作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的及/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到，这些等效构造并不背离本公开的精神及范围，而且他们可在不背离本公开的精神及范围的条件下对其作出各种改变、替代及变更。

Claims (26)

1.一种三维集成电路结构，其特征在于，包括：
管芯堆叠结构，包括第一管芯及第二管芯，所述第一管芯具有前侧及后侧，所述第二管芯具有前侧及后侧，所述第一管芯的所述前侧接合到所述第二管芯的所述前侧，所述第二管芯包括多个衬底穿孔；
金属电路结构，设置在所述第二管芯的所述后侧之上；以及
第一保护结构，设置在所述第二管芯的所述后侧内，且分隔及电隔离所述第二管芯的所述多个衬底穿孔中的一者与所述金属电路结构。
2.根据权利要求1所述的三维集成电路结构，其特征在于，所述第一保护结构的顶表面与所述第二管芯的所述后侧实质上共面。
3.根据权利要求1所述的三维集成电路结构，其特征在于，所述第一保护结构包括共形层。
4.根据权利要求1所述的三维集成电路结构，其特征在于，所述第一保护结构包括复合结构，所述复合结构包括共形层及设置在所述共形层之上的填充层，且所述共形层及所述填充层是由不同的材料形成。
5.根据权利要求1所述的三维集成电路结构，其特征在于，所述管芯堆叠结构还包括设置在所述第一管芯与所述第二管芯之间的混合接合结构。
6.根据权利要求5所述的三维集成电路结构，其特征在于，还包括设置在所述第二管芯的所述后侧内的第二保护结构，其中所述第一保护结构直接接触所述多个衬底穿孔中的一者，而所述第二保护结构与所述多个衬底穿孔间隔开。
7.根据权利要求5所述的三维集成电路结构，其特征在于，所述第一保护结构从所述第二管芯的所述后侧延伸到所述混合接合结构内。
8.根据权利要求1所述的三维集成电路结构，其特征在于，所述多个衬底穿孔中的另一者电连接到所述金属电路结构，且所述第二管芯的所述多个衬底穿孔中的所述一者的顶表面低于所述第二管芯的所述多个衬底穿孔中的所述另一者的顶表面。
9.根据权利要求1所述的三维集成电路结构，其特征在于，还包括：
介电层，在侧向上包封所述第二管芯；以及
介电层穿孔(TDV)，设置在所述介电层中且电连接到所述第一管芯及所述金属电路结构。
10.根据权利要求9所述的三维集成电路结构，其特征在于，所述介电层的顶表面、所述介电层穿孔的顶表面、所述第一保护结构的所述顶表面及所述第二管芯的所述后侧实质上共面。
11.根据权利要求1所述的三维集成电路结构，其特征在于，所述管芯堆叠结构包括晶片上芯片(CoW)结构、芯片上芯片结构、管芯上管芯结构或它们的组合。
12.一种制造三维集成电路结构的方法，其特征在于，包括：
形成管芯堆叠结构，所述管芯堆叠结构包括面对面接合在一起的第一管芯与第二管芯；
执行第一平坦化工艺，以在所述第二管芯的后侧暴露出所述第二管芯的多个衬底穿孔(TSV)，其中所述第二管芯的所述后侧具有第一凹槽，所述第一凹槽延伸到所述第二管芯的所述多个衬底穿孔中的一者中；
以共形层的方式将保护结构填入所述第一凹槽中；以及
在所述第二管芯的所述后侧之上形成金属电路结构，以通过所述多个衬底穿孔中的另一者电连接到所述管芯堆叠结构，其中所述保护结构电隔离所述第二管芯的所述多个衬底穿孔中的所述一者与所述金属电路结构。
13.根据权利要求12所述的方法，其特征在于，所述将所述保护结构填入所述第一凹槽中包括：
执行原子层沉积(ALD)工艺以在所述第二管芯的所述后侧上形成所述共形层，其中所述共形层完全覆盖所述第一凹槽的表面；
执行化学气相沉积(CVD)工艺以在所述共形层之上形成填充层；以及
执行第二平坦化工艺，以暴露出所述第二管芯的所述多个衬底穿孔中的所述另一者。
14.根据权利要求12所述的方法，其特征在于，所述形成所述管芯堆叠结构包括：
提供所述第一管芯及所述第二管芯；以及
在所述第一管芯与所述第二管芯之间形成混合接合结构，以接合所述第一管芯与所述第二管芯。
15.根据权利要求14所述的方法，其特征在于，在执行所述第一平坦化工艺之后所述第二管芯的所述后侧包括第二凹槽，所述第一凹槽及所述第二凹槽沿着从所述第二管芯的所述后侧朝所述混合接合结构的方向延伸，且所述第二凹槽与所述第二管芯的所述多个衬底穿孔间隔开。
16.根据权利要求14所述的方法，其特征在于，在执行所述第一平坦化工艺后，所述第一凹槽从所述第二管芯的所述后侧延伸到所述混合接合结构中。
17.根据权利要求12所述的方法，其特征在于，在执行所述第一平坦化工艺后，所述第二管芯的所述多个衬底穿孔中的所述一者的顶表面低于所述第二管芯的所述多个衬底穿孔中的所述另一者的顶表面。
18.根据权利要求13所述的方法，其特征在于，在执行所述第二平坦化工艺后，所述保护结构的顶表面与所述第二管芯的所述后侧实质上共面。
19.一种封装体，其特征在于，包括：
三维集成电路结构，包括管芯堆叠结构、金属电路结构及位于所述管芯堆叠结构与所述金属电路结构之间的保护结构，其中所述金属电路结构通过所述管芯堆叠结构的多个衬底穿孔(TSV)中的一者电连接到所述管芯堆叠结构，且所述保护结构分隔及电隔离所述管芯堆叠结构的所述多个衬底穿孔中的另一者与所述金属电路结构；
绝缘包封体，在侧向上包封所述三维集成电路结构；
重布线层(RDL)结构，设置在所述三维集成电路结构及所述绝缘包封体之上；以及
多个连接件，设置在所述三维集成电路结构之上并通过所述重布线层结构电连接到所述三维集成电路结构。
20.根据权利要求19所述的封装体，其特征在于，所述管芯堆叠结构包括第一管芯及在所述第一管芯之上平行地排列的多个第二管芯。
21.一种三维集成电路结构，其特征在于，包括：
管芯堆叠结构，包括接合在一起的第一管芯及第二管芯，所述第二管芯具有多个衬底穿孔；
金属电路结构，设置在所述第二管芯的后侧之上；以及
第一保护结构，夹置在所述金属电路结构的底表面与所述第二管芯的所述多个衬底穿孔中的一者的顶表面之间且接触所述金属电路结构的所述底表面与所述第二管芯的所述多个衬底穿孔中的所述一者的所述顶表面，其中所述第一保护结构内埋在第二管芯的所述后侧内，且分隔及电隔离所述第二管芯的所述多个衬底穿孔中的所述一者与所述金属电路结构。
22.一种制造三维集成电路结构的方法，其特征在于，包括：
形成管芯堆叠结构，所述管芯堆叠结构包括面对面接合在一起的第一管芯与第二管芯；
执行第一平坦化工艺，以在所述第二管芯的后侧暴露出所述第二管芯的多个衬底穿孔，其中所述第二管芯的所述后侧具有第一凹槽，所述第一凹槽延伸到所述第二管芯的所述多个衬底穿孔中的一者中；
将保护材料填入所述第一凹槽中；以及
执行第二平坦化工艺，以暴露出所述第二管芯的所述多个衬底穿孔中的另一者并在所述第一凹槽中形成保护结构，其中所述保护结构的顶表面与所述多个衬底穿孔中的所述另一者的顶表面实质上共面。
23.一种三维集成电路结构，其特征在于，包括：
管芯堆叠结构，包括接合在一起的第一管芯及第二管芯，所述第二管芯具有多个衬底穿孔；
金属电路结构，设置在所述第二管芯的顶表面之上；以及
电隔离结构，内埋在第二管芯的所述顶表面内，且电隔离所述第二管芯的所述多个衬底穿孔中的一者与所述金属电路结构。
24.一种半导体封装结构，其特征在于，包括：
第一管芯，具有第一接合结构于其上；
第二管芯，具有第二接合结构于其上，其中所述第二管芯接合至所述第一管芯，以使所述第一接合结构的第一接合介电层接触所述第二接合结构的第二接合介电层；
金属电路结构，设置在所述第二管芯的顶表面之上；以及
第一保护结构，内埋在所述第二管芯的所述顶表面内，且夹置在所述金属电路结构与所述第二管芯之间。
25.一种制造半导体封装结构的方法，其特征在于，包括：
在第一管芯上形成第一接合结构；
在第二管芯上形成第二接合结构；
通过将所述第一接合结构的第一接合介电层接触所述第二接合结构的第二接合介电层的方式将所述第二管芯接合在所述第一管芯上；
对所述第二管芯的顶表面执行第一平坦化工艺，以在所述第二管芯的所述顶表面内形成第一凹槽；
在所述第一凹槽中形成第一保护结构；以及
在所述第二管芯的所述顶表面与第一保护结构之上形成金属电路结构，其中所述第一保护结构夹置在所述金属电路结构与所述第二管芯之间。
26.一种封装体，其特征在于，包括：
第一芯片；
第二芯片，具有包括多个衬底穿孔且接合在所述第一芯片上；
间隙填充介电层，配置在所述第一芯片上且在侧向上包封所述第二芯片；
金属电路结构，设置在所述第二芯片的顶表面之上；以及
电隔离结构，内埋在第二芯片的所述顶表面内，且电隔离所述第二芯片的所述多个衬底穿孔中的一者与所述金属电路结构。
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US20190393194A1 (en) 2019-12-26
CN110648995A (zh) 2020-01-03
TW202002188A (zh) 2020-01-01
US10504873B1 (en) 2019-12-10
US20200098731A1 (en) 2020-03-26
US11532598B2 (en) 2022-12-20
US10867968B2 (en) 2020-12-15
TWI760561B (zh) 2022-04-11

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