CN110648970B - Semiconductor device and method of forming the same - Google Patents

Abstract

A semiconductor structure and a method of forming the same, wherein the method comprises: providing a substrate, wherein the substrate comprises a first area and a second area, and the first area and the second area are respectively provided with a pseudo gate structure and an interlayer dielectric layer which cover a part of the surface of the substrate; removing the dummy gate structure in the first interlayer dielectric layer to form a first dummy gate opening; removing the dummy gate structure in the second interlayer dielectric layer to form a second dummy gate opening; forming contact holes in the interlayer dielectric layers of the first region and the second region respectively, wherein the bottoms of the contact holes are exposed out of the source-drain doped regions of the first region and the second region respectively; forming a metal silicide layer on the bottom surface of the contact hole; forming a conductive plug filling the contact hole after forming the metal silicide layer; and after the conductive plug is formed, forming N-type work function material layers in the first dummy gate opening and the second dummy gate opening respectively. The semiconductor device formed by the method has better performance.

Description

Semiconductor device and method of forming the same

technical field

The present invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor device.

Background technique

With the development of semiconductor technology, the control ability of traditional planar MOS transistors on channel current is weakened, resulting in serious leakage current. Fin Field Effect Transistor (Fin FET) is an emerging multi-gate device, which generally includes a fin protruding from the surface of a semiconductor substrate, a gate structure covering part of the top surface and sidewalls of the fin, Source and drain doped regions in the fins on both sides of the gate structure.

Usually, a silicide last process is used to form metal silicide in the contact holes on the source and drain doped regions, so as to reduce the contact resistance between the source and drain doped regions and the upper metal. However, the annealing process used to form the metal silicide intensifies the diffusion of Al ions in the N-type work function material layer. The performance of semiconductor devices formed using the prior art needs to be improved.

SUMMARY OF THE INVENTION

The technical problem solved by the present invention is to provide a method for forming a semiconductor device, which reduces the diffusion of Al ions in the N-type work function material layer in the NMOS transistor to the gate dielectric layer.

In order to solve the above technical problems, embodiments of the present invention provide a method for forming a semiconductor device, including: providing a substrate, the substrate has a dummy gate structure and an interlayer dielectric layer covering part of the surface of the substrate, so The interlayer dielectric layer covers the sidewall surface of the dummy gate structure, and the substrate on both sides of the dummy gate structure has source and drain doped regions; the dummy gate structure is removed, and the interlayer dielectric layer is forming a dummy gate opening; forming a contact hole in the interlayer dielectric layer, and exposing source and drain doped regions at the bottom of the contact hole; forming a metal silicide layer on the bottom surface of the contact hole; forming the metal silicide After the layer is formed, a conductive plug is formed to fill the contact hole; after the conductive plug is formed, an N-type work function material layer is formed in the dummy gate opening.

Optionally, after the dummy gate opening is formed, the contact hole is formed.

Optionally, after forming the dummy gate opening and before forming the contact hole, the method further includes: forming an interface layer on the sidewall and bottom surface of the dummy gate opening; forming a gate dielectric layer on the surface of the interface layer ; A diffusion barrier layer is formed on the surface of the gate dielectric layer.

Optionally, the substrate includes a first region and a second region; the first region is used for forming an N-type field effect transistor, and the second region is used for forming a P-type field effect transistor.

Optionally, the dummy gate structures are respectively located on the substrate surface of the first region and the substrate surface of the second region; the source and drain doped regions are respectively located in the substrate of the first region and the second region The contact holes are respectively located in the interlayer dielectric layer in the first region and in the interlayer dielectric layer in the second region; the N-type work function material layers are located in the dummy gate openings in the first region and within the dummy gate opening of the second region.

Optionally, after forming the diffusion barrier layer and before forming the contact hole, the method further includes: forming a sacrificial structure in the dummy gate opening in the first region and in the dummy gate opening in the second region, and the The sacrificial structure fills the dummy gate openings of the first region and the dummy gate openings of the second region.

Optionally, the sacrificial structure includes a first sacrificial layer and a second sacrificial layer located on the surface of the first sacrificial layer.

Optionally, the step of forming the sacrificial structure includes: forming a first sacrificial layer on the sidewalls and bottom surfaces of the dummy gate opening in the first region and the dummy gate opening in the second region; forming a first sacrificial layer on the surface of the first sacrificial layer The second sacrificial layer.

Optionally, the material of the first sacrificial layer includes amorphous silicon, polycrystalline silicon or single crystal silicon; the material of the second sacrificial layer includes silicon oxide.

Optionally, the method for forming the sacrificial structure further includes: performing a first annealing process after forming the first sacrificial layer; the annealing temperature of the first annealing process is 800 degrees Celsius to 1000 degrees Celsius.

Optionally, the sacrificial structure is a single layer; the material of the sacrificial structure includes amorphous silicon, polycrystalline silicon or single crystal silicon.

Optionally, a second annealing process is performed after the sacrificial structure is formed; the annealing temperature of the second annealing process is 800 degrees Celsius to 1000 degrees Celsius.

Optionally, the method for forming the metal silicide layer includes: depositing a metal layer on the sidewall and bottom surface of the contact hole; performing a third annealing process to make the metal layer react with the surface of the source and drain doped regions to form metal silicide The third annealing process is a laser annealing process, and the annealing temperature is 750 degrees Celsius to 900 degrees Celsius.

Optionally, the material of the metal silicide layer includes: titanium silicon compound.

Optionally, after forming the conductive plug and before forming the N-type work function material layer, the method further includes: removing the dummy gate opening in the first region and the sacrificial structure in the dummy gate opening in the second region; After the dummy gate opening in the first region and the sacrificial structure in the dummy gate opening in the second region, the diffusion barrier layer in the dummy gate opening in the first region is removed.

Optionally, after removing the diffusion barrier layer in the dummy gate opening in the first region, and before forming the N-type work function material layer, the method further includes: forming a P-type work function in the dummy gate opening in the second region. functional material layer.

Optionally, the material of the P-type work function material layer includes titanium nitride or tantalum nitride.

Optionally, the material of the N-type work function material layer includes one or more combinations of TiAl, TiAlC, TiAlN and AlN.

Optionally, after forming the N-type work function material layer in the dummy gate opening, the method further includes: filling the dummy gate opening with a metal material to form a metal gate.

Correspondingly, the present invention also provides a semiconductor device formed by any one of the above methods.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following beneficial effects:

In the method for forming a semiconductor device provided by the technical solution of the present invention, after the metal silicide layer is formed in the contact hole, a conductive plug is formed to fill the contact hole; An N-type work function material layer is formed in the dummy gate opening. After the metal silicide layer is formed in the contact hole, the N-type work function material layer is formed in the dummy gate opening, so that the high temperature process of the annealing process for forming the metal silicide layer can be avoided. The influence of the substance can reduce the diffusion of Al ions in the N-type work function material layer, thereby reducing the diffusion of Al ions in the N-type work function material layer in the transistor to the gate dielectric layer, thereby improving the interface state of the gate dielectric layer, Further, the reliability of the gate dielectric layer is improved, and the change of the turn-on voltage of the device is avoided at the same time, so that the performance of the obtained semiconductor device is improved.

Further, the fourth annealing process for forming the gate dielectric layer, on the one hand, repairs the defects of the gate dielectric layer and improves the interface state of the gate dielectric layer, thereby helping to improve the reliability and turn-on voltage of the semiconductor device; on the other hand, The gate dielectric layer is formed before the metal silicide layer, thereby avoiding the influence of the fourth annealing process on the metal silicide layer, improving the quality of the formed metal silicide layer, thereby reducing the contact resistance of the source-drain doped region and the conductive plug, Therefore, it is beneficial to improve the performance of the semiconductor device.

Further, the forming method further includes: before forming the contact hole, forming an interface layer on the sidewall and bottom surface of the dummy gate opening. The interface layer can prevent the substrate from coming into contact with the gate dielectric layer formed on the surface of the interface layer subsequently, thereby helping to improve the performance of the semiconductor device.

Further, the diffusion barrier layer, on the one hand, can be used as a P-type work function material layer in the PMOS transistor, and on the other hand, can be used as a barrier layer to prevent the N-type work function material layer in the PMOS transistor from diffusing to the gate dielectric layer, Thereby, the reliability and turn-on voltage of the semiconductor device are improved.

Description of drawings

1 to 14 are schematic structural diagrams of steps of a method for forming a semiconductor device according to an embodiment of the present invention.

Detailed ways

As described in the background art, the performance of the semiconductor devices formed by the prior art has yet to be improved.

A method for forming a semiconductor device, comprising: providing a semiconductor substrate, the substrate includes an NMOS transistor region and a PMOS transistor region, and the semiconductor substrate of the NMOS transistor region and the PMOS transistor region has a dummy gate covering part of the surface of the substrate structure and an interlayer dielectric layer, the interlayer dielectric layer covers the sidewall surface of the dummy gate structure, and the substrate on both sides of the dummy gate structure has source and drain doped regions; the dummy gate of the NMOS transistor region is removed structure, a first dummy gate opening is formed in the interlayer dielectric layer in the NMOS transistor region; the dummy gate structure in the PMOS transistor region is removed, and a second dummy gate opening is formed in the interlayer dielectric layer in the PMOS transistor region; a first dummy gate opening is formed After the gate opening and the second dummy gate opening, a high-k dielectric layer, an N-type work function material layer on the high-k dielectric layer, and an N-type work function material are formed on the sidewalls and the bottom of the first dummy gate opening A metal gate on the layer; a high-k dielectric layer, a P-type work function material layer on the high-k dielectric layer, and a metal on the P-type work function material layer are formed on the sidewalls and the bottom of the second dummy gate opening gate; after the metal gate is formed in the first dummy gate opening and the second dummy gate opening, a contact hole is formed over the source and drain doped regions of the NMOS transistor region and the PMOS transistor region, respectively, and the sidewall and bottom of the contact hole are formed A metal silicide layer is formed on the surface; after the metal silicide layer is formed, the contact hole is filled with metal material to form a conductive plug.

By forming the metal silicide layer after forming the work function material layer, it can be avoided that the annealing process performed after the formation of the high-k dielectric layer and the heat treatment performed during the process of forming the work function material layer have an influence on the metal silicide layer that has been formed. The quality of the metal silicide layer can be improved, the contact resistance of the source-drain doped region and the conductive plug can be reduced, and the formed semiconductor device has better performance.

By forming a metal silicide layer in the contact hole on the source-drain doped region, the contact resistance between the source-drain doped region and the metal layer filling the contact hole can be reduced. However, an annealing process is required to form the metal silicide layer. After the N-type work function metal material layer is formed on the sidewalls and the bottom of the first dummy gate opening, metal silicide is formed in the contact holes on the source and drain doped regions. The high temperature process of the annealing process will aggravate the diffusion of Al ions in the N-type work function material layer formed in the NMOS transistor to the lower gate dielectric layer, thereby affecting the interface state of the gate dielectric layer, thereby affecting the interface reliability of the gate dielectric layer. and the turn-on voltage of the semiconductor device, so that the performance of the formed semiconductor device is poor.

In order to solve the technical problem, the present invention provides a method for forming a semiconductor structure, comprising: forming a contact hole in the interlayer dielectric layer, the bottom of the contact hole exposes a source and drain doped region; A metal silicide layer is formed on the bottom surface of the hole; after the metal silicide layer is formed, an N-type work function material layer is formed in the dummy gate opening. The semiconductor device formed by the method has better performance.

In order to make the above objects, features and beneficial effects of the present invention more clearly understood, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Referring to FIG. 1, a substrate 100 is provided, the substrate includes a first region A and a second region B, the substrate 100 has a dummy gate structure 103 and an interlayer dielectric layer 107 covering part of the surface of the substrate, The interlayer dielectric layer 107 covers the sidewall surface of the dummy gate structure 103 , the substrate 100 on both sides of the dummy gate structure 103 has source and drain doped regions 106 , and the surface of the interlayer dielectric layer 107 has a covering The protective layer 108 on the sidewall of the dummy gate structure 103 .

In this embodiment, the substrate 100 includes: a base 101 and a fin 102 located on the base 101 .

In other embodiments, when the semiconductor device is a planar MOS transistor, the substrate is a planar semiconductor substrate.

In this embodiment, the first area A is used to form NMOS transistors, and the second area B is used to form PMOS transistors.

In this embodiment, the method for forming the substrate 100 includes: providing an initial substrate with a first mask layer thereon, the first mask layer exposing a part of the top surface of the initial substrate; The first mask layer is a mask, and the initial substrate is etched to form the substrate 101 and the fins 102 on the substrate 101 .

In this embodiment, the material of the initial substrate is silicon. Correspondingly, the material of the base 101 and the fins 102 is silicon.

In the present embodiment, the sidewall surfaces of the dummy gate structure 103 have offset spacers 104 and main spacers 105 located on the sidewall surfaces of the offset spacers 104 .

The offset spacers 104 are used to define the positions of the lightly doped regions (not shown). The main spacers 105 are used to define the positions of the source and drain doped regions 106 .

The substrate 100 also has an isolation structure (not shown in the figure) covering the fins 102 , and the top surface of the isolation structure is lower than the top surface of the fins 102 and covers part of the fins 102 side wall.

Referring to FIG. 2, the dummy gate structure 103 in the interlayer dielectric layer 107 in the first region A is removed to form a first dummy gate opening 109; the dummy gate structure in the interlayer dielectric layer 107 in the second region B is removed 103 forms a second dummy gate opening 110 .

In this embodiment, the process of removing the dummy gate structure 103 is a dry etching process. The specific process parameters include: the gas used includes HBr and He, wherein the flow rate of HBr is 150 standard ml/min to 500 standard ml/min, the flow rate of He is 100 standard ml/min to 400 standard ml/min, and the pressure is 3 mTorr to 10 mTorr, the side wall radio frequency power is 200 watts to 500 watts, the bottom radio frequency power is 10 watts to 40 watts, and the temperature is 50 degrees Celsius to 100 degrees Celsius.

The first dummy gate opening 109 and the second dummy gate opening 110 are used for subsequent formation of the gate structure.

Referring to FIG. 3 , an interface film 111 , a gate dielectric film 112 located on the surface of the interface film 111 and a gate dielectric film 112 located on the surface of the interface film 111 are formed on the sidewalls and bottom surfaces of the first dummy gate opening 109 and the second dummy gate opening 110 and the surface of the protective layer 108 . The diffusion barrier film 113 on the surface of the gate dielectric film 112 .

The process of forming the interface film 111 includes chemical vapor deposition process, physical vapor deposition process or atomic layer deposition process.

The interface film 111 is used for the subsequent formation of the interface layer. In this embodiment, the material of the interface film 111 includes: silicon oxide. Correspondingly, the subsequently formed interface layer material includes: silicon oxide.

The gate dielectric layer film 112 is used for subsequent formation of the gate dielectric layer. The material of the gate dielectric film 112 is a high-K (K greater than 3.9) dielectric material. In this embodiment, the material of the gate dielectric layer film 112 is hafnium oxide. Correspondingly, the material of the subsequently formed gate dielectric layer is hafnium oxide. In other embodiments, the material of the gate dielectric layer film includes: La ₂ O ₃ , HfSiON, HfAlO ₂ , ZrO ₂ , Al ₂ O ₃ or HfSiO ₄ .

The formation process of the gate dielectric layer film 112 includes a chemical vapor deposition process or a physical vapor deposition process.

In this embodiment, a fourth annealing process is performed after the gate dielectric film 112 is formed; the annealing temperature of the fourth annealing process is 800 degrees Celsius to 1000 degrees Celsius.

The fourth annealing process can repair the defects of the gate dielectric film 112, thereby repairing the defects of the gate dielectric layer formed subsequently, and improving the interface state of the gate dielectric layer, thereby helping to improve the reliability and turn-on voltage of the semiconductor device.

The diffusion barrier film 113 is used for subsequent formation of a diffusion barrier layer. The material of the diffusion barrier film 113 includes tantalum nitride or titanium nitride. In this embodiment, the material of the diffusion barrier film 113 is titanium nitride. Correspondingly, the material of the subsequently formed diffusion barrier layer is titanium nitride.

The formation process of the diffusion barrier film 113 includes a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

In this embodiment, the process of forming the diffusion barrier film 113 is an atomic layer deposition process. The specific process parameters include: providing an organic precursor material containing titanium, the temperature is 80 degrees Celsius to 300 degrees Celsius, the pressure is 5 mTorr to 20 Torr, and the number of cycles is 5 to 50 times.

In this embodiment, after the diffusion barrier film 113 is formed subsequently, a sacrificial structure is formed in the first dummy gate opening 109 and the second dummy gate opening 110 , and the sacrificial structure fills the first dummy gate opening 109 and the second dummy gate opening 109 . Two dummy gate openings 110 . The sacrificial structure includes: a first sacrificial layer located on the bottom and sidewall surfaces of the first dummy gate opening 109 and the second dummy gate opening 110 and a second sacrificial layer located on the surface of the first sacrificial layer. The formation process of the first sacrificial layer and the second sacrificial layer will be described later with reference to FIGS. 4 to 5 .

Referring to FIG. 4 , a first sacrificial film 114 and a second sacrificial film 115 are formed on the surface of the diffusion barrier film 113 in the first dummy gate opening 109 and the second dummy gate opening 110 .

The forming steps of the first sacrificial film 114 and the second sacrificial film 115 include: forming a first sacrificial film 115 on the surface of the diffusion barrier film of the first dummy gate opening 109 and the second dummy gate opening 110; A second sacrificial film 115 is formed on the surface of the sacrificial film 114 , and the second sacrificial film 115 fills the first dummy gate opening 109 and the second dummy gate opening 110 .

The material of the first sacrificial film 114 includes amorphous silicon, polycrystalline silicon, and single crystal silicon. In this embodiment, the material of the first sacrificial film 114 is amorphous silicon. The amorphous silicon material can balance the oxygen content in the high-k dielectric material, and the oxygen content in the high-k dielectric layer is too high or too low. Therefore, forming the first sacrificial film 114 is beneficial to improve the performance of the semiconductor device.

The process of forming the first sacrificial film 114 includes a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process. The first sacrificial film 115 is used for the subsequent formation of the first sacrificial layer.

In this embodiment, the process of forming the first sacrificial film 114 is a chemical vapor deposition process. The specific process parameters include: the gas used includes SiH ₄ , the flow rate of the SiH ₄ is 30 standard ml/min to 3000 standard ml/min, the temperature is 360 to 520 degrees Celsius, and the pressure is 0.03 to 10 torr.

The thickness of the first sacrificial film 114 is 35 angstroms to 110 angstroms.

The significance of selecting the thickness of the first sacrificial film 114 is that if the thickness of the first sacrificial film is too thin, its protective effect on the lower gate dielectric film and the interface film is not enough, and the gate dielectric film and the interface film are easily affected by subsequent steps. Due to the influence of the annealing process, the resulting semiconductor device has poor performance; if the thickness of the first sacrificial film is too thick, since the amorphous silicon material is easily affected by the subsequent first annealing process, atomic agglomeration occurs, which is not conducive to the subsequent process. It is removed and the resulting semiconductor device has poor performance.

In this embodiment, after the first sacrificial film 114 is formed, a first annealing process is performed; the annealing temperature of the first annealing process is 800 degrees Celsius to 1000 degrees Celsius.

The first annealing process can increase the density of the underlying interface film 111 , thereby improving the isolation effect of the subsequently formed interface layer on the substrate 100 and the subsequently formed gate dielectric layer, thereby improving the performance of the semiconductor device.

The process of forming the second sacrificial film 115 includes a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process. The material of the second sacrificial layer film 115 includes silicon oxide, which is used for the subsequent formation of the second sacrificial layer.

Referring to FIG. 5 , planarize the interface film 111 , the gate dielectric film 112 , the diffusion barrier film 113 , the first sacrificial film 114 , and the second sacrificial film 115 until the top surface of the protective layer 108 is exposed. The side and bottom surfaces of the dummy gate opening 109 and the second dummy gate opening form an interface layer 116 , a gate dielectric layer 117 on the interface layer 116 , a diffusion barrier layer 118 on the gate dielectric layer 117 , and a diffusion barrier layer 118 on the diffusion barrier layer 118 The first sacrificial layer 119 and the second sacrificial layer 120 on the first sacrificial layer 119 .

The process of planarizing the interface film 111 , the gate dielectric film 112 , the diffusion barrier film 113 , the first sacrificial film 114 , and the second sacrificial film 115 until the top surface of the protection layer 108 is exposed includes: a chemical mechanical polishing process.

In other embodiments, the sacrificial structure is a single-layer sacrificial structure, the material of the single-layer sacrificial structure includes amorphous silicon, polysilicon or monocrystalline silicon, and the single-layer sacrificial structure fills the first dummy gate opening and a second dummy gate opening. After the sacrificial structure is formed, a second annealing process is performed; the annealing temperature of the second annealing process is 800 degrees Celsius to 1000 degrees Celsius.

Referring to FIG. 6 , contact holes 121 are formed in the interlayer dielectric layers 107 of the first region A and the second region B, respectively, and the bottoms of the contact holes 121 expose the sources of the first region A and the second region B, respectively Drain doped region 106 .

The method for forming the contact hole 121 includes: respectively forming a second mask layer (not shown in the figure) on the surface of the interlayer dielectric layer 107 in the first region A and the second region B, the second mask layer to expose part of the top surface of the interlayer dielectric layer 107; using the second mask layer as a mask, the interlayer dielectric layer 107 is etched until the top surface of the source and drain doped regions 106 is exposed. Contact holes 121 are formed in the interlayer dielectric layer 107 .

The second mask layer is used to define the position and size of the contact hole at the top of the source-drain doped region 106 .

The material of the second mask layer includes silicon nitride or titanium nitride.

The process of etching the interlayer dielectric layer 107 includes: one or a combination of a dry etching process and a wet etching process.

In this embodiment, the process of etching the interlayer dielectric layer 107 is a dry etching process. The specific process parameters include: the gas used includes CH ₄ and CHF ₃ , the flow rate of CH ₄ is 8 standard ml/min～500 standard ml/min, the flow rate of CHF ₃ is 30 standard ml/min～200 standard ml/min, the pressure It is 10 mtorr to 2000 mtorr, the radio frequency power is 100 watts to 1300 watts, the bias voltage is 80 volts to 500 volts, and the time is 4 seconds to 500 seconds.

The contact holes 121 are used for accommodating conductive plugs subsequently.

Referring to FIG. 7 , a metal silicide layer 122 is formed on the bottom surface of the contact hole 121 .

The method for forming the metal silicide layer 122 includes: depositing and forming a metal layer (not shown in the figure) on the sidewall and bottom surface of the contact hole 121; 106 The surface reacts to form the metal silicide layer 122; after the annealing process, the remaining metal layer is removed.

The third annealing process adopts a laser annealing process, and the annealing temperature is 750 degrees Celsius to 900 degrees Celsius.

The material of the metal silicide layer 122 includes: titanium silicon compound. The metal silicide layer 122 can improve the contact resistance between the subsequently formed conductive plug and the source and drain doped regions 106 .

Referring to FIG. 8 , after the metal silicide layer 122 is formed, a conductive plug 123 filling the contact hole 121 is formed.

The method for forming the conductive plug 123 includes: forming a conductive plug film (not shown in the figure) in the first dummy gate opening 109 and the second dummy gate opening 110 and on the surface of the protective layer 108; removing part of the conductive plug; until the top surface of the protective layer 108 is exposed, and a conductive plug 123 is formed in the contact hole 121 .

The material of the conductive plug film is metal. Therefore, the material of the conductive plug 123 is metal. Metal tungsten has excellent step coverage (step coverage) and filling, and becomes the preferred material for electrical conductivity. In this embodiment, the material of the conductive plug film is tungsten, and correspondingly, the material of the conductive plug 123 is tungsten. In other embodiments, the material of the conductive plug includes aluminum or copper.

The formation process of the conductive plug film includes a chemical vapor deposition process or a physical vapor deposition process.

In this embodiment, the process of forming the conductive plug film is a chemical vapor deposition process. The specific process parameters include: the gas used includes WF ₆ , and the flow rate of WF ₆ is 100 standard ml/min to 600 standard ml/min.

The process of removing part of the conductive plug film includes a chemical mechanical polishing process.

Referring to FIG. 9 , after the conductive plug 123 is formed and before the N-type work function material layer is formed, the sacrificial structures in the first dummy gate opening 109 and the second dummy gate opening 110 are removed (not shown in the figure). ).

The step of removing the sacrificial structure in the first dummy gate opening 109 and the second dummy gate opening 110 includes: removing the second sacrificial layer 120 in the first dummy gate opening 109 and the second dummy gate opening 110; removing all the After the second sacrificial layer 120 is removed, the first sacrificial layer 119 in the first dummy gate opening and the second dummy gate opening 110 is removed.

The process of removing the second sacrificial layer in the first dummy gate opening 109 and the second dummy gate opening 110 includes: one or a combination of a dry etching process and a wet etching process.

In this embodiment, the process of removing the second sacrificial layer in the first dummy gate opening 109 and the second dummy gate opening 110 is a dry etching process. The specific process parameters include: the gases used include He, NH ₃ and NF ₃ , wherein the flow rate of He is 600 standard ml/min to 2000 standard ml/min, and the flow rate of NH ₃ is 200 standard ml/min to 500 standard ml/min. minute, the flow rate of NF ₃ is 20 standard ml/min to 200 standard ml/min, the pressure is 2 Torr to 10 Torr, and the time is 20 to 100 seconds.

The process of removing the first sacrificial layer in the first dummy gate opening 109 and the second dummy gate opening 110 includes: one or a combination of a dry etching process and a wet etching process.

In this embodiment, the process of removing the first sacrificial layer in the first dummy gate opening 109 and the second dummy gate opening 110 is a wet etching process. The specific process parameters include: the etching solution includes NH ₄ OH solution and H ₂ O, the volume relationship between the NH ₄ OH solution and H ₂ O is 1:10-20:1, the temperature is 25 degrees Celsius to 80 degrees Celsius, and the time is 2 minutes to 100 minutes.

Referring to FIG. 10 , after removing the sacrificial layer in the first dummy gate opening 109 and the second dummy gate opening 110 , the diffusion barrier layer 118 in the first dummy gate opening 109 is removed.

The process of removing the diffusion barrier layer 118 in the first dummy gate opening 109 includes one or a combination of a dry etching process and a wet etching process.

In this embodiment, the process of removing the diffusion barrier layer 118 in the first dummy gate opening is a wet etching process. The specific process parameters include: etching solution 1 and etching solution 2, etching solution 1 includes NH ₄ OH, H ₂ O ₂ and H ₂ O, and the volume relationship ratio of NH ₄ OH, H ₂ O ₂ and H ₂ O is ₅ : ₂₀₀ :1000, the temperature is 40 degrees Celsius; the etching solution ₂ includes HCl, H2O2 and _H2O , the volume relationship of HCl, H2O2 and _H2O is ₁ :1.5:100, the temperature is 50 Celsius.

Referring to FIG. 11 , after removing the diffusion barrier layer 118 in the first dummy gate opening 109 , before forming the N-type work function material layer, a P-type work function material is formed in the second dummy gate opening 110 Membrane 124 .

The method for forming the P-type work function material film 124 in the second dummy gate opening 110 includes: forming the P-type work function material film 124 in the first dummy gate opening 109 and the second dummy gate opening 110; The P work function material film 124 in the first dummy gate opening is described.

The P-type work function material film 124 is used for the subsequent formation of the P-type work function material layer. The material of the P-type work function material film 124 includes: thallium nitride or titanium nitride. In this embodiment, the material of the P-type work function material film 124 is titanium nitride, and correspondingly, the material of the subsequently formed P-type work function material layer is titanium nitride.

The formation process of the P work function material film 124 includes a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

In this embodiment, the process of forming the P work function material film 124 is an atomic layer deposition process. The specific process parameters are: providing an organic precursor material containing titanium, the temperature is 80 degrees Celsius to 300 degrees Celsius, the pressure is 5 mTorr to 20 Torr, and the number of cycles is 5 to 50 times.

The process of removing the P work function material film 124 in the first dummy gate opening includes one or a combination of a dry etching process and a wet etching process.

In this embodiment, the process of removing the P work function material film 124 in the first dummy gate opening is a wet etching process. The specific process parameters include: etching solution 1 and etching solution 2, etching solution 1 includes NH ₄ OH, H ₂ O ₂ and H ₂ O, and the volume relationship between NH ₄ OH, H ₂ O ₂ and H ₂ O is 5 : 200:1000, the temperature is 40 degrees Celsius; the etching solution 2 includes HCl, H ₂ O ₂ and H ₂ O, and the volume ratio of HCl, H ₂ O ₂ and H ₂ O is 1:1.5:100, and the temperature is 50 Celsius.

Referring to FIG. 12 , after the P-type work function material film 124 is formed in the second dummy gate opening, an N-type work function material film 125 is formed in the first dummy gate opening 109 and the second dummy gate opening 110 respectively. .

The N-type work function material film 125 is used for the subsequent formation of an N-type work function material layer. The material of the N-type work function material film 125 includes Al ions. The material of the N-type work function material film 125 includes one or more combinations of TiAl, TiAlC, TiAlN and AlN. In this embodiment, the material of the N-type work function material film 125 is TiAl, and correspondingly, the material of the N-type work function material layer formed subsequently is TiAl.

The formation process of the N-type work function material film 125 includes a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

In this embodiment, the formation process of the N-type work function material film 126 is an atomic layer deposition process. The specific process parameters include: providing an organic precursor material containing titanium and an organic precursor material containing Al, the temperature is 80 degrees Celsius to 500 degrees Celsius, the pressure is 2 millitorr to 200 torr, and the number of cycles is 5 to 100 times.

In this embodiment, after the metal silicide layer 122 is formed in the contact holes 123 of the first region A and the second region B, respectively, the metal silicide layer 122 is formed in the first dummy gate opening 109 and the second dummy gate opening 110 . The N-type work function material film 125, the N-type work function material film 125 is used for the subsequent formation of the N-type work function material layer. Therefore, the high temperature process of the third annealing process for forming the metal silicide layer 122 can be avoided. The substances in the N-type work function material layer have an influence, thereby reducing the diffusion of Al ions in the N-type work function material layer, and reducing the diffusion of Al ions in the N-type work function material layer in the NMOS transistor to the lower gate dielectric layer 117, The interface reliability of the gate dielectric layer 117 and the turn-on voltage of the semiconductor device can be improved, thereby improving the performance of the obtained semiconductor device.

Referring to FIG. 13 , after an N-type work function material film 125 is formed in the first dummy gate opening 109 and the second dummy gate opening 110 , the first dummy gate opening 109 and the second dummy gate opening 110 are filled with The metal material is filled to form the metal gate film 126 .

The metal gate film 126 is used to form a metal gate later. In this embodiment, the material of the metal gate film is tungsten. Correspondingly, the material of the subsequently formed metal gate is tungsten. In other embodiments, the material of the metal gate film includes: Al, Cu, Ag, Au, Ni, Ti, W, WN or WSi.

The formation process of the metal gate film includes a chemical vapor deposition process or a physical vapor deposition process.

Referring to FIG. 14 , the P-type work function material film 124 , the N-type work function material film 125 and the metal gate film 126 are planarized until the top surface of the protective layer 108 is exposed, respectively at the first dummy gate opening 109 An N-type work function material layer 128 and a metal gate 129 located on the surface of the N-type work function material layer 128 are formed in the second dummy gate opening 110, and a P-type work function material layer is also formed in the second dummy gate opening 127, located between the diffusion barrier layer 118 and the N-type work function material layer 128.

The process of planarizing the P-type work function material film 124 , the N-type work function material film 125 and the metal gate film 126 includes a chemical mechanical polishing process.

Correspondingly, an embodiment of the present invention further provides a semiconductor device formed by the above method.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.

Claims (13)

1. A method of forming a semiconductor device, comprising:

providing a substrate, wherein the substrate is provided with a pseudo gate structure and an interlayer dielectric layer, the pseudo gate structure and the interlayer dielectric layer cover part of the surface of the substrate, the interlayer dielectric layer covers the surface of the side wall of the pseudo gate structure, and source and drain doped regions are arranged in the substrate on two sides of the pseudo gate structure; the substrate comprises a first region and a second region; the first region is used for forming an N-type field effect transistor, and the second region is used for forming a P-type field effect transistor;

removing the pseudo gate structure, and forming a pseudo gate opening in the interlayer dielectric layer;

forming a contact hole in the interlayer dielectric layer, wherein the bottom of the contact hole is exposed out of the source drain doped region;

forming a metal silicide layer on the bottom surface of the contact hole;

after the metal silicide layer is formed, forming a conductive plug which is filled in the contact hole;

forming an N-type work function material layer in the dummy gate opening after the conductive plug is formed;

after forming the dummy gate opening and before forming the contact hole, further comprising: forming interface layers on the side wall and the bottom surface of the pseudo gate opening; forming a gate dielectric layer on the surface of the interface layer;

forming a diffusion barrier layer on the surface of the gate dielectric layer; after forming the diffusion barrier layer and before forming the contact hole, the method further comprises: forming sacrificial structures in the dummy gate openings of the first region and the dummy gate openings of the second region, wherein the sacrificial structures fill the dummy gate openings of the first region and the dummy gate openings of the second region; the sacrificial structure comprises a first sacrificial layer and a second sacrificial layer positioned on the surface of the first sacrificial layer; the first sacrificial layer covers the side walls and the bottom surfaces of the dummy gate openings of the first region and the second region; the second sacrificial layer is positioned on the surface of the first sacrificial layer; performing a first annealing process after forming the first sacrificial layer;

after the forming of the conductive plug and before the forming of the N-type work function material layer, the method further includes: removing the second sacrificial layer in the dummy gate opening of the first region and the dummy gate opening of the second region; after removing the second sacrificial layer, removing the first sacrificial layer in the dummy gate opening of the first region and the dummy gate opening of the second region; removing the diffusion barrier layer in the dummy gate opening of the first region after removing the sacrificial structure in the dummy gate opening of the first region and the dummy gate opening of the second region; forming a P-type work function material layer in the dummy gate opening of the second region, and forming an N-type work function material layer after the P-type work function material layer is formed; the material of the second sacrificial layer comprises silicon oxide.

2. The method for forming a semiconductor device according to claim 1, wherein the contact hole is formed after the dummy gate opening is formed.

3. The method of forming a semiconductor device of claim 2, wherein forming the gate dielectric layer comprises performing a fourth annealing process.

4. The method for forming a semiconductor device according to claim 3, wherein the dummy gate structures are respectively located on a substrate surface of the first region and a substrate surface of the second region; the source-drain doped region is respectively positioned in the substrate of the first region and the substrate of the second region; the contact holes are respectively positioned in the interlayer dielectric layer of the first area and the interlayer dielectric layer of the second area; the N-type work function material layer is respectively positioned in the dummy gate opening of the first area and the dummy gate opening of the second area.

5. The method for forming a semiconductor device according to claim 4, wherein a material of the first sacrificial layer comprises amorphous silicon, polycrystalline silicon, or single crystal silicon.

6. The method for forming a semiconductor device according to claim 4, wherein an annealing temperature of the first annealing process is 800 degrees Celsius to 1000 degrees Celsius.

7. The method for forming a semiconductor device according to claim 4, wherein a second annealing process is performed after the sacrificial structure is formed; the annealing temperature of the second annealing process is 800-1000 ℃.

8. The method for forming a semiconductor device according to claim 1, wherein the method for forming the metal silicide layer comprises: depositing a metal layer on the side wall and the bottom surface of the contact hole; carrying out a third annealing process to enable the metal layer to react with the surface of the source drain doped region to form a metal silicide layer; the third annealing process is a laser annealing process, and the annealing temperature is 750-900 ℃.

9. The method for forming a semiconductor device according to claim 8, wherein a material of the metal silicide layer includes: a titanium silicon compound.

10. The method for forming a semiconductor device according to claim 4, wherein a material of the P-type work function material layer comprises titanium nitride or tantalum nitride.

11. The method of forming a semiconductor device according to claim 1, wherein a material of the N-type work function material layer includes one or a combination of TiAl, TiAlC, TiAlN, and AlN.

12. The method of forming a semiconductor device according to claim 1, further comprising, after forming an N-type work function material layer within the dummy gate opening: and filling metal materials in the dummy gate opening to form a metal gate.

13. A semiconductor device formed by a method using the semiconductor device according to any one of claims 1 to 12.

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