CN110634946B - Enhanced heterogeneous metal gate AlGaN/GaN MOS-HEMT device and preparation method thereof - Google Patents

Abstract

The invention discloses an enhanced heterogeneous metal gate AlGaN/GaN MOS-HEMT device and a preparation _method thereof, comprising: an AlN transition layer located on an _Al2O3 substrate; a multi-layered AlN transition layer located on the AlN transition layer layer buffer structure; an AlGaN barrier layer on the multi-layer buffer structure; a GaN cap layer on the AlGaN barrier layer; on the first GaN layer and upwardly through the AlGaN barrier layer and the GaN cap The source and drain of the layer; the gate oxide layer on the GaN cap layer, the source and the drain; the heterogeneous gate structure on the gate oxide layer. The invention can increase the channel driving current, can flexibly adjust the threshold voltage, and can prevent the deterioration of the channel carrier mobility.

Description

An enhanced heterogeneous metal gate AlGaN/GaN MOS-HEMT device and its preparation method

technical field

The invention belongs to the technical field of AlGaN/GaN HEMT devices, and in particular relates to an enhanced heterogeneous metal gate AlGaN/GaN MOS-HEMT device and a preparation method thereof.

Background technique

The traditional semiconductor materials represented by silicon (Si) and gallium arsenide (GaAs) have gradually failed to meet the development of modern electronic technology under the requirements of radiation resistance, high temperature, high voltage and high power. Wide bandgap semiconductor GaN electronic devices can be used in high temperature, high voltage, high frequency and harsh environments, such as radar and wireless communication base stations and satellite communications. Due to its wide band gap, high breakdown voltage, high electron saturation drift velocity, excellent electrical and optical properties, and good chemical stability, GaN is favored in high-frequency, high-power, high-temperature electronic devices. The wide application of GaN devices heralds the coming of the era of optoelectronic information and even photon information. Today, microelectronic devices are developing exponentially, and GaN devices have been widely used in both military and civilian applications.

As the single heterojunction growth process and mechanism research of AlGaN/GaN continues to mature, the performance of AlGaN/GaN HEMT devices, which are the main structure of GaN-based HEMTs, has also been continuously improved. From 1993 to the end of the last century, the mechanism driving the development of AlGaN/GaN HEMT is mainly the improvement of heterojunction performance, the gradual evolution and improvement of process technology (such as mesa etching, Schottky contact and ohmic contact), and the continuous maturity of heat treatment technology. Since 2000, the performance of ALGaN/GaN heterojunction materials has tended to be basically stable, and the improvement of ALGaN/GaN HEMT device performance mainly depends on the improvement of the process level and the improvement of the device structure. From the perspective of device design and application, traditional GaN-based HEMTs are depletion mode (normally open), but power electronic equipment should adopt enhancement mode (normally closed), because this can greatly reduce the The difficulty of integrated circuit design.

Although the industry has made a lot of efforts to improve the device structure of the enhanced AlGaN/GaN HEMT, the effect is not ideal in practical applications, and the conventional AlGaN/GaN HEMT has inherent technical defects. For example, conventional concave gate HEMT devices are difficult to manufacture, the process repeatability is poor, and the uniformity of threshold voltage is not good; the use of fluorine ion implantation or plasma treatment usually causes damage and creates defects in the semiconductor material, thereby reducing the current carrying capacity. submobility, etc.

Contents of the invention

Aiming at the deficiencies in the prior art, the present invention provides an enhanced heterogeneous metal gate AlGaN that can increase the channel drive current, flexibly adjust the threshold voltage, and prevent the deterioration of channel carrier mobility. /GaN MOS-HEMT device and its fabrication method.

An enhanced heterogeneous metal gate AlGaN/GaN MOS-HEMT device, comprising:

An AlN transition layer on the Al2O3 substrate;

a multi-layer buffer structure located on the AlN transition layer, the uppermost layer of the multi-layer buffer structure is a first GaN layer;

an AlGaN barrier layer located on the first GaN layer, the thickness of the AlGaN barrier layer is 5 nm to 10 nm;

a GaN cap layer located above the AlGaN barrier layer;

a source electrode and a drain electrode located on the first GaN layer and upwardly passing through the AlGaN barrier layer and the GaN cap layer;

a gate oxide layer over the GaN cap layer, source and drain;

A heterogeneous gate structure located on the gate oxide layer, the heterogeneous gate structure includes two metal gates with different work functions arranged in parallel in contact with each other;

The multi-layer buffer structure includes:

a GaN buffer layer located above the AlN transition layer;

a low temperature GaN buffer layer located on the GaN buffer layer;

the first GaN layer overlying the low temperature GaN buffer layer;

Wherein, the low temperature is 300-400°C.

Further, the tops of the source and the drain are higher than the GaN cap layer.

A preparation method for an enhanced heterogeneous metal gate AlGaN/GaN MOS-HEMT device, comprising:

Step 1: Nitriding the upper surface of the cleaned Al2O3 substrate to form an AlN transition layer;

Deposit and grow a multi-layer buffer structure on the AlN transition layer, the uppermost layer of the multi-layer buffer structure is a first GaN layer; grow a 5-10nm AlGaN barrier layer on the first GaN layer; growing a GaN cap layer on the barrier layer;

Step 2: spin-coating a positive photoresist on the GaN cap layer, and exposing the source and drain regions by photolithography;

Step 3: forming holes for preparing source and drain electrodes by etching to the first GaN layer;

Step 4: Deposit metal at the position of the hole to obtain a metallized source and drain to form an ohmic contact; after removing the photoresist and excess metal in the gate area, etch the GaN cap layer to 1~2nm;

Step 5: Perform high-temperature annealing treatment in a nitrogen atmosphere; deposit and grow a layer of silicon dioxide as a gate oxide layer at room temperature;

Step 6: Spin-coat positive photoresist on the gate oxide layer, and expose the gate region by photolithography;

Step 7: Depositing and growing the first gate metal layer, covering the first gate metal layer with a positive photoresist as a protective layer, exposing the preset second gate metal region by photolithography, and then etching removing the first gate metal layer located in the second gate metal region;

Step 8: Depositing and growing a second gate metal layer with the same thickness as the first gate metal layer on the surface of the device, etching off all the redundant parts of the two metals and the remaining photoresist and performing chemical mechanical polishing, so that The planar arrangement of two metal gates forms a heterogeneous gate structure;

Step 9: Coating positive photoresist around the heterogeneous gate structure, and etching away the gate oxide layers on both sides of the heterogeneous gate structure;

Step 10: Remove the photoresist around the heterogeneous gate structure to expose the metal gate;

The deposition and growth multilayer buffer structure described in step 1 includes:

Depositing and growing a GaN buffer layer on the AlN transition layer at a growth temperature of 600-800°C;

Depositing and growing a low-temperature GaN buffer layer on the GaN buffer layer at a growth temperature of 300-400°C;

The first GaN layer is deposited and grown on the low-temperature GaN buffer layer at a constant temperature of 700°C.

In particular, etching away the gate oxide layers on both sides of the heterogeneous gate structure in step nine refers to:

The gate oxide layer on both sides of the heterogeneous gate structure is wet etched by hydrogen fluoride solution, or the gate oxide layer on both sides of the heterogeneous gate structure is plasma etched by argon plasma.

In particular, as described in step five, a silicon dioxide layer is deposited and grown at room temperature as a gate oxide layer, and the refractive index of the silicon dioxide layer reaches 1.5 by using a plasma-enhanced chemical vapor deposition technique.

Compared with the prior art, the present invention has the following beneficial effects:

1. By setting an AlGaN barrier layer whose thickness is much smaller than the critical thickness of AlGaN, the ability to confine 2DEG is improved, and the surface density and channel drive current of 2DEG are improved;

2. By designing a GaN cap layer under the gate oxide layer above the AlGaN barrier layer, it not only increases the physical distance between the device surface and 2DEG, reduces interface scattering, and avoids roughness of the device surface The deterioration of the channel carrier mobility by scattering can further reduce the gate leakage current;

3. By setting a heterogeneous gate structure composed of two metal gates with different work functions arranged side by side in contact with each other, it can not only overcome the inherent technical defects of the conventional concave gate AlGaN/GaN HEMT, but also simplify the manufacturing process of the device process to improve the electrical characteristics of the device; it is also possible to flexibly design the difference between the work function of the two metals and the work function of the GaN cap layer, and the channel lengths corresponding to the gates of the two metals. Different channel potential distributions are introduced into the 2DEG channel at , and then the threshold voltage of the device is adjusted;

4. By setting a multi-layer buffer structure composed of a high-temperature GaN buffer layer, a low-temperature GaN buffer layer, and a constant temperature GaN layer (the first GaN layer) on the substrate, the defect density on the surface is the same as that of traditional sapphire or silicon carbide (SiC ) is greatly reduced compared to the GaN substrate grown on it, which can effectively improve the reliability of the device;

5. By making the source and drain protrude from the surface of the device, a surrounding electrode is formed, which is beneficial to adjust the threshold voltage of the device; it also reduces the junction capacitance of the source and drain regions without reducing the preferred value .

6. By using the MOS structure, it is compatible with the mainstream compound semiconductor process and CMOS process, and the structure is simple; compared with traditional GaN HEMT devices, the number of material layers is reduced, the substrate quality is better, the process repeatability is high, and it is easy to large-scale manufacture.

Description of drawings

Fig. 1 is the structural representation after step 1 of the preparation method of the present invention;

Fig. 2 is a structural schematic diagram after step 2 of the preparation method of the present invention;

Fig. 3 is a structural schematic diagram after step 3 of the preparation method of the present invention;

Fig. 4 is a structural schematic diagram after step 4 of the preparation method of the present invention;

Fig. 5 is a schematic structural view after step five of the preparation method of the present invention;

Fig. 6 is a schematic structural diagram after step six of the preparation method of the present invention;

Fig. 7 is a schematic structural diagram after step 7 of the preparation method of the present invention;

Fig. 8 is a schematic structural diagram after step 8 of the preparation method of the present invention;

Fig. 9 is a schematic structural diagram after step nine of the preparation method of the present invention;

Fig. 10 is a structural schematic diagram of the device of the present invention;

Among them, 1-Al2O3 substrate, 2-AlN transition layer, 3-multilayer buffer structure, 31-GaN buffer layer, 32-low temperature GaN buffer layer, 33-first GaN layer, 4-AlGaN barrier layer, 5-GaN cap layer, 6-gate oxide layer, 71-first gate metal layer, 72-second gate metal layer, 8-photoresist.

Detailed ways

In order to make the technical means, creative features, goals and effects of the invention easy to understand, the present invention will be further elaborated below in conjunction with specific illustrations.

An enhanced heterogeneous metal gate AlGaN/GaN MOS-HEMT device, as shown in Figure 10, includes:

An AlN transition layer 2 located on the Al ₂ O ₃ substrate 1;

A multi-layer buffer structure 3 located on the AlN transition layer 2, the uppermost layer of the multi-layer buffer structure 3 is a first GaN layer 33;

An AlGaN barrier layer 4 located on the first GaN layer 33, the thickness of the AlGaN barrier layer 4 is 5-10 nm;

a GaN cap layer 5 located on the AlGaN barrier layer 4;

a source and a drain located on the first GaN layer 33 and upwardly passing through the AlGaN barrier layer 4 and the GaN cap layer 5;

a gate oxide layer 6 located on the GaN cap layer 5, source and drain;

A heterogeneous gate structure located on the gate oxide layer 6 , the heterogeneous gate structure includes two kinds of metal gates with different work functions that are arranged side by side in contact with each other.

The composition of Al in the AlGaN barrier layer may be 0.2-0.3, and its thickness is preferably 5 nm. The thickness of the GaN cap layer may be 1-2 nm. The ohmic contacts of the source and drain can be selected from titanium, aluminum, nickel and gold, and the typical deposition or etching thicknesses of the four metals can be 30nm, 180nm, 40nm and 100nm respectively. The multi-layer buffer structure means that there are at least two buffer layers therein. The heterogeneous gate structure in the present invention is not limited to two kinds of metal gates with different work functions, and three or more kinds of metal gates can also be arranged side by side.

First, the thickness of the AlGaN barrier layer is much smaller than the critical thickness of AlGaN, which can better form a two-dimensional electron gas (2DEG) at the interface of the AlGaN/GaN heterojunction close to the GaN surface. This scheme utilizes a very thin AlGaN barrier layer, which improves the ability to confine 2DEG, and improves the area density and channel driving current of 2DEG. Second, since the 2DEG at the ALGaN/GaN heterojunction interface is very close to the surface of GaN, and the thickness of the AlGaN barrier layer is very thin, the 2DEG is easily affected by the scattering effect of the interface state and surface roughness of the upper surface of AlGaN near the gate. Under low temperature conditions, the carrier mobility of 2DEG is greatly reduced, and the electrical performance of the device will be adversely affected; for this reason, a GaN cap layer is designed on the AlGaN barrier layer, which increases the distance between the device surface and 2DEG. The physical distance between them reduces interface scattering. In addition, the cap layer can further reduce the gate leakage current. Thirdly, by setting a heterogeneous gate structure composed of two metal gates with different work functions arranged side by side in contact with each other, this scheme can not only overcome the inherent technical defects of conventional concave gate AlGaN/GaN HEMTs, but also simplify the device design. The manufacturing process can improve the electrical characteristics of the device. It is also possible to flexibly design the difference between the work function of the two metals and the work function of the GaN cap layer, and the channel lengths corresponding to the two metal gates. Different channel potential distributions are introduced into the 2DEG channel at the junction interface to adjust the device threshold voltage. There are many possibilities for the selection of heterogeneous gate metals and the ratio of channel lengths, which can improve the design freedom of devices and circuits.

As an optimized solution, the multi-layer buffer structure includes:

a GaN buffer layer 31 located on the AlN transition layer 2;

a low-temperature GaN buffer layer 32 located on the GaN buffer layer 31;

The first GaN layer 33 located on the low-temperature GaN buffer layer 32 .

In this solution, a metal organic chemical vapor deposition (MOCVD) method is adopted, the growth temperature of the GaN buffer layer may be 600-800°C, the growth temperature of the low-temperature GaN buffer layer may be 300-400°C, and the first The growth temperature of the GaN layer may be a constant temperature of 700°C.

In this scheme, a high-temperature GaN buffer layer is first grown on an Al ₂ O ₃ substrate, and then a low-temperature GaN buffer layer is grown on top of the GaN buffer layer, and finally a GaN layer is grown under constant temperature conditions, and this layer is used as an AlGaN/GaN Compared with the traditional GaN substrate grown on sapphire or silicon carbide (SiC), the defect density on the surface of the actual HEMT substrate is greatly reduced, which can effectively improve the reliability of the device.

As an optimized solution, the tops of the source and drain are higher than the GaN cap layer 5 .

In this solution, the source and drain protrude from the surface of the device, forming a surrounding electrode, which is beneficial to adjust the threshold voltage of the device. First, the source and drain metals are on the same plane as the GaN cap layer during preparation. Since the GaN cap layer needs to be etched and thinned in the process, and it is not desired to reduce the preferred value of the source and drain metal, the source The drain protrudes beyond the GaN cap layer. Secondly, the thickness of the source-drain metal is equal to the sum of the protruding part and the embedded part, which not only does not reduce the preferred value, but also reduces the junction capacitance of the source-drain region.

The present invention also discloses a method for preparing an enhanced heterogeneous metal gate ALGaN/GaN MOS-HEMT device, as shown in Figure 1-10, including:

Step 1: Nitriding the upper surface of the cleaned Al ₂ O ₃ substrate 1 to form an AlN transition layer 2;

Depositing and growing a GaN buffer layer 31 on the AlN transition layer 2 at a growth temperature of 600-800°C;

Depositing and growing a low-temperature GaN buffer layer 32 on the GaN buffer layer 31 at a growth temperature of 300-400°C;

Depositing and growing a first GaN layer 33 on the low-temperature GaN buffer layer 32 at a constant temperature of 700°C;

growing an AlGaN barrier layer 4 of 5-10 nm on the first GaN layer 33;

growing a 20nm GaN cap layer 5 on the AlGaN barrier layer 4;

Step 2: spin-coat positive photoresist 8 on the GaN cap layer 5, and expose the source and drain regions (defining the channel region) by photolithography;

Step 3: forming holes for preparing source and drain electrodes by etching to the first GaN layer 33;

Step 4: Deposit metal at the position of the hole to obtain a metallized source and drain to form an ohmic contact; after removing the photoresist 8 and excess metal in the gate region, etch the GaN cap layer 5 to 1 to 2nm;

Step 5: performing high-temperature annealing treatment in a nitrogen atmosphere; depositing and growing a silicon dioxide layer as a gate oxide layer 6 at room temperature;

Step 6: Spin-coat positive photoresist 8 on the gate oxide layer 6, and expose the gate region (defining the gate active region) by photolithography;

Step 7: Depositing and growing the first gate metal layer 71 (the gate metal is usually preferably titanium or gold), covering the first gate metal layer 71 with a positive photoresist 8 as a protective layer, and exposing the preliminary gate metal layer 71 by photolithography. The second gate metal region is provided, and then the first gate metal layer 71 located in the second gate metal region is removed by etching;

Step 8: Deposit and grow a second gate metal layer 72 with the same thickness as the first gate metal layer 71 on the surface of the device, etch away all the redundant parts of the two metals and the remaining photoresist 8 and perform chemical mechanical Polishing, so that the two metal gates are arranged planarly to form a heterogeneous gate structure;

Step 9: Coating positive photoresist 8 around the heterogeneous gate structure, and etching away the gate oxide layers on both sides of the heterogeneous gate structure;

Step 10: removing the photoresist 8 around the heterogeneous gate structure to expose the metal gate.

In step 1, the Al ₂ O ₃ substrate is cleaned by chemical cleaning, excess oxides are removed, dried and cleaved,

The cleaved substrate is further cleaned with hydrogen plasma, and nitrogen plasma is added into the reaction chamber to nitride the surface of the Al ₂ O ₃ substrate to form an AlN transition layer. On the transition layer, a thicker intrinsic GaN buffer layer of about 2 μm can be formed by metal-organic chemical vapor deposition (MOCVD), and the growth temperature is controlled at 600-800°C; then continue to grow the second intrinsic GaN layer at low temperature. The GaN buffer layer has a thickness of about 1 μm, and the growth temperature is controlled at 300-400 °C; finally, a GaN substrate with a thickness of about 2 μm is grown at a constant temperature of 700 °C, and a thin layer of AlGaN is grown on the substrate as a barrier layer , and its thickness may be 5-10 nm.

The etching depth in step three is determined by the metal material selected for the ohmic contact. The source and drain ohmic contacts can be selected from titanium, aluminum, nickel and gold, and the typical deposition or etching thicknesses of the four metals are 30nm, 180nm, 40nm and 100nm respectively; for example, if the source and drain are selected For aluminum, the etching depth of the source and drain regions is 180nm.

The annealing temperature in step five may be 800° C., and the annealing time may be 30 seconds. The deposition and growth of a layer of silicon dioxide at room temperature as the gate oxide layer may use plasma-enhanced chemical vapor deposition technology. The layer of silicon dioxide has a refractive index of 1.5 and a thickness of 10 nm. Since the refractive index of ordinary silicon dioxide is generally between 1.1-1.2, and the refractive index is related to the uniformity, the refractive index required to reach 1.5 in this scheme can make the silicon dioxide film have higher uniformity and density , and smaller interface states.

The protective layer is provided in step seven to ensure that the remaining part of the first gate metal layer is not affected by the process when the second gate metal layer is deposited. According to the channel length corresponding to the designed second gate metal layer, a corresponding length L2 is etched in the first gate metal layer, and the length of the remaining first metal gate is L1. If the channel length between the source and the drain is set as L, it is necessary to satisfy L1+L2=L.

The etching in Step 9 may be carried out by wet etching the gate oxide layer on both sides of the heterogeneous gate structure through hydrogen fluoride solution, or by plasma etching by argon plasma.

For example, if titanium (Ti) is selected for the first gate metal layer, gold (Au) can be selected for the second gate metal layer, the work function of titanium is 4.33eV, and the work function of gold is 5.1eV. There is a significant difference in the work function of the two.

The invention adopts MOS structure, which is compatible with the mainstream compound semiconductor process and CMOS process, and has a simple structure; compared with traditional GaN HEMT devices, the number of material layers is reduced, the substrate quality is better, the process repeatability is high, and it is easy to manufacture on a large scale .

The above descriptions are only preferred implementations of the present invention, and the scope of protection of the present invention is not limited to the above-mentioned implementations. All technical solutions belonging to the principle of the present invention belong to the scope of protection of the present invention. For those skilled in the art, some improvements made without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims (5)

1. An enhanced heterogeneous metal gate AlGaN/GaN MOS-HEMT device is characterized in that, comprising: An AlN transition layer on top of the Al ₂ O ₃ substrate; a multi-layer buffer structure located on the AlN transition layer, the uppermost layer of the multi-layer buffer structure is a first GaN layer; an AlGaN barrier layer located on the first GaN layer, the thickness of the AlGaN barrier layer is 5 nm to 10 nm; a GaN cap layer located above the AlGaN barrier layer; a source electrode and a drain electrode located on the first GaN layer and upwardly passing through the AlGaN barrier layer and the GaN cap layer; a gate oxide layer over the GaN cap layer, source and drain; A heterogeneous gate structure located on the gate oxide layer, the heterogeneous gate structure includes two metal gates with different work functions arranged in parallel in contact with each other; The multi-layer buffer structure includes: a GaN buffer layer located above the AlN transition layer; a low temperature GaN buffer layer located on the GaN buffer layer; the first GaN layer overlying the low temperature GaN buffer layer; Wherein, the low temperature is 300-400°C. 2. A kind of enhanced heterogeneous metal gate AlGaN/GaN MOS-HEMT device according to claim 1, is characterized in that: The source and drain tops are higher than the GaN cap layer. 3. A method for preparing an enhanced heterogeneous metal gate AlGaN/GaN MOS-HEMT device, characterized in that it comprises: Step 1: Nitriding the upper surface of the cleaned Al ₂ O ₃ substrate to form an AlN transition layer; Deposit and grow a multi-layer buffer structure on the AlN transition layer, the uppermost layer of the multi-layer buffer structure is a first GaN layer; grow a 5-10nm AlGaN barrier layer on the first GaN layer; growing a GaN cap layer on the barrier layer; Step 2: spin-coating a positive photoresist on the GaN cap layer, and exposing the source and drain regions by photolithography; Step 3: forming holes for preparing source and drain electrodes by etching to the first GaN layer; Step 4: Deposit metal at the position of the hole to obtain a metallized source and drain to form an ohmic contact; after removing the photoresist and excess metal in the gate area, etch the GaN cap layer to 1~2nm; Step 5: Perform high-temperature annealing treatment in a nitrogen atmosphere; deposit and grow a layer of silicon dioxide as a gate oxide layer at room temperature; Step 6: Spin-coat positive photoresist on the gate oxide layer, and expose the gate region by photolithography; Step 7: Depositing and growing the first gate metal layer, covering the first gate metal layer with a positive photoresist as a protective layer, exposing the preset second gate metal region by photolithography, and then etching removing the first gate metal layer located in the second gate metal region; Step 8: Depositing and growing a second gate metal layer with the same thickness as the first gate metal layer on the surface of the device, etching off all the redundant parts of the two metals and the remaining photoresist and performing chemical mechanical polishing, so that The planar arrangement of two metal gates forms a heterogeneous gate structure; Step 9: Coating positive photoresist around the heterogeneous gate structure, and etching away the gate oxide layers on both sides of the heterogeneous gate structure; Step 10: Remove the photoresist around the heterogeneous gate structure to expose the metal gate; The deposition and growth multilayer buffer structure described in step 1 includes: Depositing and growing a GaN buffer layer on the AlN transition layer at a growth temperature of 600-800°C; Depositing and growing a low-temperature GaN buffer layer on the GaN buffer layer at a growth temperature of 300-400°C; The first GaN layer is deposited and grown on the low-temperature GaN buffer layer at a constant temperature of 700°C. 4. A method for manufacturing an enhanced heterogeneous metal gate AlGaN/GaN MOS-HEMT device according to claim 3, characterized in that in step 9, the gate oxide on both sides of the heterogeneous gate structure is etched away. Layer means: The gate oxide layer on both sides of the heterogeneous gate structure is wet etched by hydrogen fluoride solution, or the gate oxide layer on both sides of the heterogeneous gate structure is plasma etched by argon plasma. 5. A method for preparing an enhanced heterogeneous metal gate AlGaN/GaN MOS-HEMT device according to claim 3, characterized in that: in step five, a silicon dioxide layer is deposited and grown at room temperature as the gate The oxide layer adopts plasma-enhanced chemical vapor deposition technology, and the refractive index of the silicon dioxide layer reaches 1.5.

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