CN110634876B - Method for manufacturing flash memory device - Google Patents
Method for manufacturing flash memory device Download PDFInfo
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- CN110634876B CN110634876B CN201910938087.XA CN201910938087A CN110634876B CN 110634876 B CN110634876 B CN 110634876B CN 201910938087 A CN201910938087 A CN 201910938087A CN 110634876 B CN110634876 B CN 110634876B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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Abstract
The application discloses a method for manufacturing a flash memory device, which comprises the following steps: providing a substrate, wherein the substrate comprises an active region, a grid is formed on the active region, and the grid comprises a control grid; carrying out nitridation treatment on the grid and the substrate to change the side surface activity of the control grid; and an organic medium layer is filled between the control gates. According to the method, in the manufacturing process of the flash memory device, after the grid electrode is formed on the substrate, the substrate and the grid electrode are subjected to nitriding treatment, the organic medium layer is filled in the gap between the control gates, and the activity of the side surface of the control gate is changed after the control gate is subjected to nitriding treatment, so that the deformation of the control gate caused by bubble residue due to the fact that the organic medium layer is filled can be reduced to a certain extent, and the yield of the flash memory device is improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor manufacturing technologies, and in particular, to a method for manufacturing a flash memory device.
Background
A Flash Memory (Nand-Flash, hereinafter referred to as "Flash Memory") is a Memory using a Non-volatile Memory (NVM) technology, and is currently widely used in electronic products with a storage function, such as smart phones, tablet computers, digital cameras, Universal Serial Bus Flash disks (USB Flash disks, simply referred to as "USB disks"), and the like. The flash memory is mainly characterized in that: the capacity is relatively large, the rewriting speed is high, the method is suitable for storing a large amount of data, and the data can be still stored after power failure, so that the method is more and more widely applied.
A gate of a flash memory device includes a Control Grid (CG), and in a manufacturing process of the flash memory device, after the Control gate is etched, an Organic Dielectric Layer (ODL) is required to be filled in a gap between the Control gates for the purpose of protecting the Control gate.
However, in the process of filling the gap between the control gates with the organic dielectric layer, bubbles usually remain to cause lateral deformation of the control gates, thereby resulting in a low yield of the flash memory device.
Disclosure of Invention
The application provides a manufacturing method of a flash memory device, which can solve the problem that the manufacturing method of the flash memory device provided by the related technology easily causes lateral deformation of a control gate.
In one aspect, an embodiment of the present application provides a method for manufacturing a flash memory device, including:
providing a substrate, wherein the substrate comprises an active area, a grid electrode is formed on the active area, and the grid electrode comprises a control grid;
performing nitridation treatment on the grid and the substrate to change the side surface activity of the control grid;
and filling organic dielectric layers on the surfaces of the grid and the substrate, so that the organic dielectric layers are filled between the control grids.
Optionally, the processing temperature of the nitridation processing is 600 to 1000 ℃.
Optionally, the time of the nitriding treatment is 30 seconds to 1 minute.
Optionally, when the gate and the substrate are subjected to the nitridation treatment, the flow rate of the introduced nitrogen gas is greater than 60 standard milliliters/minute.
Optionally, before performing the nitridation process on the gate and the substrate, the method further includes:
generating a multilayer film structure on the substrate;
covering the area of the grid electrode on the surface of the multilayer film structure through a photoetching process;
and etching other areas of the multilayer film structure except the area where the grid is located to form the grid.
Optionally, the multilayer film structure sequentially includes an oxide layer, a first polysilicon layer, a dielectric layer, a second polysilicon layer, a spacer layer, and a hard mask layer along a direction from the substrate to the gate;
the second polysilicon layer forms the control gate after passing through the etch.
Optionally, the oxide layer includes a first silicon oxide layer, the spacer layer includes a silicon nitride layer, and the dielectric layer includes an ONO dielectric layer.
Optionally, the hard mask layer includes a second silicon dioxide layer.
Optionally, the height of the organic dielectric layer is higher than that of the gate electrode.
Optionally, after the organic dielectric layer is filled on the surfaces of the gate and the substrate, the method further includes:
removing the organic dielectric layer for the first time to expose the second silicon dioxide layer without exposing the ONO dielectric layer;
removing the second silicon dioxide layer on the top of the grid for the second time;
and removing the organic medium layer on the surfaces of the substrate and the grid electrode for the third time.
Optionally, the removing the organic dielectric layer for the first time includes:
and removing the organic medium layer for the first time by a dry etching process.
Optionally, the reaction gas of the dry etching process includes oxygen.
Optionally, the third removing the organic dielectric layer on the substrate and the surface of the gate includes:
and removing the organic medium layer on the surfaces of the substrate and the grid electrode for the third time by a wet etching process.
Optionally, the reaction solution of the wet etching process includes hydrogen fluoride.
Optionally, the active region includes a memory cell region and a peripheral circuit region.
The technical scheme at least comprises the following advantages:
in the manufacturing process of the flash memory device, after the grid electrode is formed on the substrate, the substrate and the grid electrode are subjected to nitridation treatment, the organic medium layer is filled in the gap between the control gates, and the activity of the side surfaces of the control gates is changed after the nitridation treatment, so that the deformation of the control gates caused by bubble residues caused by filling the organic medium layer can be reduced to a certain extent, and the yield of the flash memory device is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the embodiments or the technical solutions in the prior art are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained according to the drawings without creative efforts for those skilled in the art.
Fig. 1 is a flow chart of a method of manufacturing a flash memory device provided in an exemplary embodiment of the present application;
fig. 2 to 5 are schematic diagrams illustrating a method for manufacturing a flash memory device according to an exemplary embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or the two elements may be communicated with each other, or the two elements may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Fig. 2 to 5 are schematic diagrams of a method for manufacturing a flash memory device according to an exemplary embodiment of the present application, where fig. 2 and 4 are cross-sectional views of a memory cell region of the flash memory device, and fig. 3 and 5 are cross-sectional views of a peripheral circuit region of the flash memory device. In this application, a direction in which the thickness of the substrate is defined is a Z axis, a direction in which the length of the gate electrode on a plane in which the substrate is located is a Y axis, and a direction perpendicular to the Y axis on the plane in which the substrate is located is an X axis.
Example 1:
referring to fig. 1, a flow chart of a method for manufacturing a flash memory device according to an exemplary embodiment of the present application is shown, the method including:
And 102, performing nitridation treatment on the grid and the substrate to change the side surface activity of the control grid.
And 103, filling organic dielectric layers on the surfaces of the grid electrode and the substrate, so that the organic dielectric layers are filled between the control grid electrodes.
In summary, in the embodiment, in the manufacturing process of the flash memory device, after the gate electrode is formed on the substrate, the substrate and the gate electrode are subjected to nitridation processing, and the gap between the control gates is filled with the organic dielectric layer, because the control gates are subjected to nitridation processing and the activity of the side surfaces of the control gates is changed, the deformation of the control gates caused by the bubble residue caused by filling the organic dielectric layer can be reduced to a certain extent, and the yield of the flash memory device is improved.
Referring to fig. 2 and 3, in step 101, a substrate 210 includes an active region 201, the active region 201 is formed with a gate 220, and the gate 220 includes a control gate 223. Illustratively, the substrate 210 is a Silicon substrate, or alternatively, the substrate 210 is a Silicon-On-Insulator (SOI).
Referring to fig. 4 and 5, after step 102 is performed, an organic dielectric layer 202 is filled between the control gates 223. The organic dielectric layer 202 is a material that does not react with hydrofluoric acid (HF) in the wet etching solution, and is filled by coating the surfaces of the substrate 210 and the gate electrode 220.
Example 2:
referring to example 1, fig. 4 and fig. 5, example 2 differs from example 1 in that: the organic dielectric layer 202 has a height higher than that of the gate electrode 220.
Example 3:
referring to example 1 and example 2, example 3 differs from the above examples in that: in step 102, the temperature of the nitridation process is 600 to 1000 ℃. Optionally, in this embodiment, the time of the nitridation treatment is 30 seconds to 1 minute; optionally, in this embodiment, nitrogen (N) is introduced when performing nitridation on the gate 220 and the substrate 2102) The flow rate of (2) is more than 60 standard milliliters per minute (sccm).
Example 4:
referring to examples 1 to 3, example 4 differs from the above examples in that: before step 101, further comprising: generating a multilayer film structure on a substrate; covering the area where the grid electrode on the surface of the multilayer film structure is located by a photoetching process; and etching the other areas of the multilayer film structure except the area where the grid electrode is located to form the grid electrode.
Example 5:
referring to example 4, example 5 differs from example 4 in that: the multilayer film structure sequentially includes an oxide layer, a first polysilicon layer, a dielectric layer, a second polysilicon layer, a spacer layer, and a hard mask layer along a substrate-to-Gate direction (i.e., a Z-axis direction in fig. 2 to 5), where the first polysilicon layer forms a Floating Gate (FG) after being etched, and the second polysilicon layer forms a control Gate after being etched.
Optionally, in this embodiment, the Oxide layer includes a first silicon Oxide layer, the spacer layer includes a silicon Nitride layer, and the dielectric layer includes an Oxide-Nitride-Oxide (ONO) dielectric layer; optionally, in this embodiment, the hard mask layer includes a second silicon dioxide layer.
Example 6:
referring to example 5, example 6 differs from example 5 in that: after step 103, further comprising: removing the organic dielectric layer for the first time to expose the second silicon dioxide layer without exposing the ONO dielectric layer; removing the second silicon dioxide layer on the top of the grid for the second time; and removing the organic medium layer on the surfaces of the substrate and the grid for the third time, so as to remove the residual organic medium layer.
Optionally, in this embodiment, the "removing the organic dielectric layer for the first time" includes: removing the organic medium layer for the first time by a dry etching process; optionally, the reaction gas of the dry etching process comprises oxygen (O)2)。
Optionally, in this embodiment, the "removing the organic dielectric layer on the surfaces of the substrate and the gate for the third time" includes: removing the organic medium layers on the surfaces of the substrate and the grid electrode for the third time through a wet etching process; optionally, the reaction solution of the wet etching process includes hydrogen fluoride.
Optionally, in the above embodiments, referring to fig. 2 to 5, the gate 220 sequentially includes a first silicon oxide layer 226, a floating gate 225, an ONO dielectric layer 224, a control gate 223, a silicon nitride layer 222, and a second silicon oxide layer 221 along the direction from the substrate 210 to the top end of the gate 220.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention as herein introduced are intended to be covered by the scope of protection of the present application.
Claims (13)
1. A method of manufacturing a flash memory device, comprising:
providing a substrate, wherein the substrate comprises an active area, a grid is formed on the active area, and the grid comprises a control grid;
performing nitridation treatment on the grid and the substrate to change the side surface activity of the control grid;
filling organic dielectric layers on the surfaces of the grid and the substrate, so that the organic dielectric layers are filled between the control gates, and the height of each organic dielectric layer is higher than that of the grid;
removing the organic dielectric layer for the first time to expose the second silicon dioxide layer of the grid electrode without exposing the ONO dielectric layer of the grid electrode, wherein the ONO dielectric layer is positioned below the second silicon dioxide layer;
removing the second silicon dioxide layer on the top of the grid for the second time;
and removing the organic medium layer on the surfaces of the substrate and the grid electrode for the third time.
2. The method of claim 1, wherein the nitridation process has a process temperature of 600 to 1000 degrees celsius.
3. The method according to claim 2, wherein the nitriding treatment is carried out for a period of 30 seconds to 1 minute.
4. The method of claim 3, wherein the flow rate of the introduced nitrogen gas is greater than 60 standard ml/min when the gate and the substrate are subjected to the nitridation process.
5. The method of any of claims 1 to 4, further comprising, prior to the nitridation processing of the gate and the substrate:
generating a multilayer film structure on the substrate;
covering the area of the grid electrode on the surface of the multilayer film structure through a photoetching process;
and etching other areas of the multilayer film structure except the area where the grid is located to form the grid.
6. The method of claim 5, wherein the multilayer film structure comprises an oxide layer, a first polysilicon layer, a dielectric layer, a second polysilicon layer, a spacer layer and a hard mask layer in sequence along the direction from the substrate to the gate;
the second polysilicon layer forms the control gate after passing through the etch.
7. The method of claim 6, wherein the oxide layer comprises a first silicon oxide layer, the spacer layer comprises a silicon nitride layer, and the dielectric layer comprises an ONO dielectric layer.
8. The method of claim 7, wherein the hard mask layer comprises a second silicon dioxide layer.
9. The method of claim 1, wherein the first removing the organic dielectric layer comprises:
and removing the organic medium layer for the first time by a dry etching process.
10. The method of claim 9, wherein the reactive gas of the dry etching process comprises oxygen.
11. The method of claim 1, wherein the third removing of the organic dielectric layer on the surface of the substrate and the gate electrode comprises:
and removing the organic medium layer on the surfaces of the substrate and the grid electrode for the third time by a wet etching process.
12. The method of claim 11, wherein the reaction solution of the wet etching process comprises hydrogen fluoride.
13. The method of any of claims 1 to 4, wherein the active region comprises a memory cell region and a peripheral circuit region.
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| CN201910938087.XA CN110634876B (en) | 2019-09-30 | 2019-09-30 | Method for manufacturing flash memory device |
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| CN110634876B true CN110634876B (en) | 2022-03-18 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20050064673A (en) * | 2003-12-24 | 2005-06-29 | 주식회사 하이닉스반도체 | Method of manufacturing a flash memory device |
| CN104157559A (en) * | 2013-05-14 | 2014-11-19 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method of control gate and manufacture method of floating gate |
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| KR100609942B1 (en) * | 2004-01-09 | 2006-08-08 | 에스티마이크로일렉트로닉스 엔.브이. | Manufacturing Method of Flash Memory Cell |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20050064673A (en) * | 2003-12-24 | 2005-06-29 | 주식회사 하이닉스반도체 | Method of manufacturing a flash memory device |
| CN104157559A (en) * | 2013-05-14 | 2014-11-19 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method of control gate and manufacture method of floating gate |
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