CN110620630A - Time synchronization method, device, network equipment and computer readable storage medium - Google Patents

Abstract

Embodiments of the present invention provide a time synchronization method, device, network equipment, and computer-readable storage medium. The processor first performs time synchronization on the system clock according to the time synchronization protocol, and after determining that the time synchronization of the system clock has reached a stable state, switches to The time synchronization chip continues to synchronize the system clock. Since the scheme in which the processor performs time synchronization according to the time synchronization protocol has the advantage of fast synchronization convergence speed, using this scheme at the beginning of time synchronization can quickly converge the time deviation between the local device and the master device. Since the time synchronization chip will fully suppress and filter the message data with the main device, after the time synchronization of the system clock reaches a stable state, the time synchronization chip will continue to perform time synchronization after the time synchronization chip, which can avoid network shocks, interference noise, etc. The impact of the time synchronization result, thereby improving the synchronization stability and synchronization accuracy of the system clock time synchronization.

Description

Time synchronization method, device, network device and computer-readable storage medium

technical field

The present invention relates to the communication field, in particular to a time synchronization method, device, network equipment and computer-readable storage medium.

Background technique

With the rise of 5G (5th Generation, fifth-generation mobile communication) network technology, and the promotion of 5G-related application requirements and clock technology standards, the IEEE (Institute of Electrical and Electronics Engineers, Institute of Electrical and Electronics Engineers) 1588 time synchronization protocol is Network clock time synchronization plays an important role. As an important backup of the GPS (Global Positioning System, Global Positioning System) time source, the 1588 clock provides a high-precision clock time synchronization function for the entire communication network, providing strong support and guarantee for the normal operation of network communication services.

In the prior art, the CPU of the network device can run the 1588 time synchronization protocol stack to interact with the master device so as to realize the synchronization of the system clock. However, since the path delay from the network device port to the CPU is uncertain, the accuracy of this time synchronization solution is not high. Moreover, considering the processing capability and processing speed of the CPU, generally no or only simple suppression filter processing is performed during time stamp calculation and processing. Therefore, this solution also has the disadvantages of being sensitive to network vibration and noise interference and having poor stability.

Therefore, there is an urgent need to provide a new time synchronization solution to solve the problems of low precision and poor stability of the existing time synchronization solution.

Contents of the invention

The time synchronization method, device, network equipment, and computer-readable storage medium provided by the embodiments of the present invention mainly solve the technical problem of providing a new time synchronization solution to solve the problem of low precision and poor stability of existing time synchronization solutions question.

In order to solve the above technical problems, an embodiment of the present invention provides a time synchronization method, including:

The processor performs time synchronization on the system clock according to the time synchronization protocol;

When it is determined that the time synchronization of the system clock has reached a stable state, the time synchronization chip is switched to continue time synchronization of the system clock.

Optionally, switching the synchronization chip to continue time synchronization of the system clock includes:

Control the system clock to output time to the time synchronization chip;

After the time synchronization chip locks the time of the system clock, the time synchronization chip is controlled to synchronize the time of the system clock, and stop the processor from synchronizing the time of the system clock.

Optionally, determining that the time synchronization of the system clock reaches a stable state includes:

It is determined that in K consecutive synchronization detections, the time deviation Δt between the device and the master device is smaller than the preset deviation ΔTh for N times, N and K are both positive integers greater than 0, and K is greater than or equal to N.

Optionally, N is equal to K.

Optionally, the time synchronization protocol is the precision clock synchronization protocol standard PTP of the network measurement and control system.

Optionally, after the control synchronization chip continues to perform time synchronization on the system clock, it also includes:

When the synchronization chip is in an abnormal state, the control processor continues to perform time synchronization on the system clock according to the time synchronization protocol.

The embodiment of the present invention also provides a time synchronization device, including:

The first synchronization module is configured to perform time synchronization on the system clock according to the time synchronization protocol;

A synchronous detection module is used to detect whether the time synchronization of the system clock reaches a stable state;

The second synchronization module is configured to switch the time synchronization chip to continue time synchronization of the system clock after determining that the time synchronization of the system clock has reached a stable state.

The embodiment of the present invention also provides a network device, including a processor, a memory, a time synchronization chip, a communication unit, and a communication bus;

The communication bus is used to realize the connection and communication between the processor and the memory, the time synchronization chip and the communication unit;

The processor is used to execute one or more programs stored in the memory, so as to realize the steps of any one of the above time synchronization methods.

Optionally, the time synchronization chip is a 1588 function chip.

An embodiment of the present invention also provides a computer storage medium, the computer-readable storage medium stores one or more programs, and one or more programs can be executed by one or more processors to implement any of the above time synchronization methods A step of.

The beneficial effects of the present invention are:

According to the time synchronization method, device, network device, and computer-readable storage medium provided by the embodiments of the present invention, the processor first performs time synchronization on the system clock according to the time synchronization protocol, and when the time synchronization of the system clock reaches a stable state, switches the The time synchronization chip continues to perform time synchronization to the system clock. Since the solution of the processor performing time synchronization according to the time synchronization protocol has the advantage of fast synchronization convergence speed, using this solution at the beginning of time synchronization can make the time deviation between the local device and the master device converge quickly. Since the time synchronization chip will fully suppress and filter the message data with the main device, after the time synchronization of the system clock reaches a stable state, the time synchronization chip will continue to perform time synchronization after the time synchronization chip, which can avoid network shocks, interference noise, etc. The impact of the time synchronization result, thereby improving the synchronization stability and synchronization accuracy of the system clock time synchronization.

Other features and corresponding beneficial effects of the present invention are explained in the following part of the specification, and it should be understood that at least part of the beneficial effects become obvious from the description in the specification of the present invention.

Description of drawings

FIG. 1 is a flowchart of a time synchronization method provided in Embodiment 1 of the present invention;

FIG. 2 is a flow chart of switching the time synchronization of the system clock by the time synchronization chip provided in Embodiment 1 of the present invention;

FIG. 3 is a flowchart of a time synchronization method provided in Embodiment 2 of the present invention;

FIG. 4 is a schematic diagram of a display interface of a network device provided in Embodiment 2 of the present invention;

FIG. 5 is a schematic structural diagram of a time synchronization device provided in Embodiment 3 of the present invention;

FIG. 6 is a schematic structural diagram of a time synchronization device provided in Embodiment 4 of the present invention;

FIG. 7 is a schematic diagram of a hardware structure of a network device provided in Embodiment 5 of the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below through specific implementation manners in conjunction with the accompanying drawings. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

Embodiment one:

The full name of the IEEE 1588 Time Synchronization Protocol is the Precision Clock Synchronization Protocol Standard for Network Measurement and Control Systems (IEEE1588 Precision Clock Synchronization Protocol), referred to as PTP (Precision timing Protocol, Precision Time Protocol). It supports time synchronization between master and slave devices through packet exchange, with sub-microsecond time synchronization accuracy. The 1588 time synchronization system can be realized by pure software, for example, using the CPU to implement the 1588 protocol stack to complete the sending and receiving of PTP messages, time stamp processing and time synchronization. Realizing the 1588 time synchronization system by CPU pure software has some advantages: simple implementation, only need to maintain 1588 protocol stack, independent of the specific hardware at the bottom; fast synchronization convergence; low cost, etc. However, limited by the performance of the CPU, the sending rate of PTP packets is low. Moreover, due to the uncertainty of the path delay of the message from the device port to the CPU and the delay of software processing, this time method cannot achieve high precision.

In order to improve the precision of time synchronization, the 1588 time synchronization system can be realized by combining CPU software and underlying hardware. The CPU software is responsible for the operation of the protocol stack, and sends the calculation results of each sending and receiving message synchronization to adjust the underlying hardware. The underlying hardware is responsible for delay measurement and correction of packets on the internal transmission path of the device. In this way, the time synchronization accuracy of network devices can be greatly improved (up to nanosecond level), and the synchronization convergence speed is very fast. However, considering the processing power and speed of the CPU, this method generally does not perform or only performs simple suppression filtering during timestamp calculation and processing. Therefore, the result of time synchronization is very sensitive to network oscillation and noise interference, and the stability of time synchronization is poor.

In order to get rid of the limitations of the CPU software implementation in the above-mentioned scheme, a special 1588 function chip can be considered when designing the 1588 time synchronization system scheme. The 1588 function chip can run the 1588 protocol stack independently of the CPU, send and receive PTP messages, and perform time stamp processing and calculation. The CPU only needs to do the configuration and management work of the 1588 function chip. Compared with running the entire 1588 protocol stack, the CPU overhead can be ignored. In order to ensure the stability of 1588 time synchronization, the 1588 function chip performs sliding window filtering on the message data during synchronization. This processing can prevent clock time synchronization from being affected by network shocks, but at the same time, the sliding window filter processing also increases the time for synchronization to stabilize, and although the larger the sliding window, the better the effect of preventing network shocks, but the time synchronization reaches The time required for steady state is also longer. Especially when the initial synchronization time of the 1588 function chip is too different from the time of the peer device, the time required for synchronization convergence will be significantly increased.

In view of the above solution, in order to solve the problem of poor synchronization accuracy and synchronization stability when CPU pure software implements time synchronization, the 1588 function chip is used for time synchronization. While improving the accuracy and stability of time synchronization, it increases the problem of synchronization convergence time. This embodiment provides a time synchronization solution, please refer to Figure 1:

S102: The processor performs time synchronization on the system clock according to the time synchronization protocol.

When two network devices interact, it is necessary to ensure that the system times of the two network devices are consistent. In general, the slave device synchronizes the time of its own system clock with the time of the master device. Therefore, in this embodiment, the time synchronization method can be performed by the slave device. After the time synchronization starts, the slave device can control the processor of the device to perform time synchronization on the system clock of the device according to the time synchronization protocol. It should be understood that the so-called time synchronization of the system clock by the processor here refers to the situation where the processor will perform the main tasks such as running the protocol stack when the time synchronization of the system clock is performed, rather than the processor simply participating in the system clock For example, if the processor only configures the parameters of the time synchronization chip and does not perform other work of time synchronization, this situation cannot be counted as time synchronization by the processor. The process of the processor synchronizing the system clock according to the time synchronization protocol is introduced below, for example:

The slave device controls the processor to run the time synchronization protocol stack, sends and receives time synchronization messages with the master device, and then calculates the time deviation between the device and the master device according to the message timestamp, and then calculates the time of the system clock according to the calculation result Make adjustments to achieve time synchronization with the system clock of the device.

It should be understood that when the processor runs the time synchronization protocol stack to synchronize the time of the system clock, it only performs simple suppression filtering processing or even does not perform time filtering processing at all. Therefore, the slave device controls the processor according to the time synchronization protocol. When the system clock is synchronized, the time of the system clock can be achieved relatively quickly to achieve synchronization convergence. While controlling the processor to synchronize the time of the system clock, the slave device will detect the current time synchronization of the system clock to determine whether the time synchronization of the system clock is satisfied and reaches a stable state.

S104: After determining that the time synchronization of the system clock has reached a stable state, switch the time synchronization chip to continue time synchronization of the system clock.

After determining that the time synchronization of the system clock has reached a stable state, the slave device can control the switching and the time synchronization chip continues to perform time synchronization on the system clock. In this way, when the time synchronization chip is switched to perform time synchronization, the time synchronization of the time synchronization chip can skip the synchronization unconverged process, thereby avoiding the problem of slow convergence speed of the time synchronization chip. In an example of this embodiment, while the controller processor is performing time synchronization, the slave device will detect whether the time synchronization of the system clock has reached a stable state. Once it detects that the time synchronization of the system clock has reached a stable state, it will switch to the The time synchronization chip continues to perform time synchronization to the system clock. Of course, in some special cases, after the time synchronization of the system clock reaches a stable state, the processor can continue to be used for time synchronization for a period of time, and then switch to the synchronization stage where the time synchronization chip performs synchronization.

There are two requirements for the synchronization of the system clock to reach a stable state: first, the time synchronization accuracy of the system clock meets the requirements; second, the time synchronization of the system clock tends to be stable, that is, the time difference between the system clock and the master device does not fluctuate much. In order to determine whether the time synchronization of the system clock has reached a stable state, the slave device will perform a synchronization detection every time the processor calculates the time deviation between the current time of the system clock and the time of the master device to determine whether the system clock of the device is consistent with the time of the master device. Whether the time deviation Δt between devices is smaller than the preset deviation ΔTh. If the slave device determines that Δt is less than ΔTh in N times of detections among the K consecutive detections, it can be determined that the time synchronization of the system clock of the device has reached a stable state. For example, if K is set to 50 and N is set to 45, at least 45 of the latest 50 synchronization detections from the slave device have a detection result of Δt less than ΔTh, and it can be determined that the time synchronization of the system clock has reached stability state. Of course, in some examples of this embodiment, the values of K and N can also be set to be the same, that is, N=K. In this case, as long as the slave device determines that there have been K consecutive detection results that Δt ΔTh, it can be determined that the time synchronization of the system clock has reached a stable state. For example, N=K=5, as long as the slave device detects that the time deviation Δt between the system clock and the master device is less than the preset deviation ΔTh for 5 consecutive times, it can be determined that the time synchronization of the system clock has reached a stable state, and the time synchronization can be switched The chip continues to time-synchronize to the system clock.

The general process of the time synchronization chip for the system clock is basically similar to that of the processor for the time synchronization of the system clock: the time synchronization chip runs the time synchronization protocol stack independently of the processor, allowing the slave device and the master device to perform time synchronization. Synchronize the sending and receiving of messages, and calculate the time deviation between the device and the master device, and adjust the time of the system clock according to the time deviation.

It should be understood that the so-called "continuation" above means that the time synchronization chip synchronizes the system clock on the basis of the time synchronization performed by the processor. Therefore, when switching to the time synchronization chip for time synchronization, the slave device It should be ensured that the time synchronization chip first obtains the current time of the system clock. In this embodiment, the process of switching from the time synchronization switching of the system clock by the processor to the time synchronization of the system clock by the time synchronization chip can be shown in the flowchart of FIG. 2:

S202: Control the system clock to output time to the time synchronization chip.

In the process of controlling the time synchronization of the system clock by the control processor, the slave device will simultaneously detect whether the time synchronization of the system clock is satisfied and reaches a stable state. If the detection result indicates that the current stable state has been reached, the slave device can control the system clock to time The synchronization chip outputs the time so that the time synchronization chip can lock the time of the system clock. This process enables the time synchronization chip to obtain the synchronization result of the processor's time synchronization. The synchronization result will be used as the basis for the subsequent time synchronization of the time synchronization chip.

S204: After the time synchronization chip locks the time of the system clock, control the time synchronization chip to synchronize the time of the system clock, and stop the processor from synchronizing the time of the system clock.

After detecting that the time synchronization chip has locked the time output by the system clock, the slave device can control the time synchronization chip to synchronize the time of the system clock, and at the same time stop the processor from synchronizing the time of the system clock. Thereafter, the synchronization time received by the system clock should be output by the time synchronization chip.

It should be understood that although the time synchronization process of the time synchronization chip to the system clock is generally similar to the time synchronization process of the processor to the system clock, in this embodiment, the time synchronization chip will perform a sliding window on the message data sent and received. Filter processing, so the time synchronization result of the system clock can be prevented from being affected by network oscillation and interference noise. Therefore, the time synchronization method provided in this embodiment can combine the advantages of fast synchronization convergence when the processor performs time synchronization and the advantages of good synchronization stability and high synchronization accuracy when the time synchronization chip performs time synchronization.

The so-called time synchronization protocol in this embodiment may be the PTP protocol, and the time synchronization chip may be a 1588 function chip, or other chips for time synchronization with functions similar to the 1588 function chip. The 1588 function chip has a greater advantage in the packet sending rate than the way the processor runs the PTP protocol stack, and can well cope with scenarios that require a higher packet sending and receiving rate, such as frequency recovery.

In the time synchronization method provided in this embodiment, first, a processor is used to run a time synchronization protocol stack to perform time synchronization on a system clock, so that the time synchronization converges quickly. After confirming that the time synchronization of the system clock is in a stable state, you can switch to the time synchronization chip and continue to perform subsequent time synchronization based on the time synchronization result of the processor, so that the time synchronization has better synchronization accuracy and stability and improves the system Clock synchronization effect.

Furthermore, since the time synchronization chip has a relatively good message sending and receiving rate, it is suitable for frequency synchronization of the system clock and can meet the needs of scenarios such as frequency recovery.

Embodiment two:

This embodiment will continue to further introduce the time synchronization method provided by this embodiment in conjunction with some specific examples. Please refer to the flowchart of the time synchronization method shown in FIG. 3:

In this embodiment, the time synchronization protocol is the 1588 time synchronization protocol, that is, the PTP protocol, and the time synchronization chip is a 1588 function chip for example. This example is not the only implementation of the present invention. In addition, in the slave device, the system clock can be implemented by an FPGA (Field-Programmable Gate Array, Field Programmable Gate Array), and provided to each device, module, etc. in the device that needs to use the system time.

S302: The processor performs time synchronization on the system clock according to the time synchronization protocol.

The slave device control processor runs the time synchronization protocol stack according to the time synchronization protocol, exchanges messages with the master device, calculates the time deviation with the master device according to the message timestamp, and calculates the time of the system clock according to the time deviation Adjustment. It should be understood that when the processor runs the time synchronization protocol stack, it controls the communication unit of the slave device to send and receive messages with the master device.

S304: Detect whether the time synchronization of the system clock reaches a stable state.

If the judgment result is yes, it means that the time synchronization of the system clock has reached a stable state at present, so S306 can be entered, otherwise, it means that the time synchronization of the system clock has not yet reached a stable state, so it is necessary to continue to execute S302. In this embodiment, to detect whether the time synchronization of the system clock reaches a stable state, it may be detected whether the number of consecutive times that the time deviation Δt between the system clock and the master device is smaller than the preset deviation ΔTh reaches the preset number.

It should be understood that the value of the preset number of times is related to the current synchronization network environment. For example, in a synchronous environment supported by synchronous Ethernet, the value of the preset number of times may be appropriately reduced, and in a synchronous environment that does not support synchronous Ethernet, such as a pure 1588 synchronization environment, the value of the preset number of times may be appropriately increased. Similarly, the value of ΔTh is also related to the current synchronous network environment. In a synchronous environment supported by synchronous Ethernet, the value of ΔTh can be appropriately reduced. In an environment that does not support synchronous Ethernet, such as pure 1588 synchronization , the value of ΔTh can be appropriately increased. However, the value of ΔTh cannot be lower than the synchronization precision supported by the slave device. For example, for a slave device whose time precision is 8 ns, the value of ΔTh should be greater than or equal to 8 ns. Considering that the synchronization precision of the processor is not high, therefore, for a slave device whose time precision is 8 ns, the value of ΔTh is usually greater than 8 ns.

S306: Control the system clock to output time to the time synchronization chip.

After the slave device detects that the time synchronization of the system clock has reached a stable state, the slave device can control the system clock to output time to the time synchronization chip, that is, let the system clock transmit the time synchronization result of the processor to the time synchronization chip.

S308: Control the time synchronization chip to continue to perform time synchronization on the system clock.

After ensuring that the time synchronization chip locks the time of the system clock, the slave device controls the switch, allowing the system clock to perform time synchronization according to the output of the time synchronization chip. At this time, the processor does not need to run the time synchronization protocol stack to communicate with the master device. interaction, so the processing overhead of the processor can be greatly reduced. In addition, because the time synchronization chip runs the time synchronization protocol stack to send and receive messages, the speed can meet the requirements of frequency recovery. Therefore, after the time synchronization chip is controlled to continue time synchronization of the system clock, the frequency of the system clock and the master device can also be synchronized. frequency for synchronization.

S310: Detect whether the time synchronization chip is in an abnormal state.

While controlling the time synchronization chip to synchronize the system clock, the slave device will also detect the work of the time synchronization chip to determine whether the time synchronization chip is in an abnormal state, such as whether the time synchronization chip is faulty, etc. If it is determined that the time synchronization chip If it is in an abnormal state, go to S312, otherwise go to S308.

S312: Switching the processor to perform time synchronization on the system clock.

If it is determined that the time synchronization chip is in an abnormal state, the slave device can control and switch to the processor for time synchronization of the system clock, so that the system clock no longer performs time synchronization based on the output of the time synchronization chip. At this time, the slave device can control the time synchronization to be turned off chip. In addition, the slave device can also send an alarm message to remind the management personnel of the slave device that the time synchronization chip is abnormal, so that the management personnel can deal with the abnormal situation in time. Figure 4 shows a schematic diagram of a display interface for a network device to send prompt information to the management personnel after detecting a 1588 function chip failure. It should be understood that, in addition to the way of prompting the The alarm can be issued by sending out a prompt sound or a prompt voice.

In addition, after switching back to the time synchronization of the system clock by the processor, the slave device will no longer switch the time synchronization mode according to the time synchronization of the system clock reaching a stable state, so the slave device does not need to detect the status of the system clock. Whether time synchronization has reached a steady state.

The time synchronization method provided in this embodiment not only combines the respective advantages of the scheme of using the processor to run the protocol stack for time synchronization and the scheme of using the time synchronization chip for time synchronization, so that the entire time synchronization process shows a fast synchronization convergence speed, synchronization It has the advantages of high precision and good synchronization stability; moreover, it can also use the advantages of fast sending and receiving speed of the time synchronization chip to synchronize the frequency of the system clock. Furthermore, in the process of using the time synchronization chip to synchronize the time of the system clock, the slave device will also monitor whether the time synchronization chip is faulty, and when the time synchronization chip cannot work normally, it will switch to the processor to continue the time synchronization. It avoids the problem that when the time synchronization chip has a hardware failure, it cannot output or the output clock is abnormal, which seriously affects the normal operation of the system.

Embodiment three:

This embodiment provides a time synchronization device. Referring to FIG. 5 , the time synchronization device 50 includes a software synchronization module 502 and a chip synchronization module 504 . Wherein the first synchronization module 502 is used to control the processor to perform time synchronization on the system clock according to the time synchronization protocol, and the synchronization detection module 504 is used to detect whether the time synchronization of the system clock has reached a stable state; After the detection result of the module 504 is yes, the time synchronization chip is switched to continue time synchronization of the system clock.

When two network devices interact, it is necessary to ensure that the system times of the two network devices are consistent. In general, the slave device synchronizes the time of its own system clock with the time of the master device. Therefore, in this embodiment, the time synchronization apparatus 50 may be deployed on various network devices serving as slave devices. After the time synchronization starts, the first synchronization module 502 can perform time synchronization on the system clock of the device according to the time synchronization protocol. It should be understood that the so-called first synchronization module 502 here synchronizes the time of the system clock, which means that when the system clock is time synchronized, the first synchronization module 502 will perform main tasks such as running the protocol stack, rather than the first synchronization module 502. A synchronization module 502 simply participates in the time synchronization of the system clock. For example, if the first synchronization module 502 only configures the parameters of the time synchronization chip, but does not perform other tasks of time synchronization, then this situation cannot be regarded as caused by the first synchronization module. The synchronization module 502 performs time synchronization. The process of time synchronization of the system clock by the first synchronization module 502 according to the time synchronization protocol is introduced below, for example:

The first synchronization module 502 runs the time synchronization protocol stack, sends and receives time synchronization messages with the master device, then calculates the time deviation between the device and the master device according to the message timestamp, and then calculates the time of the system clock according to the calculation result Make adjustments to achieve time synchronization with the system clock of the device.

It should be understood that when the first synchronization module 502 runs the time synchronization protocol stack to synchronize the system clock, it will only perform simple suppression filtering processing or even no time filtering processing at all. Therefore, the first synchronization module 502 according to the time When the synchronization protocol synchronizes the system clock, it can make the time of the system clock achieve synchronization convergence relatively quickly. While performing time synchronization on the system clock, the synchronization detection module 504 will detect the current time synchronization of the system clock to determine whether the time synchronization of the system clock has reached a stable state.

After the synchronization detection module 504 determines that the time synchronization of the system clock has reached a stable state, the second synchronization module 506 may control to switch the time synchronization chip to continue time synchronization of the system clock. In this way, when the time synchronization chip is switched to perform time synchronization, the time synchronization of the time synchronization chip can skip the synchronization unconverged process, thereby avoiding the problem of slow convergence speed of the time synchronization chip. In an example of this embodiment, while the controller processor of the first synchronization module 502 is performing time synchronization, the synchronization detection module 504 will detect whether the time synchronization of the system clock has reached a stable state, once the time synchronization of the system clock is detected When a stable state is reached, the second synchronization module 506 immediately controls to switch to the time synchronization chip to continue time synchronization. Of course, in some special cases, the first synchronization module 502 can also continue to use the processor to perform time synchronization for a period of time after the synchronization detection module 504 detects that the time synchronization of the system clock has reached a stable state, and then the second synchronization module 506 It is switched to the synchronization stage where the time synchronization chip performs synchronization.

There are two requirements for the synchronization of the system clock to reach a stable state: first, the time synchronization accuracy of the system clock meets the requirements; second, the time synchronization of the system clock tends to be stable, that is, the time difference between the system clock and the master device does not fluctuate much. In order to determine whether the time synchronization of the system clock has reached a stable state, the synchronization detection module 504 will perform a synchronization detection after the processor calculates the time deviation between the current time of the system clock and the time of the master device each time to determine the system clock of this device. Whether the time deviation Δt with the master device is smaller than the preset deviation ΔTh. If the synchronization detection module 504 determines that in the K consecutive detections, there are N detection results where Δt is less than ΔTh, it can be determined that the time synchronization of the device's system clock has reached a stable state. For example, if K is set to 50, and N is set to 45, then at least among the latest 50 synchronization detections of the synchronization detection module 504, there are at least 45 detection results that Δt is less than ΔTh, and it can be determined that the time synchronization of the system clock has been completed. reach a steady state. Of course, in some examples of this embodiment, the values of K and N can also be set to be the same, that is, N=K. In this case, only the synchronization detection module 504 determines that there are K consecutive detection results that are all If Δt is less than ΔTh, it can be determined that the time synchronization of the system clock has reached a stable state. For example, if N=K=5, as long as the synchronization detection module 504 detects that the time deviation Δt between the system clock and the master device is less than the preset deviation ΔTh for 5 consecutive times, it can be determined that the time synchronization of the system clock has reached a stable state, and it can be switched by The time synchronization chip continues to perform time synchronization to the system clock.

The general process that the second synchronization module 506 controls the time synchronization chip to synchronize the system clock is basically similar to the general process that the processor performs time synchronization to the system clock: the second synchronization module 506 controls the time synchronization chip to run the time synchronization protocol independently of the processor The stack sends and receives time synchronization messages with the master device, and calculates the time deviation between the device and the master device, and adjusts the time of the system clock according to the time deviation.

It should be understood that the so-called "continuation" above means that the time synchronization chip synchronizes the time of the system clock on the basis of the time synchronization performed by the processor. Therefore, when switching to the time synchronization chip for time synchronization, the second The synchronization module 506 should ensure that the time synchronization chip obtains the current time of the system clock first.

During the process of the first synchronization module 502 controlling the processor to perform time synchronization on the system clock, the synchronization detection module 504 will simultaneously detect whether the time synchronization of the system clock meets the requirements of reaching a stable state. If the detection result indicates that the current state has reached a stable state, then the first The second synchronization module 506 can control the system clock to output time to the time synchronization chip, so that the time synchronization chip can lock the time of the system clock. This process can enable the time synchronization chip to obtain the synchronization result of the processor performing time synchronization, and the synchronization result will be used as The basis for the subsequent time synchronization of the time synchronization chip.

After detecting that the time synchronization chip has locked the output time of the system clock, the second synchronization module 506 can control the time synchronization chip to synchronize the time of the system clock, and at the same time stop the processor from synchronizing the time of the system clock. Thereafter, the synchronization time received by the system clock should be output by the time synchronization chip.

It should be understood that although the time synchronization process of the time synchronization chip to the system clock is generally similar to the time synchronization process of the processor to the system clock, in this embodiment, the time synchronization chip will perform a sliding window on the message data sent and received. Filter processing, so the time synchronization result of the system clock can be prevented from being affected by network oscillation and interference noise. Therefore, the time synchronization device 50 provided in this embodiment can combine the advantages of fast synchronization convergence when the processor performs time synchronization and the advantages of good synchronization stability and high synchronization accuracy when the time synchronization chip performs time synchronization.

The so-called time synchronization protocol in this embodiment may be the PTP protocol, and the time synchronization chip may be a 1588 function chip, or other chips for time synchronization with functions similar to the 1588 function chip. The 1588 function chip has a greater advantage in the packet sending rate than the way the processor runs the PTP protocol stack, and can well cope with scenarios that require a higher packet sending and receiving rate, such as frequency recovery.

The time synchronization device provided in this embodiment first uses a processor to run a time synchronization protocol stack to perform time synchronization on a system clock, so that time and time synchronization converges quickly. After confirming that the time synchronization of the system clock is in a stable state, you can switch to the time synchronization chip and continue to perform subsequent time synchronization based on the time synchronization result of the processor, so that the time synchronization has better synchronization accuracy and stability and improves the system Clock synchronization effect.

Furthermore, since the time synchronization chip has a relatively good message sending and receiving rate, it is suitable for frequency synchronization of the system clock and can meet the needs of scenarios such as frequency recovery.

Embodiment four:

This embodiment will continue to further introduce the aforementioned time synchronization device in conjunction with some specific examples. In this embodiment, it is assumed that the time synchronization protocol is the 1588 time synchronization protocol, that is, the PTP protocol, and the time synchronization chip is a 1588 function chip. Personnel should understand that this is only an example given in this embodiment, and is not the only implementation manner of the present invention.

Please refer to a schematic structural diagram of a time synchronization device shown in FIG. 6: the time synchronization device 60 includes a first synchronization module 602, a synchronization detection module 604, and a second synchronization module 606, as well as an exception handling module 608, wherein the first synchronization Module 602, synchronization detection module 604, and second synchronization module 606 are similar to the functions of the modules in FIG. Perform time synchronization. The following is an introduction to the process in which the time synchronization device 60 performs time synchronization of the slave device system clock:

The first synchronization module 602 controls the processor to run the time synchronization protocol stack according to the time synchronization protocol, interacts with the master device, and calculates the time deviation with the master device according to the message timestamp, and adjusts the system clock according to the time deviation time to adjust. It should be understood that when the processor runs the time synchronization protocol stack, it sends and receives messages with the master device by controlling the communication unit of the slave device.

When the first synchronization module 602 controls the processor to run the time synchronization protocol stack to synchronize the system clock, the synchronization detection module 604 can detect whether the time synchronization of the system clock has reached a stable state. If the judgment result of the synchronization detection module 604 is yes, it means that the time synchronization of the system clock has reached a stable state, and therefore, the second synchronization module 606 can start working. Otherwise, it means that the time synchronization of the system clock has not reached a stable state, so the first synchronization module 602 will continue to work. In this embodiment, the synchronization detection module 604 detects whether the time synchronization of the system clock has reached a stable state, and may detect whether the number of consecutive times that the time deviation Δt between the system clock and the master device is smaller than the preset deviation ΔTh reaches the preset number.

It should be understood that the value of the preset number of times is related to the current synchronization network environment. For example, in a synchronous environment supported by synchronous Ethernet, the value of the preset number of times may be appropriately reduced, and in a synchronous environment that does not support synchronous Ethernet, such as a pure 1588 synchronization environment, the value of the preset number of times may be appropriately increased. Similarly, the value of ΔTh is also related to the current synchronous network environment. In a synchronous environment supported by synchronous Ethernet, the value of ΔTh can be appropriately reduced. In an environment that does not support synchronous Ethernet, such as pure 1588 synchronization , the value of ΔTh can be appropriately increased. However, the value of ΔTh cannot be lower than the synchronization precision supported by the slave device. For example, for a slave device whose time precision is 8 ns, the value of ΔTh should be greater than or equal to 8 ns. Considering that the synchronization precision of the processor is not high, therefore, for a slave device whose time precision is 8 ns, the value of ΔTh is usually greater than 8 ns.

After the synchronization detection module 604 detects that the time synchronization of the system clock has reached a stable state, the second synchronization module 606 can control the system clock to output time to the time synchronization chip, that is, let the system clock transmit the time synchronization result of the processor to the time synchronization chip.

After ensuring that the time synchronization chip locks the time of the system clock, the second synchronization module 606 controls to switch, allowing the system clock to perform time synchronization according to the output of the time synchronization chip. At this time, the processor does not need to run the time synchronization protocol stack and the master device Packet interaction is carried out, so the processing overhead of the processor can be greatly reduced. In addition, because the time synchronization chip runs the time synchronization protocol stack to send and receive messages, the speed can meet the requirements of frequency recovery. Therefore, after the time synchronization chip is controlled to continue time synchronization of the system clock, the frequency of the system clock and the master device can also be synchronized. frequency for synchronization.

While controlling the time synchronization chip to synchronize the system clock, the abnormal handling module 608 will detect the work of the time synchronization chip to determine whether the time synchronization chip is in an abnormal state, such as whether the time synchronization chip is faulty, etc. If the chip is in an abnormal state, it enters into the abnormal handling module 608 to switch the time synchronization of the system clock by the processor, so that the system clock no longer performs time synchronization according to the output of the time synchronization chip. At this time, the abnormal handling module 608 can control the shutdown of the time synchronization chip . In addition, the exception handling module 608 can also make the slave device send out an alarm message to prompt the management personnel of the slave device that the time synchronization chip is abnormal, so that the management personnel can deal with the abnormal situation in time. Figure 4 shows a schematic diagram of a display interface for a network device to send prompt information to the management personnel after detecting a 1588 function chip failure. It should be understood that, in addition to the way of prompting the The alarm can be issued by sending out a prompt sound or a prompt voice.

In addition, after switching back to the time synchronization of the system clock by the processor, the second synchronization module 606 will no longer switch the time synchronization mode according to the time synchronization of the system clock reaching a stable state, so the synchronization detection module 604 does not need Then check whether the time synchronization of the system clock has reached a stable state. Therefore, both the synchronization detection module 604 and the second synchronization module 606 may be in a dormant state.

The time synchronization devices provided in this embodiment and Embodiment 3 can all be deployed on network equipment, wherein the functions of the first synchronization module, the synchronization detection module, the second synchronization module and the exception handling module can all be implemented by the processor of the network equipment accomplish.

The time synchronization device provided in this embodiment not only combines the respective advantages of the scheme of using the processor to run the protocol stack for time synchronization and the scheme of using the time synchronization chip for time synchronization, so that the entire time synchronization process shows a fast synchronization convergence speed, synchronization It has the advantages of high precision and good synchronization stability; moreover, it can also use the advantages of fast sending and receiving speed of the time synchronization chip to synchronize the frequency of the system clock. Furthermore, in the process of using the time synchronization chip to synchronize the time of the system clock, the slave device will also monitor whether the time synchronization chip is faulty, and when the time synchronization chip cannot work normally, it will switch to the processor to continue the time synchronization. It avoids the problem that in the case of a hardware failure of the time synchronization chip, the output cannot be output or the output clock is abnormal, which seriously affects the normal operation of the system.

Embodiment five:

This embodiment first provides a computer-readable storage medium, which can store one or more computer programs that can be read, compiled, and executed by one or more processors. In this embodiment The computer-readable storage medium may store a time synchronization program, and the time synchronization program may be executed by one or more processors to implement any one of the time synchronization methods described in Embodiments 1 and 2 above.

This embodiment also provides a network device, please refer to the schematic diagram of the hardware structure of the network device 7 shown in FIG. 7:

The network device 7 includes a processor 71, a memory 72, a time synchronization chip 73, a communication unit 74, and a communication bus 75 for realizing the communication between the processor 71 and the memory 72, the time synchronization chip 73, and the communication unit 74 respectively. The memory 72 may be the aforementioned storage medium storing the time synchronization program. The processor 71 can read the time synchronization program stored in the memory 72, compile and execute any time synchronization method introduced in Embodiments 1 and 2.

In this embodiment, the processor 71 of the network device 7 performs time synchronization on the system clock of the device according to the time synchronization program, which may be performed according to the 1588 time synchronization protocol, and the time synchronization chip 73 may also be a 1588 function chip. The time synchronization process of the network device 7 is briefly introduced below:

The processor 71 can run a time synchronization protocol stack, such as a 1588 time synchronization protocol stack, control the communication unit 74 to interact with the master device, calculate the time deviation between the device and the master device according to the message timestamp, and calculate the time deviation between the device and the master device according to the time stamp. The deviation adjusts the system time of this device synchronously. Processor 71 also can detect whether the time synchronization of system clock has reached a steady state when operating the protocol stack to synchronize the time of system clock, if the detection result is yes, then processor 71 notifies time synchronization chip 73 to continue to system clock time to synchronize. Optionally, the processor 71 can notify the system clock, for example, the FPGA chip outputs the time to the time synchronization chip 73, after determining the time when the time synchronization chip 73 locks the system clock, the processor 71 can stop running the time synchronization protocol stack, and the time synchronization is performed by the time synchronization chip 73. The chip 73 independently runs the time synchronization protocol stack to synchronize the system clock.

In addition, while the time synchronization chip 73 is synchronizing the system clock, the processor 71 can also monitor the working state of the time synchronization chip 73. If it is determined that the time synchronization chip 73 is in an abnormal state, such as a failure of the time synchronization chip 73, then processing The controller 71 will continue to run the protocol stack to synchronize the system clock. At the same time, the processor 71 can control to turn off the abnormal time synchronization chip 73 to prevent the time synchronization chip 73 from outputting wrong synchronization information to the system clock.

For other details of the time synchronization of the network device 7, reference may be made to the introduction of the foregoing embodiments, which will not be repeated here.

The network device and the computer-readable storage medium provided in this embodiment ensure fast synchronization convergence speed, high synchronization precision and good synchronization stability of system clock time synchronization. At the same time, after the time synchronization chip fails, it can be switched to the processor to continue the time synchronization immediately, avoiding the problem that the hardware failure of the time synchronization chip affects the normal operation of the system.

Obviously, those skilled in the art should understand that each module or each step of the above-mentioned embodiments of the present invention can be realized by a general-purpose computing device, and they can be concentrated on a single computing device, or distributed across multiple computing devices. On the network, optionally, they can be implemented with executable program codes of computing devices, thus, they can be stored in computer storage media (ROM/RAM, magnetic disk, optical disk) to be executed by computing devices, and in some In some cases, the steps shown or described can be performed in a different order than here, or they can be fabricated into individual integrated circuit modules, or multiple modules or steps can be fabricated into a single integrated circuit module for implementation. . Therefore, the present invention is not limited to any specific combination of hardware and software.

The above content is a further detailed description of the embodiments of the present invention in conjunction with specific implementation modes, and it cannot be assumed that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deduction or replacement can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (10)

1. A method of time synchronization, comprising:

the processor carries out time synchronization on the system clock according to a time synchronization protocol;

and after the time synchronization of the system clock is determined to reach a stable state, switching a time synchronization chip to continue to perform time synchronization on the system clock.

2. The time synchronization method of claim 1, wherein the switching to continue time synchronizing the system clock by a synchronization chip comprises:

controlling the system clock to output time to the time synchronization chip;

and after the time synchronization chip locks the time of the system clock, controlling the time synchronization chip to perform time synchronization on the system clock, and stopping the time synchronization of the processor on the system clock.

3. The method of time synchronization of claim 1, wherein the determining that the time synchronization of the system clock reaches a steady state comprises:

and determining that the time deviation delta t between the equipment and the main equipment is less than the preset deviation delta Th for a preset time.

4. The time synchronization method according to claim 3, wherein the determining that the number of times that the time deviation Δ t between the own device and the master device is smaller than the preset deviation Δ Th reaches a preset number of times includes:

and determining whether the continuous times that the time deviation delta t between the equipment and the main equipment is smaller than the preset deviation delta Th reach the preset times.

5. The method for time synchronization of claim 1, wherein the time synchronization protocol is a precision clock synchronization protocol standard, PTP, of a network measurement and control system.

6. The time synchronization method according to any one of claims 1 to 5, wherein after controlling the synchronization chip to continue time synchronizing the system clock, further comprising:

and when the synchronization chip is in an abnormal state, controlling the processor to continue to perform time synchronization on the system clock according to the time synchronization protocol.

7. A time synchronization apparatus, comprising:

the first synchronization module is used for carrying out time synchronization on the system clock according to a time synchronization protocol;

the synchronous detection module is used for detecting whether the time synchronization of the system clock reaches a stable state;

and the second synchronization module is used for switching the time synchronization chip to continue to perform time synchronization on the system clock after the time synchronization of the system clock is determined to reach a stable state.

8. A network device is characterized by comprising a processor, a memory, a time synchronization chip, a communication unit and a communication bus;

the communication bus is used for realizing the connection and communication among the processor, the memory, the time synchronization chip and the communication unit respectively;

the processor is configured to execute one or more programs stored in the memory to implement the steps of the time synchronization method of any one of claims 1 to 6.

9. The network device of claim 8, wherein the time synchronization chip is a 1588 function chip.

10. A computer-readable storage medium, characterized in that the computer-readable storage medium stores one or more programs which are executable by one or more processors to implement the steps of the time synchronization method according to any one of claims 1 to 6.