[go: up one dir, main page]

CN110609795B - Memory management method, memory control circuit unit and memory storage device - Google Patents

Memory management method, memory control circuit unit and memory storage device Download PDF

Info

Publication number
CN110609795B
CN110609795B CN201810612079.1A CN201810612079A CN110609795B CN 110609795 B CN110609795 B CN 110609795B CN 201810612079 A CN201810612079 A CN 201810612079A CN 110609795 B CN110609795 B CN 110609795B
Authority
CN
China
Prior art keywords
super
units
physical
good
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810612079.1A
Other languages
Chinese (zh)
Other versions
CN110609795A (en
Inventor
柯伯政
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Phison Electronics Corp
Original Assignee
Phison Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Phison Electronics Corp filed Critical Phison Electronics Corp
Priority to CN201810612079.1A priority Critical patent/CN110609795B/en
Publication of CN110609795A publication Critical patent/CN110609795A/en
Application granted granted Critical
Publication of CN110609795B publication Critical patent/CN110609795B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/0223User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023Free address space management
    • G06F12/0238Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

本发明提供一种用于可复写式非易失性存储器模块的存储器管理方法、存储器控制电路单元与存储器存储装置。可复写式非易失性存储器模块包括多个超实体单元,多个超实体单元至少包括多个好超实体单元及多个部分好超实体单元。所述方法包括接收主机写入指令;根据多个好超实体单元与多个部分好超实体单元的个数比率从多个超实体单元选择出第一超实体单元集合,其中第一超实体单元集合包括按个数比率从多个超实体单元选择出的多个第一好超实体单元及至少一个第一部分好超实体单元;以及将数据写入至第一超实体单元集合的好实体抹除单元中,以回应主机写入指令。

Figure 201810612079

The invention provides a memory management method for a rewritable non-volatile memory module, a memory control circuit unit and a memory storage device. The rewritable non-volatile memory module includes a plurality of superphysical units, and the plurality of superphysical units at least include a plurality of good superphysical units and a plurality of partial good superphysical units. The method includes receiving a host write command; selecting a first set of super-physical units from the plurality of super-physical units according to the ratio of the number of multiple good super-physical units to a plurality of partial good super-physical units, wherein the first super-physical unit The collection includes a plurality of first good super-substance units selected from the plurality of super-substance units according to the number ratio and at least one first part of good super-substance units; unit in response to host write commands.

Figure 201810612079

Description

存储器管理方法、存储器控制电路单元与存储器存储装置Memory management method, memory control circuit unit and memory storage device

技术领域technical field

本发明涉及一种存储器管理方法、存储器控制电路单元与存储器存储装置。The invention relates to a memory management method, a memory control circuit unit and a memory storage device.

背景技术Background technique

数码相机、移动电话与MP3播放器在这几年来的成长十分迅速,使得消费者对存储媒体的需求也急速增加。由于可复写式非易失性存储器模块(例如,快闪存储器)具有数据非易失性、省电、体积小,以及无机械结构等特性,所以非常适合内建于上述所举例的各种可携式多媒体装置中。Digital cameras, mobile phones, and MP3 players have grown rapidly in recent years, making consumers' demand for storage media also increase rapidly. Since the rewritable non-volatile memory module (for example, flash memory) has the characteristics of data non-volatility, power saving, small size, and no mechanical structure, it is very suitable for being built in the various memory modules listed above. in portable multimedia devices.

为了提高快闪存储器的最高速度(即频宽),当今快闪存储器大部分使用多通道(channel)的设计。属于不同通道且区块面不同的实体抹除单元(block)可以组成一个虚拟区块(Virtual Block,VB)(在此亦称为超实体单元)。然而因为出厂良率与使用寿命等因素(early bad/later bad),超实体单元中的一些实体抹除单元会因坏掉而无法使用,其中,包含因坏掉而无法使用的实体抹除单元的超实体单元称之为部分好超实体单元(non allgood VB),所有实体抹除单元皆可用的超实体单元称之为好超实体单元(all good VB)。In order to increase the maximum speed (ie bandwidth) of the flash memory, most of the current flash memory uses a multi-channel (channel) design. Physical erase units (blocks) belonging to different channels and with different block planes can form a virtual block (Virtual Block, VB) (also referred to as a super-physical unit herein). However, due to factors such as factory yield and service life (early bad/later bad), some physical erasing units in the super-solid unit will become unusable due to damage, including physical erasing units that cannot be used due to damage The super-substance unit of VB is called part good VB (non allgood VB), and the super-substance unit available to all solid erasing units is called good VB (all good VB).

为了提高生产的良率以及快闪存储器的寿命,部分好超实体单元也会拿来使用。但在使用部分好超实体单元的时候,有些通道会因此通道的实体抹除单元坏掉而无法使用,就会造成整个通道闲置,浪费频宽。In order to improve the production yield and the lifetime of the flash memory, some good super solid cells will also be used. However, when some good super-physical units are used, some channels cannot be used because the physical erasing unit of the channel is broken, which will cause the entire channel to be idle and waste bandwidth.

请参照图1,图1为单位时间内快闪存储器的速度持续低落的示意图。当快闪存储器设计不良,单位时间内连续挑到包括有坏实体抹除单元的部分好超实体单元的话,就可能会造成单位时间内快闪存储器的速度持续低落,或是速度忽快忽慢等等性能不稳定的情形,这在许多应用上是不乐意见到的。Please refer to FIG. 1 . FIG. 1 is a schematic diagram of a continuous decrease in the speed of the flash memory per unit time. When the design of the flash memory is poor, if some good super-physical units including bad physical erasing units are continuously selected per unit time, the speed of the flash memory may continue to decrease per unit time, or the speed may fluctuate. Wait for the situation of unstable performance, which is not happy to see in many applications.

发明内容Contents of the invention

本发明提供一种存储器管理方法、存储器控制电路单元与存储器存储装置。The invention provides a memory management method, a memory control circuit unit and a memory storage device.

本发明的一范例实施例提出一种存储器管理方法,用于可复写式非易失性存储器模块。可复写式非易失性存储器模块包括至少包括多个好超实体单元及多个部分好超实体单元的多个超实体单元,其中每一个好超实体单元包括多个好实体抹除单元,每一个部分好超实体单元包括至少一个坏实体抹除单元。此存储器管理方法包括:接收主机写入指令;根据可复写式非易失性存储器模块中多个好超实体单元与多个部分好超实体单元的个数比率从多个超实体单元选择出第一超实体单元集合,其中第一超实体单元集合包括按个数比率从多个超实体单元选择出的多个第一好超实体单元及至少一个第一部分好超实体单元;以及将数据写入至第一超实体单元集合的好实体抹除单元中,以回应主机写入指令。An exemplary embodiment of the present invention provides a memory management method for a rewritable non-volatile memory module. The rewritable non-volatile memory module includes at least a plurality of good super-substance units comprising a plurality of good super-substance units and a plurality of partial good super-substance units, wherein each good super-substance unit comprises a plurality of good super-substance units, each A partially good super-substance unit includes at least one bad-substance erasure unit. The memory management method includes: receiving a host write command; selecting the first super-solid unit from the multiple super-solid units according to the number ratio of multiple good super-solid units and multiple good super-solid units in the rewritable non-volatile memory module A collection of super-substance units, wherein the first collection of super-substance units comprises a plurality of first good super-substance units selected from a plurality of super-substance units according to the number ratio and at least one first part of good super-substance units; and writing data to the good physical erase unit of the first super-physical unit set in response to the host write command.

在本发明的一范例实施例中,上述存储器管理方法还包括根据多个好超实体单元的个数与多个部分好超实体单元的个数动态地更新个数比率。In an exemplary embodiment of the present invention, the memory management method further includes dynamically updating the number ratio according to the number of good superphysical units and the number of partial good superphysical units.

在本发明的一范例实施例中,上述存储器管理方法还包括根据可复写式非易失性存储器模块中好超实体单元与部分好超实体单元的个数比率从可复写式非易失性存储器模块中除第一超实体单元集合以外的剩余超实体单元之中选择出第二超实体单元集合,其中第二超实体单元集合包括按个数比率从剩余超实体单元选择出的多个第二好超实体单元及至少一个第二部分好超实体单元;以及将数据继续写入至第二超实体单元集合的好实体抹除单元中。In an exemplary embodiment of the present invention, the above-mentioned memory management method further includes selecting from the rewritable non-volatile memory according to the ratio of the number of good super-physical units to some good super-physical units in the rewritable non-volatile memory module. Select the second set of super-entity units from the remaining super-entity units in the module except the first set of super-entity units, wherein the second set of super-entity units includes a plurality of second super-entity units selected from the remaining super-entity units according to the number ratio Good super-physical units and at least one second part of good super-physical units; and continuing to write data into the good physical erase units of the second set of super-physical units.

在本发明的一范例实施例中,上述存储器管理方法还包括将多个超实体单元至少分组为坏超实体单元、部分好超实体单元以及好超实体单元;对坏超实体单元、部分好超实体单元以及好超实体单元分别作标记;以及更新超实体单元伫列表。In an exemplary embodiment of the present invention, the memory management method further includes at least grouping a plurality of super-physical units into bad super-physical units, some good super-physical units, and good super-physical units; Solid elements and good supersolid elements are marked separately; and the supersolid element queue list is updated.

在本发明的一范例实施例中,上述存储器管理方法还包括依据每一超实体单元中坏实体抹除单元的个数与每一超实体单元中实体抹除单元的总个数的比例将多个超实体单元至少分组为坏超实体单元、部分好超实体单元以及好超实体单元。In an exemplary embodiment of the present invention, the above-mentioned memory management method further includes setting the ratio of the number of bad physical erasing units in each super-physical unit to the total number of physical erasing units in each super-physical unit superphysical units are grouped at least into bad superphysical units, some good superphysical units, and good superphysical units.

在本发明的一范例实施例中,其中根据可复写式非易失性存储器模块中多个好超实体单元与多个部分好超实体单元的个数比率从多个超实体单元选择出第一超实体单元集合的步骤包括:依据超实体单元伫列表选择出第一超实体单元集合;以及对第一超实体单元集合中的多个第一好超实体单元的个数及至少一个第一部分好超实体单元的个数计数。In an exemplary embodiment of the present invention, the first super-solid unit is selected from the plurality of super-solid units according to the ratio of the number of good super-solid units to a plurality of partial good super-solid units in the rewritable non-volatile memory module. The step of super-solid unit set includes: selecting the first super-solid unit set according to the super-solid unit queue table; Count the number of super solid elements.

本发明的一范例实施例提出一种存储器控制电路单元,用于包括多个超实体单元的可复写式非易失性存储器模块。多个超实体单元至少包括多个好超实体单元及多个部分好超实体单元,其中每一个好超实体单元包括多个好实体抹除单元,每一个部分好超实体单元包括至少一个坏实体抹除单元。此存储器控制电路单元包括:主机接口、存储器接口以及存储器管理电路。主机接口用以电性连接至主机系统。存储器接口用以电性连接至可复写式非易失性存储器模块。存储器管理电路电性连接至主机接口与存储器接口。其中存储器管理电路用以接收主机写入指令,根据可复写式非易失性存储器模块中多个好超实体单元与多个部分好超实体单元的个数比率从多个超实体单元选择出第一超实体单元集合,第一超实体单元集合包括按个数比率从多个超实体单元选择出的多个第一好超实体单元及至少一个第一部分好超实体单元。存储器管理电路还用以将数据写入至第一超实体单元集合的好实体抹除单元中,以回应主机写入指令。An exemplary embodiment of the present invention provides a memory control circuit unit for a rewritable non-volatile memory module including a plurality of super-physical units. A plurality of super-entity units at least includes a plurality of good super-entity units and a plurality of partial good super-entity units, wherein each good super-entity unit includes a plurality of good-entity erasure units, and each partial good super-entity unit includes at least one bad entity Erase the unit. The memory control circuit unit includes: a host interface, a memory interface and a memory management circuit. The host interface is used to electrically connect to the host system. The memory interface is used for electrically connecting to the rewritable non-volatile memory module. The memory management circuit is electrically connected to the host interface and the memory interface. Wherein the memory management circuit is used to receive the write command from the host, and select the first super-solid unit from the multiple super-solid units according to the ratio of the number of good super-solid units in the rewritable non-volatile memory module to a plurality of partial good super-solid units. A set of super-physical units. The first set of super-physical units includes a plurality of first good super-physical units and at least one first partial good super-physical unit selected from the plurality of super-physical units according to the number ratio. The memory management circuit is also used for writing data into good physical erase units of the first super-physical unit set in response to a host write command.

在本发明的一范例实施例中,其中存储器管理电路还用以根据多个好超实体单元的个数与多个部分好超实体单元的个数动态地更新个数比率。In an exemplary embodiment of the present invention, the memory management circuit is further configured to dynamically update the number ratio according to the number of good superphysical units and the number of partial good superphysical units.

在本发明的一范例实施例中,其中存储器管理电路还用以根据可复写式非易失性存储器模块中好超实体单元与部分好超实体单元的个数比率从可复写式非易失性存储器模块中除第一超实体单元集合以外的剩余超实体单元之中选择出第二超实体单元集合,其中第二超实体单元集合包括按个数比率从剩余超实体单元选择出的多个第二好超实体单元及至少一个第二部分好超实体单元。此外,存储器管理电路还用以将数据继续写入至第二超实体单元集合的好实体抹除单元中。In an exemplary embodiment of the present invention, the memory management circuit is further configured to switch from the rewritable nonvolatile A second set of super-entity units is selected from the remaining super-entity units in the memory module except the first set of super-entity units, wherein the second set of super-entity units includes a plurality of first super-entity units selected from the remaining super-entity units according to the number ratio Two good super-substance elements and at least one second part of good super-substance elements. In addition, the memory management circuit is also used to continue writing data into good physical erase units of the second super-physical unit set.

在本发明的一范例实施例中,其中存储器管理电路哈用以将多个超实体单元至少分组为坏超实体单元、部分好超实体单元以及好超实体单元并且对坏超实体单元、部分好超实体单元以及好超实体单元分别作标记。此外,存储器管理电路还用以更新超实体单元伫列表。In an exemplary embodiment of the present invention, wherein the memory management circuit is configured to at least group a plurality of super-entity units into bad super-entity units, partially good super-entity units, and good super-entity units and for bad super-entity units, partially good super-entity units Super-solid units and good super-solid units are marked separately. In addition, the memory management circuit is also used to update the super-physical unit queue table.

在本发明的一范例实施例中,其中存储器管理电路还用以依据每一超实体单元中坏实体抹除单元的个数与每一超实体单元中实体抹除单元的总个数的一比例将多个超实体单元至少分组为坏超实体单元、部分好超实体单元以及好超实体单元。In an exemplary embodiment of the present invention, the memory management circuit is further configured according to a ratio of the number of bad physical erase units in each super-physical unit to the total number of physical erase units in each super-physical unit The plurality of superphysical units are grouped at least into bad superphysical units, partially good superphysical units, and good superphysical units.

在本发明的一范例实施例中,其中存储器管理电路还用以根据可复写式非易失性存储器模块中多个好超实体单元与多个部分好超实体单元的个数比率从多个超实体单元选择出第一超实体单元集合的操作包括,存储器管理电路还用以依据超实体单元伫列表选择出第一超实体单元集合。存储器管理电路还用以对第一超实体单元集合中的多个第一好超实体单元的个数及至少一个第一部分好超实体单元的个数计数。In an exemplary embodiment of the present invention, the memory management circuit is further configured to select from a plurality of super-physical units according to the ratio of the number of good super-physical units to a plurality of partial good super-physical units in the rewritable non-volatile memory module The operation of selecting the first set of super-physical units by the physical unit includes that the memory management circuit is also used to select the first set of super-physical units according to the queue list of super-physical units. The memory management circuit is also used for counting the number of multiple first good super-physical units and the number of at least one first partial good super-physical unit in the first super-physical unit set.

本发明的一范例实施例提出一种存储器存储装置,包括:连接接口单元、可复写式非易失性存储器模块以及存储器控制电路单元。连接接口单元用以电性连接至主机系统。可复写式非易失性存储器模块包括多个超实体单元,多个超实体单元至少包括多个好超实体单元及多个部分好超实体单元,其中每一个好超实体单元包括多个好实体抹除单元,每一个部分好超实体单元包括至少一个坏实体抹除单元。存储器控制电路单元电性连接至连接接口单元与可复写式非易失性存储器模块。其中存储器控制电路单元用以接收主机写入指令,根据可复写式非易失性存储器模块中多个好超实体单元与多个部分好超实体单元的个数比率从多个超实体单元选择出第一超实体单元集合,第一超实体单元集合包括按个数比率从多个超实体单元选择出的多个第一好超实体单元及至少一个第一部分好超实体单元。存储器控制电路单元还用以将数据写入至第一超实体单元集合的好实体抹除单元中,以回应主机写入指令。An exemplary embodiment of the present invention provides a memory storage device, including: a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is used to electrically connect to the host system. The rewritable non-volatile memory module includes a plurality of super-entity units, and the plurality of super-entity units at least include a plurality of good super-entity units and a plurality of partial good super-entity units, wherein each good super-entity unit includes a plurality of good super-entity units Erasing units, each part of good super-physical units includes at least one bad-physical erasing unit. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable non-volatile memory module. Wherein the memory control circuit unit is used to receive the write command from the host, and selects from the plurality of super-solid units according to the number ratio of a plurality of good super-solid units and a plurality of partial good super-solid units in the rewritable non-volatile memory module A first set of super-physical units. The first set of super-physical units includes a plurality of first good super-physical units and at least one first partial good super-physical unit selected from the plurality of super-physical units according to the number ratio. The memory control circuit unit is also used for writing data into the good physical erase unit of the first super-physical unit set in response to the host write command.

在本发明的一范例实施例中,其中存储器控制电路单元还用以根据多个好超实体单元的个数与多个部分好超实体单元的个数动态地更新个数比率。In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to dynamically update the number ratio according to the number of good superphysical units and the number of partial good superphysical units.

在本发明的一范例实施例中,其中存储器控制电路单元还用以根据可复写式非易失性存储器模块中好超实体单元与部分好超实体单元的个数比率从可复写式非易失性存储器模块中除第一超实体单元集合以外的剩余超实体单元之中选择出第二超实体单元集合,其中第二超实体单元集合包括按个数比率从剩余超实体单元选择出的多个第二好超实体单元及至少一个第二部分好超实体单元。存储器控制电路单元还用以将数据继续写入至第二超实体单元集合的好实体抹除单元中。In an exemplary embodiment of the present invention, the memory control circuit unit is also used to switch from the rewritable nonvolatile Select a second set of super-entity units from the remaining super-entity units in the memory module except the first set of super-entity units, wherein the second set of super-entity units includes a plurality of super-entity units selected from the remaining super-entity units according to the number ratio A second-best super-substance element and at least one second partial-best super-substance element. The memory control circuit unit is also used for continuing to write data into good physical erase units of the second super-physical unit set.

在本发明的一范例实施例中,其中存储器控制电路单元还用以将多个超实体单元至少分组为坏超实体单元、部分好超实体单元以及好超实体单元并且对坏超实体单元、部分好超实体单元以及好超实体单元分别作标记。存储器控制电路单元还用以更新超实体单元伫列表。In an exemplary embodiment of the present invention, the memory control circuit unit is further used to at least group a plurality of super-entity units into bad super-entity units, some good super-entity units, and good super-entity units, and for bad super-entity units, some super-entity units Good super-solid elements and good super-solid elements are marked separately. The memory control circuit unit is also used to update the super-physical unit queue table.

在本发明的一范例实施例中,其中存储器控制电路单元还用以依据每一超实体单元中坏实体抹除单元的个数与每一超实体单元中实体抹除单元的总个数的比例将多个超实体单元至少分组为坏超实体单元、部分好超实体单元以及好超实体单元。In an exemplary embodiment of the present invention, the memory control circuit unit is also used to base the ratio of the number of bad physical erase units in each super-physical unit to the total number of physical erase units in each super-physical unit The plurality of superphysical units are grouped at least into bad superphysical units, partially good superphysical units, and good superphysical units.

在本发明的一范例实施例中,其中存储器控制电路单元还用以根据可复写式非易失性存储器模块中多个好超实体单元与多个部分好超实体单元的个数比率从多个超实体单元选择出第一超实体单元集合的操作包括,存储器控制电路单元还用以依据超实体单元伫列表选择出第一超实体单元集合。存储器控制电路单元还用以对第一超实体单元集合中的多个第一好超实体单元的个数及至少一个第一部分好超实体单元的个数计数。In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to select from multiple The operation of selecting the first set of super-physical units by the super-physical unit includes that the memory control circuit unit is also used to select the first set of super-physical units according to the queue list of super-physical units. The memory control circuit unit is also used for counting the number of multiple first good super-physical units and the number of at least one first partial good super-physical unit in the first super-physical unit set.

基于上述,本发明提供一种存储器管理方法、存储器控制电路单元与存储器存储装置,依据好超实体单元与部分好超实体单元的个数比率选择超实体单元集合以供主机系统的数据写入,平均了部分好超实体单元中坏实体抹除单元出现的机率,使得单位时间内可复写式非易失性存储器模块速度稳定,并且可复写式非易失性存储器模块的实体抹除单元使用次数较为平均,减少了平均磨损的机率,提高了可复写式非易失性存储器模块的使用寿命。Based on the above, the present invention provides a memory management method, a memory control circuit unit, and a memory storage device. According to the ratio of the number of good superphysical units to some good superphysical units, a set of hyperphysical units is selected for data writing by the host system. The probability of occurrence of bad physical erasing units in some good super-physical units is averaged, so that the speed of the rewritable non-volatile memory module is stable per unit time, and the number of times the physical erasing unit of the rewritable non-volatile memory module is used It is relatively average, reduces the probability of average wear, and improves the service life of the rewritable non-volatile memory module.

为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合附图作详细说明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

附图说明Description of drawings

图1为单位时间内快闪存储器的速度持续低落的示意图;FIG. 1 is a schematic diagram showing that the speed of the flash memory per unit time continues to decrease;

图2是根据一范例实施例所示出的主机系统、存储器存储装置及输入/输出(I/O)装置的示意图;2 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment;

图3是根据另一范例实施例所示出的主机系统、存储器存储装置及输入/输出(I/O)装置的示意图;3 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to another exemplary embodiment;

图4是根据另一范例实施例所示出的主机系统与存储器存储装置的示意图;FIG. 4 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment;

图5是根据一范例实施例所示出的主机系统与存储器存储装置的概要方块图;5 is a schematic block diagram of a host system and a memory storage device according to an exemplary embodiment;

图6是根据一范例实施例所示出的存储器控制电路单元的概要方块图;FIG. 6 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment;

图7是根据一范例实施例所示出的管理超实体单元的范例示意图;Fig. 7 is an example schematic diagram of a management super-entity unit shown according to an example embodiment;

图8是根据一范例实施例所示出的超实体单元中的实体抹除单元与逻辑地址映射的范例示意图;FIG. 8 is an example schematic diagram of a physical erase unit and logical address mapping in a super-physical unit according to an example embodiment;

图9是根据一范例实施例所示出的超实体单元中的实体抹除单元与逻辑地址重新映射的范例示意图;FIG. 9 is an exemplary schematic diagram of remapping physical erase units and logical addresses in a super-physical unit according to an exemplary embodiment;

图10为单位时间内快闪存储器的速度平稳的示意图;Fig. 10 is a schematic diagram of a stable speed of the flash memory per unit time;

图11是根据一范例实施例所示出的存储器管理方法的流程图;Fig. 11 is a flowchart of a memory management method according to an exemplary embodiment;

图12是根据一范例实施例所示出的实体抹除单元与逻辑地址重新映射的流程图;FIG. 12 is a flow chart of remapping between physical erasing units and logical addresses according to an exemplary embodiment;

图13是根据另一范例实施例所示出的存储器管理方法的流程图。Fig. 13 is a flowchart of a memory management method according to another exemplary embodiment.

附图标号说明:Explanation of reference numbers:

10:存储器存储装置10: Memory storage device

11:主机系统11: Host system

12:输入/输出(I/O)装置12: Input/Output (I/O) device

110:系统总线110: System bus

111:处理器111: Processor

112:随机存取存储器(RAM)/缓冲存储器112: Random Access Memory (RAM)/Cache

113:只读存储器(ROM)113: Read Only Memory (ROM)

114:数据传输接口114: data transmission interface

20:主机板20: Motherboard

201:随身盘201: Pen drive

202:存储卡202: memory card

203:固态硬盘203: SSD

204:无线存储器存储装置204: Wireless memory storage device

205:全球定位系统模块205: Global Positioning System Module

206:网络接口卡206: Network interface card

207:无线传输装置207: Wireless transmission device

208:键盘208: Keyboard

209:屏幕209: screen

210:喇叭210: Horn

30:存储器存储装置30: Memory storage device

31:主机系统31: Host system

32:SD卡32: SD card

33:CF卡33: CF card

34:嵌入式存储装置34: Embedded storage device

341:嵌入式多媒体卡341: Embedded multimedia card

342:嵌入式多芯片封装存储装置342: Embedded multi-chip package storage device

402:连接接口单元402: Connect the interface unit

404:存储器控制电路单元404: memory control circuit unit

406:可复写式非易失性存储器模块406: Rewritable non-volatile memory module

502:存储器管理电路502: memory management circuit

504:主机接口504: host interface

506:存储器接口506: memory interface

508:缓冲存储器508: buffer memory

510:电源管理电路510: power management circuit

512:错误检查与校正电路512: Error checking and correction circuit

310、320、330、340:通道310, 320, 330, 340: channel

312、322、332、342:第一区块面312, 322, 332, 342: the first block surface

314、324、334、344:第二区块面314, 324, 334, 344: the second block surface

410(0)~410(N)、420(0)~420(N)、430(0)~430(N)、440(0)~440(N)、450(0)~450(N)、460(0)~460(N)、470(0)~470(N)、480(0)~480(N):实体抹除单元410(0)~410(N), 420(0)~420(N), 430(0)~430(N), 440(0)~440(N), 450(0)~450(N), 460(0)~460(N), 470(0)~470(N), 480(0)~480(N): Entity erasing unit

VB0、VB1、VB2、VBn:超实体单元VB0, VB1, VB2, VBn: super solid elements

VB0、VB1:部分好超实体单元VB0, VB1: some good supersolid elements

450(0)、470(0)、440(1)、450(1)、460(N):坏实体抹除单元450(0), 470(0), 440(1), 450(1), 460(N): bad entity erase unit

440(0)、460(0):好实体抹除单元440(0), 460(0): good physical erasing unit

610(0)~680(N):逻辑地址610(0)~680(N): logical address

S1101:接收主机写入指令S1101: Receive host write command

S1103:根据可复写式非易失性存储器模块中多个好超实体单元与多个部分好超实体单元的个数比率从多个超实体单元选择出第一超实体单元集合的步骤S1103: A step of selecting a first set of super-substance units from a plurality of super-substance units according to the number ratio of multiple good super-substance units to a plurality of partial good super-substance units in the rewritable non-volatile memory module

S1105:根据多个好超实体单元的个数与多个部分好超实体单元的个数动态地更新个数比率的步骤S1105: A step of dynamically updating the number ratio according to the number of multiple good super-solid units and the number of multiple partial good super-solid units

S1107:根据可复写式非易失性存储器模块中好超实体单元与部分好超实体单元的个数比率从可复写式非易失性存储器模块除第一超实体单元集合以外的剩余超实体单元之中选择出第二超实体单元集合的步骤S1107: According to the ratio of the number of good super-substance units and some good super-substance units in the rewritable non-volatile memory module, from the remaining super-substance units in the rewritable non-volatile memory module except the first super-substance unit set The step of selecting the second set of super-solid units

S1109:将主机系统的数据写入至第一超实体单元集合的好实体抹除单元中的步骤S1109: the step of writing the data of the host system to the good physical erasing unit of the first super-physical unit set

S1111:将主机系统的数据继续写入至第二超实体单元集合的好实体抹除单元中,以回应主机写入指令的步骤S1111: Continue writing the data of the host system into the good physical erasing unit of the second super-physical unit set in response to the host write command

S1201:从多个超实体单元之中选择第一部分好超实体单元及第二部分好超实体单元的步骤S1201: the step of selecting the first part of good super-solid units and the second part of good super-solid units from multiple super-solid units

S1203:将第一部分好超实体单元的好实体抹除单元映射至第二部分好超实体单元的坏实体抹除单元的逻辑地址,第二部分好超实体单元的坏实体抹除单元不再映射至逻辑地址,其中,第一部分好超实体单元的好实体抹除单元与第二部分好超实体单元的坏实体抹除单元属于同一通道且属于同一区块面的步骤S1203: Map the good physical erasing units of the first good super-physical units to the logical addresses of the bad physical erasing units of the second good super-physical units, and no longer map the bad physical erasing units of the second good super-physical units To the logical address, wherein, the good physical erasing unit of the first part of the good super-physical unit and the bad physical erasing unit of the second part of the good super-physical unit belong to the same channel and belong to the same block plane

S1205:更新逻辑-实体映射表的步骤S1205: Steps for updating the logic-entity mapping table

S1301:将多个超实体单元至少分组为坏超实体单元、部分好超实体单元以及好超实体单元的步骤S1301: A step of grouping multiple super-solid units into at least bad super-solid units, some good super-solid units, and good super-solid units

S1303:对坏超实体单元、部分好超实体单元以及好超实体单元分别作标记的步骤S1303: the step of marking bad super-solid units, some good super-solid units and good super-solid units respectively

S1305:更新超实体单元伫列表的步骤S1305: Steps for updating the queue list of supersolid elements

S1307:依据超实体单元伫列表选择出第一超实体单元集合的步骤S1307: A step of selecting a first super-solid unit set according to the super-solid unit queue list

S1309:对第一超实体单元集合中的多个第一好超实体单元的个数及至少一个第一部分好超实体单元的个数计数的步骤S1309: A step of counting the number of multiple first good super-substance units and the number of at least one first part of good super-substance units in the first super-substance unit set

具体实施方式Detailed ways

一般而言,存储器存储装置(亦称,存储器存储系统)包括可复写式非易失性存储器模块与控制器(亦称,控制电路单元)。通常存储器存储装置是与主机系统一起使用,以使主机系统可将数据写入至存储器存储装置或从存储器存储装置中读取数据。Generally speaking, a memory storage device (also called a memory storage system) includes a rewritable non-volatile memory module and a controller (also called a control circuit unit). Typically memory storage devices are used with a host system such that the host system can write data to or read data from the memory storage device.

图2是根据一范例实施例所示出的主机系统、存储器存储装置及输入/输出(I/O)装置的示意图,并且图3是根据另一范例实施例所示出的主机系统、存储器存储装置及输入/输出(I/O)装置的示意图。2 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment, and FIG. 3 is a schematic diagram of a host system, a memory storage device, according to another exemplary embodiment. Schematic diagram of the device and input/output (I/O) devices.

请参照图2与图3,主机系统11一般包括处理器111、随机存取存储器(randomaccess memory,RAM)112、只读存储器(read only memory,ROM)113及数据传输接口114。处理器111、随机存取存储器112、只读存储器113及数据传输接口114皆电性连接至系统总线(system bus)110。Please refer to FIG. 2 and FIG. 3 , the host system 11 generally includes a processor 111 , a random access memory (random access memory, RAM) 112 , a read only memory (read only memory, ROM) 113 and a data transmission interface 114 . The processor 111 , random access memory 112 , ROM 113 and data transmission interface 114 are all electrically connected to a system bus 110 .

在本范例实施例中,主机系统11是通过数据传输接口114与存储器存储装置10电性连接。例如,主机系统11可经由数据传输接口114将数据写入至存储器存储装置10或从存储器存储装置10中读取数据。此外,主机系统11是通过系统总线110与I/O装置12电性连接。例如,主机系统11可经由系统总线110将输出信号传送至I/O装置12或从I/O装置12接收输入信号。In this exemplary embodiment, the host system 11 is electrically connected to the memory storage device 10 through the data transmission interface 114 . For example, the host system 11 can write data into the memory storage device 10 or read data from the memory storage device 10 via the data transmission interface 114 . In addition, the host system 11 is electrically connected to the I/O device 12 through the system bus 110 . For example, host system 11 may transmit output signals to or receive input signals from I/O devices 12 via system bus 110 .

在本范例实施例中,处理器111、随机存取存储器112、只读存储器113及数据传输接口114是可设置在主机系统11的主机板20上。数据传输接口114的数目可以是一或多个。通过数据传输接口114,主机板20可以经由有线或无线方式电性连接至存储器存储装置10。存储器存储装置10可例如是随身盘201、存储卡202、固态硬盘(Solid State Drive,SSD)203或无线存储器存储装置204。无线存储器存储装置204可例如是近距离无线通讯(NearField Communication Storage,NFC)存储器存储装置、无线传真(WiFi)存储器存储装置、蓝牙(Bluetooth)存储器存储装置或低功耗蓝牙存储器存储装置(例如,iBeacon)等以各式无线通讯技术为基础的存储器存储装置。此外,主机板20也可以通过系统总线110电性连接至全球定位系统(Global Positioning System,GPS)模块205、网络接口卡206、无线传输装置207、键盘208、屏幕209、喇叭210等各式I/O装置。例如,在一范例实施例中,主机板20可通过无线传输装置207存取无线存储器存储装置204。In this exemplary embodiment, the processor 111 , the random access memory 112 , the read-only memory 113 and the data transmission interface 114 can be disposed on the motherboard 20 of the host system 11 . The number of data transmission interfaces 114 may be one or more. Through the data transmission interface 114 , the motherboard 20 can be electrically connected to the memory storage device 10 via wires or wirelessly. The memory storage device 10 may be, for example, a flash drive 201 , a memory card 202 , a solid state drive (Solid State Drive, SSD) 203 or a wireless memory storage device 204 . The wireless memory storage device 204 can be, for example, a near field communication (NearField Communication Storage, NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device or a Bluetooth low energy storage device (for example, iBeacon) and other memory storage devices based on various wireless communication technologies. In addition, the main board 20 can also be electrically connected to a global positioning system (Global Positioning System, GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210 and other types of I via the system bus 110. /O device. For example, in an exemplary embodiment, the motherboard 20 can access the wireless memory storage device 204 through the wireless transmission device 207 .

在一范例实施例中,所提及的主机系统为可实质地与存储器存储装置配合以存储数据的任意系统。虽然在上述范例实施例中,主机系统是以电脑系统来作说明,但本揭示不限于此。图3是根据另一范例实施例所示出的主机系统与存储器存储装置的示意图。请参照图4,在另一范例实施例中,主机系统31也可以是数码相机、摄影机、通讯装置、音频播放器、视频播放器或平板电脑等系统,而存储器存储装置30可为其所使用的SD卡32、CF卡33或嵌入式存储装置34等各式非易失性存储器存储装置。嵌入式存储装置34包括嵌入式多媒体卡(embedded MMC,eMMC)341和/或嵌入式多芯片封装存储装置(embedded Multi ChipPackage,eMCP)342等各类型将存储器模块直接电性连接于主机系统的基板上的嵌入式存储装置。In an example embodiment, reference to a host system is substantially any system that can cooperate with a memory storage device to store data. Although in the above exemplary embodiments, the host system is described as a computer system, the disclosure is not limited thereto. FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment. Please refer to FIG. 4 , in another exemplary embodiment, the host system 31 can also be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 can be used for it. SD card 32, CF card 33 or embedded storage device 34 and other non-volatile memory storage devices. The embedded storage device 34 includes various types of substrates such as an embedded multimedia card (embedded MMC, eMMC) 341 and/or an embedded multi-chip package storage device (embedded Multi Chip Package, eMCP) 342, etc., directly electrically connecting the memory module to the host system. on the embedded storage device.

图5是根据一范例实施例所示出的主机系统与存储器存储装置的概要方块图。FIG. 5 is a schematic block diagram of a host system and a memory storage device according to an exemplary embodiment.

请参照图5,存储器存储装置10包括连接接口单元402、存储器控制电路单元404与可复写式非易失性存储器模块406。Referring to FIG. 5 , the memory storage device 10 includes a connection interface unit 402 , a memory control circuit unit 404 and a rewritable non-volatile memory module 406 .

在本范例实施例中,连接接口单元402是相容于安全数字(Secure Digital,SD)接口标准。然而,必须了解的是,本发明不限于此,连接接口单元402亦可以是符合序列先进附件(Serial Advanced Technology Attachment,SATA)标准、并列先进附件(ParallelAdvanced Technology Attachment,PATA)标准、电气和电子工程师协会(Institute ofElectrical and Electronic Engineers,IEEE)1394标准、高速周边零件连接接口(Peripheral Component Interconnect Express,PCI Express)标准、通用序列总线(Universal Serial Bus,USB)标准、超高速一代(Ultra High Speed-I,UHS-I)接口标准、超高速二代(Ultra High Speed-II,UHS-II)接口标准、存储棒(Memory Stick,MS)接口标准、多芯片封装(Multi-Chip Package)接口标准、多媒体存储卡(Multi Media Card,MMC)接口标准、嵌入式多媒体存储卡(Embedded Multimedia Card,eMMC)接口标准、通用快闪存储器(Universal Flash Storage,UFS)接口标准、嵌入式多芯片封装(embedded MultiChip Package,eMCP)接口标准、小型快闪(Compact Flash,CF)接口标准、整合式驱动电子接口(Integrated Device Electronics,IDE)标准或其他适合的标准。在本范例实施例中,连接接口单元402可与存储器控制电路单元404封装在一个芯片中,或者连接接口单元402是布设于一包含存储器控制电路单元的芯片外。In this exemplary embodiment, the connection interface unit 402 is compatible with the Secure Digital (SD) interface standard. However, it must be understood that the present invention is not limited thereto, and the connection interface unit 402 may also be a serial advanced attachment (Serial Advanced Technology Attachment, SATA) standard, a parallel advanced attachment (Parallel Advanced Technology Attachment, PATA) standard, electrical and electronic engineers Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, high-speed peripheral component connection interface (Peripheral Component Interconnect Express, PCI Express) standard, Universal Serial Bus (Universal Serial Bus, USB) standard, Ultra High Speed-I , UHS-I) interface standard, Ultra High Speed-II (UHS-II) interface standard, memory stick (Memory Stick, MS) interface standard, multi-chip package (Multi-Chip Package) interface standard, multimedia Memory card (Multi Media Card, MMC) interface standard, embedded multimedia memory card (Embedded Multimedia Card, eMMC) interface standard, universal flash memory (Universal Flash Storage, UFS) interface standard, embedded multichip package (embedded MultiChip Package) , eMCP) interface standard, Compact Flash (CF) interface standard, Integrated Device Electronics (IDE) standard, or other suitable standards. In this exemplary embodiment, the connection interface unit 402 and the memory control circuit unit 404 can be packaged in one chip, or the connection interface unit 402 is arranged outside a chip including the memory control circuit unit.

存储器控制电路单元404用以执行以硬件型式或韧件型式实作的多个逻辑门或控制指令,并且根据主机系统11的指令在可复写式非易失性存储器模块406中进行数据的写入、读取与抹除等操作。The memory control circuit unit 404 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware, and write data in the rewritable non-volatile memory module 406 according to the instructions of the host system 11 , read and erase operations.

可复写式非易失性存储器模块406是电性连接至存储器控制电路单元404,并且用以存储主机系统11所写入的数据。可复写式非易失性存储器模块406具有实体抹除单元(也称实体区块)410(0)~410(N)。例如,实体抹除单元410(0)~410(N)可属于同一个存储器晶粒(die)或者属于不同的存储器晶粒。每一实体抹除单元分别具有数个实体页面(也称实体程序化单元),其中属于同一个实体抹除单元的实体页面可被独立地写入且被同时地抹除。然而,必须了解的是,本发明不限于此,每一实体抹除单元是可由64个实体页面、256个实体页面或其他任意个实体页面所组成。The rewritable non-volatile memory module 406 is electrically connected to the memory control circuit unit 404 and used for storing data written by the host system 11 . The rewritable non-volatile memory module 406 has physical erasing units (also called physical blocks) 410(0)˜410(N). For example, the physical erase units 410(0)˜410(N) may belong to the same memory die or belong to different memory dies. Each physical erasing unit has several physical pages (also called physical programming units), wherein the physical pages belonging to the same physical erasing unit can be written independently and erased simultaneously. However, it must be understood that the present invention is not limited thereto, and each physical erasing unit may be composed of 64 physical pages, 256 physical pages or any other number of physical pages.

更详细来说,实体抹除单元为抹除的最小单位。亦即,每一实体抹除单元含有最小数目的一并被抹除的存储单元。实体程序化单元为程序化的最小单元。即,实体程序化单元为写入数据的最小单元。每一实体程序化单元通常包括数据位元区与冗余位元区。数据位元区包含多个实体存取地址用以存储使用者的数据,而冗余位元区用以存储系统的数据(例如,控制信息与错误更正码)。在本范例实施例中,每一个实体程序化单元的数据位元区中会包含8个实体存取地址,且一个实体存取地址的大小为512字节(byte)。然而,在其他范例实施例中,数据位元区中也可包含数目更多或更少的实体存取地址,本发明并不限制实体存取地址的大小以及个数。例如,在一范例实施例中,实体抹除单元为实体区块,并且实体程序化单元为实体页面或实体扇区,但本发明不以此为限。In more detail, the entity erasing unit is the smallest unit of erasing. That is, each physical erase unit contains the minimum number of memory cells to be erased together. Entity programming unit is the smallest unit of programming. That is, the entity programming unit is the smallest unit for writing data. Each physical programming unit generally includes a data bit field and a redundant bit field. The data bit area contains a plurality of physical access addresses for storing user data, and the redundant bit area is used for storing system data (eg, control information and error correction code). In this exemplary embodiment, the data bit area of each physical programming unit includes 8 physical access addresses, and the size of one physical access address is 512 bytes. However, in other exemplary embodiments, the data bit area may also include more or less physical access addresses, and the present invention does not limit the size and number of physical access addresses. For example, in an exemplary embodiment, the physical erasing unit is a physical block, and the physical programming unit is a physical page or a physical sector, but the invention is not limited thereto.

在本范例实施例中,可复写式非易失性存储器模块406为单阶存储单元(SingleLevel Cell,SLC)NAND型快闪存储器模块(即,一个存储单元中可存储1个数据位元的快闪存储器模块)。然而,本发明不限于此,可复写式非易失性存储器模块406亦可是多阶存储单元(Multi Level Cell,MLC)NAND型快闪存储器模块(即,一个存储单元中可存储2个数据位元的快闪存储器模块)、复数阶存储单元(Trinary Level Cell,TLC)NAND型快闪存储器模块(即,一个存储单元中可存储3个数据位元的快闪存储器模块)或其他具有相同特性的存储器模块。In this exemplary embodiment, the rewritable non-volatile memory module 406 is a single-level memory cell (SingleLevel Cell, SLC) NAND flash memory module (that is, a flash memory unit that can store 1 data bit. flash memory module). However, the present invention is not limited thereto, and the rewritable non-volatile memory module 406 may also be a multi-level memory cell (Multi Level Cell, MLC) NAND flash memory module (that is, two data bits can be stored in one memory cell) Elementary flash memory module), complex-order storage unit (Trinary Level Cell, TLC) NAND flash memory module (that is, a flash memory module that can store 3 data bits in one storage unit) or other with the same characteristics memory module.

图6是根据一范例实施例所示出的存储器控制电路单元的概要方块图。FIG. 6 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment.

请参照图6,存储器控制电路单元404包括存储器管理电路502、主机接口504与存储器接口506。Referring to FIG. 6 , the memory control circuit unit 404 includes a memory management circuit 502 , a host interface 504 and a memory interface 506 .

存储器管理电路502用以控制存储器控制电路单元404的整体运作。具体来说,存储器管理电路502具有多个控制指令,并且在存储器存储装置10运作时,此些控制指令会被执行以进行数据的写入、读取与抹除等运作。The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404 . Specifically, the memory management circuit 502 has a plurality of control instructions, and when the memory storage device 10 is operating, these control instructions are executed to perform operations such as writing, reading, and erasing data.

在本范例实施例中,存储器管理电路502的控制指令是以韧件型式来实作。例如,存储器管理电路502具有微处理器单元(未示出)与只读存储器(未示出),并且此些控制指令是被烧录至此只读存储器中。当存储器存储装置10运作时,此些控制指令会由微处理器单元来执行以进行数据的写入、读取与抹除等运作。In this exemplary embodiment, the control commands of the memory management circuit 502 are implemented in the form of firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

在本发明另一范例实施例中,存储器管理电路502的控制指令亦可以程序码型式存储于可复写式非易失性存储器模块406的特定区域(例如,存储器模块中专用于存放系统数据的系统区)中。此外,存储器管理电路502具有微处理器单元(未示出)、只读存储器(未示出)及随机存取存储器(未示出)。特别是,此只读存储器具有驱动码,并且当存储器控制电路单元404被致能时,微处理器单元会先执行此驱动码段来将存储于可复写式非易失性存储器模块406中的控制指令载入至存储器管理电路502的随机存取存储器中。之后,微处理器单元会运转此些控制指令以进行数据的写入、读取与抹除等运作。In another exemplary embodiment of the present invention, the control instructions of the memory management circuit 502 can also be stored in a specific area of the rewritable non-volatile memory module 406 in the form of program codes (for example, a system dedicated to storing system data in the memory module) area). In addition, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a driver code, and when the memory control circuit unit 404 is enabled, the microprocessor unit will first execute the driver code segment to store the data stored in the rewritable non-volatile memory module 406 The control instructions are loaded into the random access memory of the memory management circuit 502 . Afterwards, the microprocessor unit will execute these control instructions to perform operations such as writing, reading and erasing data.

此外,在本发明另一范例实施例中,存储器管理电路502的控制指令亦可以一硬件型式来实作。例如,存储器管理电路502包括微控制器、存储单元管理电路、存储器写入电路、存储器读取电路、存储器抹除电路与数据处理电路。存储单元管理电路、存储器写入电路、存储器读取电路、存储器抹除电路与数据处理电路是电性连接至微控制器。其中,存储单元管理电路用以管理可复写式非易失性存储器模块406的实体抹除单元;存储器写入电路用以对可复写式非易失性存储器模块406下达写入指令以将数据写入至可复写式非易失性存储器模块406中;存储器读取电路用以对可复写式非易失性存储器模块406下达读取指令以从可复写式非易失性存储器模块406中读取数据;存储器抹除电路用以对可复写式非易失性存储器模块406下达抹除指令以将数据从可复写式非易失性存储器模块406中抹除;而数据处理电路用以处理欲写入至可复写式非易失性存储器模块406的数据以及从可复写式非易失性存储器模块406中读取的数据。In addition, in another exemplary embodiment of the present invention, the control instructions of the memory management circuit 502 can also be implemented in a hardware form. For example, the memory management circuit 502 includes a microcontroller, a memory unit management circuit, a memory writing circuit, a memory reading circuit, a memory erasing circuit and a data processing circuit. The storage unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are electrically connected to the microcontroller. Wherein, the storage unit management circuit is used to manage the physical erasing unit of the rewritable non-volatile memory module 406; the memory writing circuit is used to issue a write command to the rewritable non-volatile memory module 406 to write data into the rewritable nonvolatile memory module 406; the memory read circuit is used to issue a read instruction to the rewritable nonvolatile memory module 406 to read from the rewritable nonvolatile memory module 406 Data; the memory erasing circuit is used to issue an erase command to the rewritable non-volatile memory module 406 to erase data from the rewritable non-volatile memory module 406; and the data processing circuit is used to process the data to be written Data input to the rewritable non-volatile memory module 406 and data read from the rewritable non-volatile memory module 406.

主机接口504是电性连接至存储器管理电路502并且用以电性连接至连接接口单元402,以接收与识别主机系统11所传送的指令与数据。也就是说,主机系统11所传送的指令与数据会通过主机接口504来传送至存储器管理电路502。在本范例实施例中,主机接口504是相容于SATA标准。然而,必须了解的是本发明不限于此,主机接口504亦可以是相容于PATA标准、IEEE 1394标准、PCI Express标准、USB标准、UHS-I接口标准、UHS-II接口标准、SD标准、MS标准、MMC标准、CF标准、IDE标准或其他适合的数据传输标准。The host interface 504 is electrically connected to the memory management circuit 502 and is used to electrically connect to the connection interface unit 402 to receive and identify commands and data transmitted by the host system 11 . That is to say, the commands and data sent by the host system 11 are sent to the memory management circuit 502 through the host interface 504 . In this exemplary embodiment, the host interface 504 is compatible with the SATA standard. However, it must be understood that the present invention is not limited thereto, and the host interface 504 can also be compatible with PATA standard, IEEE 1394 standard, PCI Express standard, USB standard, UHS-I interface standard, UHS-II interface standard, SD standard, MS standard, MMC standard, CF standard, IDE standard or other suitable data transmission standards.

存储器接口506是电性连接至存储器管理电路502并且用以存取可复写式非易失性存储器模块406。也就是说,欲写入至可复写式非易失性存储器模块406的数据会经由存储器接口506转换为可复写式非易失性存储器模块406所能接受的格式。The memory interface 506 is electrically connected to the memory management circuit 502 and used for accessing the rewritable non-volatile memory module 406 . That is to say, the data to be written into the rewritable nonvolatile memory module 406 will be converted into a format acceptable to the rewritable nonvolatile memory module 406 via the memory interface 506 .

在一范例实施例中,存储器控制电路单元404还包括缓冲存储器508、电源管理电路510与错误检查与校正电路512。In an exemplary embodiment, the memory control circuit unit 404 further includes a buffer memory 508 , a power management circuit 510 and an error checking and correction circuit 512 .

缓冲存储器508是电性连接至存储器管理电路502并且用以暂存来自于主机系统11的数据与指令或来自于可复写式非易失性存储器模块406的数据。The buffer memory 508 is electrically connected to the memory management circuit 502 and used for temporarily storing data and instructions from the host system 11 or data from the rewritable non-volatile memory module 406 .

电源管理电路510是电性连接至存储器管理电路502并且用以控制存储器存储装置10的电源。The power management circuit 510 is electrically connected to the memory management circuit 502 and used to control the power of the memory storage device 10 .

错误检查与校正电路512是电性连接至存储器管理电路502并且用以执行错误检查与校正程序以确保数据的正确性。具体来说,当存储器管理电路502从主机系统11中接收到写入指令时,错误检查与校正电路512会为对应此写入指令的数据产生对应的错误检查与校正码(Error Checking and Correcting Code,ECC Code),并且存储器管理电路502会将对应此写入指令的数据与对应的错误检查与校正码写入至可复写式非易失性存储器模块406中。之后,当存储器管理电路502从可复写式非易失性存储器模块406中读取数据时会同时读取此数据对应的错误检查与校正码,并且错误检查与校正电路512会根据此错误检查与校正码对所读取的数据执行错误检查与校正程序。The error checking and correcting circuit 512 is electrically connected to the memory management circuit 502 and used for executing error checking and correcting procedures to ensure the correctness of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correcting circuit 512 will generate a corresponding error checking and correcting code (Error Checking and Correcting Code) for the data corresponding to the write command. , ECC Code), and the memory management circuit 502 will write the data corresponding to the write command and the corresponding ECC code into the rewritable non-volatile memory module 406 . Afterwards, when the memory management circuit 502 reads data from the rewritable non-volatile memory module 406, it will simultaneously read the error checking and correction code corresponding to the data, and the error checking and correction circuit 512 will read the error checking and correction code according to the error checking and correction code. The correction code performs error checking and correction procedures on the read data.

在本范例实施例中,错误检查与校正电路512是以低密度奇偶检查码(lowdensity parity code,LDPC)来实作。然而,在另一范例实施例中,错误检查与校正电路512也可以BCH码、回旋码(convolutional code)、涡轮码(turbo code)、比特翻转(bitflipping)等编码/解码算法来实作。In this exemplary embodiment, the error checking and correcting circuit 512 is implemented with a low density parity code (LDPC). However, in another exemplary embodiment, the error checking and correcting circuit 512 can also be implemented with encoding/decoding algorithms such as BCH codes, convolutional codes, turbo codes, and bit flipping.

具体来说,存储器管理电路502会依据所接收的数据及对应的错误检查与校正码(以下亦称为错误校正码)来产生错误校正码框(ECC Frame)并且将错误校正码框写入至可复写式非易失性存储器模块406中。之后,当存储器管理电路502从可复写式非易失性存储器模块406读取数据时,错误检查与校正电路512会根据错误校正码框中的错误校正码来验证所读取的数据的正确性。Specifically, the memory management circuit 502 will generate an error correction code frame (ECC frame) according to the received data and the corresponding error checking and correction code (hereinafter referred to as error correction code) and write the error correction code frame into In the rewritable non-volatile memory module 406 . Afterwards, when the memory management circuit 502 reads data from the rewritable non-volatile memory module 406, the error checking and correction circuit 512 will verify the correctness of the read data according to the error correction code in the error correction code box .

以下描述存储器管理电路502、主机接口504与存储器接口506、缓冲存储器508、电源管理电路510与错误检查与校正电路512所执行的操作,亦可参考为由存储器控制电路单元404所执行。The operations performed by the memory management circuit 502 , the host interface 504 and the memory interface 506 , the buffer memory 508 , the power management circuit 510 and the error checking and correction circuit 512 are described below, which may also be referred to as being performed by the memory control circuit unit 404 .

图7是根据一范例实施例所示出的管理超实体单元的范例示意图。Fig. 7 is an exemplary schematic diagram of a management super-entity unit shown according to an exemplary embodiment.

必须了解的是,在此描述可复写式非易失性存储器模块406的实体抹除单元的运作时,以“分组”等词来操作实体抹除单元是逻辑上的概念。也就是说,可复写式非易失性存储器模块的实体抹除单元的实际位置并未更动,而是逻辑上对可复写式非易失性存储器模块的实体抹除单元进行操作。It must be understood that when describing the operation of the physical erasing unit of the rewritable non-volatile memory module 406 , operating the physical erasing unit with words such as “grouping” is a logical concept. That is to say, the actual position of the physical erasing unit of the rewritable non-volatile memory module is not changed, but the physical erasing unit of the rewritable non-volatile memory module is logically operated.

请参照图7,可复写式非易失性存储器模块406包括分别属于通道310、通道320、通道330以及通道340(以下简称通道310~340)且分别属于第一区块面312、第一区块面322、第一区块面332、第一区块面342(以下简称第一区块面312~342)、第二区块面314、第二区块面324、第二区块面334、第二区块面344(以下简称第二区块面314~344)的多个实体抹除单元组成的多个超实体单元。例如,通道310~340分别地为不同通道,第一区块面312~342与第二区块面314~344分别地为不同的区块面。Please refer to FIG. 7 , the rewritable non-volatile memory module 406 includes channels 310, 320, 330 and 340 (hereinafter referred to as channels 310-340) and respectively belonging to the first block surface 312 and the first area. Block surface 322, first block surface 332, first block surface 342 (hereinafter referred to as first block surface 312-342), second block surface 314, second block surface 324, second block surface 334 1. A plurality of super-solid units composed of a plurality of physical erasing units of the second block plane 344 (hereinafter referred to as the second block plane 314-344). For example, the channels 310 - 340 are respectively different channels, and the first block planes 312 - 342 and the second block planes 314 - 344 are respectively different block planes.

其中,实体抹除单元410(0)~410(N)与实体抹除单元420(0)~420(N)分别属于通道310的第一区块面312与第二区块面314。实体抹除单元430(0)~430(N)与实体抹除单元440(0)~440(N)属于通道320的第一区块面322与第二区块面324。实体抹除单元450(0)~450(N)与实体抹除单元460(0)~460(N)属于通道330的第一区块面332与第二区块面334。并且实体抹除单元470(0)~470(N)与实体抹除单元480(0)~480(N)属于通道340的第一区块面342与第二区块面344。Wherein, the physical erasing units 410(0)˜410(N) and the physical erasing units 420(0)˜420(N) belong to the first block plane 312 and the second block plane 314 of the channel 310 respectively. The physical erasing units 430 ( 0 )˜ 430 (N) and the physical erasing units 440 ( 0 )˜ 440 (N) belong to the first block plane 322 and the second block plane 324 of the channel 320 . The physical erasing units 450 ( 0 )˜ 450 (N) and the physical erasing units 460 ( 0 )˜ 460 (N) belong to the first block plane 332 and the second block plane 334 of the channel 330 . Moreover, the physical erasing units 470 ( 0 )˜ 470 (N) and the physical erasing units 480 ( 0 )˜ 480 (N) belong to the first block plane 342 and the second block plane 344 of the channel 340 .

再请参照图7,而属于不同通道且属于不同区块面的多个实体抹除单元可以组成一个虚拟区块(Virtual Block,VB)(在此亦称为超实体单元)。例如,实体抹除单元410(0)、实体抹除单元420(0)、实体抹除单元430(0)、实体抹除单元440(0)、实体抹除单元450(0)、实体抹除单元460(0)、实体抹除单元470(0)及实体抹除单元480(0)(以下简称实体抹除单元410(0)~480(0))可以组成超实体单元VB0。同样地,实体抹除单元410(1)~480(1)可以组成超实体单元VB1。实体抹除单元410(2)~480(2)可以组成超实体单元VB2。以此类推,实体抹除单元410(N)~480(N)可以组成超实体单元VBn。Referring to FIG. 7 again, multiple physical erasing units belonging to different channels and different block planes can form a virtual block (Virtual Block, VB) (also referred to as a super-physical unit herein). For example, entity erase unit 410(0), entity erase unit 420(0), entity erase unit 430(0), entity erase unit 440(0), entity erase unit 450(0), entity erase unit The unit 460(0), the physical erasing unit 470(0) and the physical erasing unit 480(0) (hereinafter referred to as the physical erasing units 410(0)˜480(0)) can form a super-physical unit VB0. Likewise, the physical erasing units 410(1)-480(1) can form a super-physical unit VB1. The physical erasing units 410(2)-480(2) can form a super-physical unit VB2. By analogy, the physical erasing units 410(N)˜480(N) can form a super-physical unit VBn.

于一范例实施例中,超实体单元VB0包括有坏实体抹除单元450(0)以及坏实体抹除单元470(0),超实体单元VB1包括有坏实体抹除单元440(1)以及坏实体抹除单元450(1),超实体单元VBn包括有坏实体抹除单元460(N)。也就是说,超实体单元VB0、超实体单元VB1以及超实体单元VBn均包括至少一个坏实体抹除单元,仅部分实体抹除单元可用,因此,超实体单元VB0、超实体单元VB1以及超实体单元VBn可视为部分好超实体单元。而超实体单元VB2中包括的实体抹除单元410(2)~480(2)均为可用的好实体抹除单元,超实体单元VB2可视为好超实体单元。In an exemplary embodiment, the super-physical unit VB0 includes a bad physical erase unit 450(0) and a bad physical erase unit 470(0), and the super-physical unit VB1 includes a bad physical erase unit 440(1) and a bad physical erase unit 440(1). The physical erase unit 450(1), super-physical unit VBn includes a bad physical erase unit 460(N). That is to say, the super entity unit VB0, the super entity unit VB1 and the super entity unit VBn all include at least one bad entity erasing unit, and only part of the entity erasing units are available. Therefore, the super entity unit VB0, the super entity unit VB1 and the super entity Unit VBn can be regarded as a part of good super-solid unit. The physical erasing units 410( 2 )- 480 ( 2 ) included in the super-solid unit VB2 are all available good physical erasing units, and the super-solid unit VB2 can be regarded as a good super-physical unit.

图8是根据一范例实施例所示出的超实体单元中的实体抹除单元与逻辑地址映射的范例示意图,并且图9是根据一范例实施例所示出的超实体单元中的实体抹除单元与逻辑地址重新映射的范例示意图。Fig. 8 is an exemplary schematic diagram of physical erasing unit and logical address mapping in a super-physical unit according to an exemplary embodiment, and Fig. 9 is a physical erasing in a super-physical unit according to an exemplary embodiment Example diagram of cell and logical address remapping.

请参照图8。在一范例实施例中,存储器管理电路502会配置逻辑地址610(0)~680(N)给主机系统11,以映射至实体抹除单元410(0)~480(N),以利于存储数据的实体抹除单元进行数据存取。特别是,主机系统11会通过逻辑地址610(0)~680(N)来存取实体抹除单元410(0)~480(N)中的数据。此外,存储器管理电路502会建立逻辑-实体映射表(logical-physical mapping table),以记录逻辑地址与实体抹除单元之间的映射关系。此逻辑-实体映射表还可以例如是记录逻辑地址与实体程序化单元、逻辑程序化单元与实体程序化单元和/或逻辑程序化单元与实体抹除单元之间的映射关系等各种逻辑与实体的对应关系,本发明不加以限制。Please refer to Figure 8. In an exemplary embodiment, the memory management circuit 502 allocates the logical addresses 610(0)-680(N) to the host system 11 to map to the physical erasing units 410(0)-480(N) to facilitate data storage The physical erasing unit performs data access. In particular, the host system 11 accesses the data in the physical erasing units 410(0)˜480(N) through the logical addresses 610(0)˜680(N). In addition, the memory management circuit 502 establishes a logical-physical mapping table to record the mapping relationship between logical addresses and physical erasing units. This logic-entity mapping table can also record various logical and The correspondence between entities is not limited in the present invention.

一般来说,在存储器存储装置10出厂之前,制造商会使用量产工具(MassProduction tool,MP tool)来对存储器存储装置10执行开卡操作,以执行初始化动作。Generally, before the memory storage device 10 leaves the factory, the manufacturer will use a mass production tool (Mass Production tool, MP tool) to perform a card opening operation on the memory storage device 10 to perform an initialization operation.

请参照图9,存储器存储装置10执行开卡操作时,会利用重新映射(即remap)的方式来将多个超实体单元VB0~VBn至少分组为坏超实体单元、部分好超实体单元以及好超实体单元,从而排列出尽可能多的好超实体单元来使用,延长存储器存储装置10的使用寿命。在一范例实施例中,存储器控制电路单元404从多个超实体单元VB0~VBn之中选择第一部分好超实体单元(例如部分好超实体单元VB0)及第二部分好超实体单元(例如部分好超实体单元VB1)。例如,部分好超实体单元VB0包括坏实体抹除单元450(0)以及坏实体抹除单元470(0),部分好超实体单元VB1包括坏实体抹除单元440(1)以及坏实体抹除单元450(1)。存储器控制电路单元404将部分好超实体单元VB0的好实体抹除单元440(0)映射至部分好超实体单元VB1的坏实体抹除单元440(1)的逻辑地址640(1)。部分好超实体单元VB1的坏实体抹除单元440(1)不再映射至逻辑地址,并且部分好超实体单元VB0的好实体抹除单元440(0)与部分好超实体单元VB1的坏实体抹除单元440(1)属于同一通道320且属于同一区块面324。此外,存储器控制电路单元404更新逻辑-实体映射表。Please refer to FIG. 9 , when the memory storage device 10 performs a card opening operation, it will use remapping (ie remap) to group multiple super-entity units VB0-VBn into at least bad super-entity units, some good super-entity units, and good super-entity units. The super-solid units are arranged to use as many good super-solid units as possible, so as to prolong the service life of the memory storage device 10 . In an exemplary embodiment, the memory control circuit unit 404 selects a first partial good superphysical unit (for example, a partial good superphysical unit VB0 ) and a second partial good superphysical unit (for example, a partial Good super solid element VB1). For example, part of the good super-physical unit VB0 includes the bad physical erase unit 450(0) and the bad physical erase unit 470(0), and the partial good super-physical unit VB1 includes the bad physical erase unit 440(1) and the bad physical erase unit 440(1). Unit 450(1). The memory control circuit unit 404 maps the good physical erase unit 440(0) of the partial good super-physical unit VB0 to the logical address 640(1) of the bad physical erase unit 440(1) of the partial good super-physical unit VB1. The bad physical erased unit 440(1) of the partially good superphysical unit VB1 is no longer mapped to a logical address, and the good physical erased unit 440(0) of the partially good superphysical unit VB0 is identical to the bad physical unit of the partially good superphysical unit VB1 The erase units 440( 1 ) belong to the same channel 320 and belong to the same block plane 324 . In addition, the memory control circuit unit 404 updates the logic-entity mapping table.

同样地,存储器控制电路单元404从多个超实体单元VB0~VBn之中选择第三部分好超实体单元(例如部分好超实体单元VBn),存储器控制电路单元404将第一部分好超实体单元(例如部分好超实体单元VB0)的好实体抹除单元460(0)映射至部分好超实体单元VBn的坏实体抹除单元460(N)的逻辑地址660(N)。部分好超实体单元VBn的坏实体抹除单元460(N)不再映射至逻辑地址,并且部分好超实体单元VB0的好实体抹除单元460(0)与部分好超实体单元VBn的坏实体抹除单元460(N)属于同一通道330且属于同一区块面334。此外,存储器控制电路单元404更新逻辑-实体映射表。Similarly, the memory control circuit unit 404 selects a third part of good super-entity units (such as a part of good super-entity units VBn) from a plurality of super-entity units VB0-VBn, and the memory control circuit unit 404 selects the first part of good super-entity units ( For example, the good physical erase unit 460(0) of the partial good super-physical unit VB0) is mapped to the logical address 660(N) of the bad physical erase unit 460(N) of the partial good super-physical unit VBn. The bad physical erased unit 460(N) of the partial good superphysical unit VBn is no longer mapped to a logical address, and the good physical erased unit 460(0) of the partial good superphysical unit VB0 is the same as the bad physical unit 460(0) of the partial good superphysical unit VBn Erase units 460(N) belong to the same channel 330 and belong to the same block plane 334 . In addition, the memory control circuit unit 404 updates the logic-entity mapping table.

在上述范例实施例中,存储器控制电路单元404利用重新映射的方式将坏实体抹除单元(例如坏实体抹除单元440(1)、坏实体抹除单元460(N))集中在超实体单元VB0中,并且存储器控制电路单元404会依据超实体单元VB0~VBn中每一个超实体单元的坏实体抹除单元的个数与实体抹除单元个数的比例将超实体单元VB0~VBn至少分组为坏超实体单元、部分好超实体单元以及好超实体单元。In the above exemplary embodiment, the memory control circuit unit 404 gathers the bad physical erase units (such as the bad physical erase unit 440(1), the bad physical erase unit 460(N)) in the super-physical unit by means of remapping VB0, and the memory control circuit unit 404 will at least group the super-physical units VB0-VBn into groups according to the ratio of the number of bad physical erasing units of each super-physical unit in the super-physical units VB0-VBn to the number of physical erasing units are bad super-solid elements, some good super-solid elements and good super-solid elements.

一般来说,当一个超实体单元的坏实体抹除单元的个数与一个超实体单元的实体抹除单元的总个数的比例超出四分之一时,可以判定此超实体单元为坏超实体单元。也就是说,此超实体单元不可用。若超实体单元至少包括一个坏实体抹除单元但坏实体抹除单元的个数少于四分之一的实体抹除单元的总个数时,可以判定此超实体单元为部分好超实体单元。若超实体单元不包括坏实体抹除单元,则可以判定此超实体单元为好超实体单元。Generally speaking, when the ratio of the number of bad entity erasing units of a super entity unit to the total number of entity erasing units of a super entity unit exceeds 1/4, it can be determined that this super entity unit is a bad super entity unit. solid unit. That is, this supersolid element is not available. If the super-solid unit includes at least one bad entity erasing unit but the number of bad entity erasing units is less than a quarter of the total number of entity erasing units, it can be determined that this super-solid unit is partly good super-solid unit . If the super-physical unit does not include the bad-physical erasing unit, it can be determined that the super-physical unit is a good super-physical unit.

此外,存储器控制电路单元404会对坏超实体单元、部分好超实体单元以及好超实体单元分别作标记,并更新超实体单元伫列表。在此,超实体单元伫列表是用以记录代表超实体单元的信息,例如可以是超实体单元的标记、编号、识别值或是其实体抹除单元所对应的逻辑地址。也就是说,存储器存储装置10执行开卡操作重新映射之后,其信息对应记录在更新后的超实体单元伫列表中。在一范例实施例中,存储器控制电路单元404可以依序将坏超实体单元、部分好超实体单元以及好超实体单元的信息记录在超实体单元伫列表,为便于存储器控制电路单元404选取。In addition, the memory control circuit unit 404 marks the bad super-solid units, part of the good super-solid units and good super-solid units respectively, and updates the super-solid unit queue list. Here, the super-physical unit queue table is used to record the information representing the super-physical unit, for example, it may be the label, serial number, identification value of the super-physical unit or the logical address corresponding to its physical erasing unit. That is to say, after the memory storage device 10 executes the remapping of the opening operation, its information is correspondingly recorded in the updated super-physical unit queue table. In an exemplary embodiment, the memory control circuit unit 404 may sequentially record information of bad superphysical units, some good superphysical units, and good superphysical units in the superphysical unit queue table for the convenience of the memory control circuit unit 404 to select.

在一范例实施例中,存储器控制电路单元404依据超实体单元伫列表选择出第一超实体单元集合、第二超实体单元集合等多个超实体单元集合,并且同时对超实体单元集合中的多个好超实体单元的个数及至少一个部分好超实体单元的个数计数,根据多个好超实体单元的个数与多个部分好超实体单元的个数动态地更新个数比率,以使得第一超实体单元集合包括按个数比率选择出的好超实体单元及部分好超实体单元,第二超实体单元集合包括按更新的个数比率选择出的好超实体单元及部分好超实体单元,以此类推,直至选择出多个超实体单元集合。In an exemplary embodiment, the memory control circuit unit 404 selects a plurality of super-physical unit sets such as the first super-physical unit set and the second super-physical unit set according to the super-physical unit queue table, and simultaneously selects the super-physical unit sets in the super-physical unit set The number of multiple good super-substance units and the number of at least one part of good super-substance units are counted, and the number ratio is dynamically updated according to the number of multiple good super-substance units and the number of multiple partial good super-substance units, In order to make the first super-substance unit set include the good super-substance unit and some good super-substance units selected according to the number ratio, the second super-substance unit collection includes the good super-substance unit and part of the good super-substance unit selected according to the updated number ratio. Super-solid units, and so on, until multiple sets of super-solid units are selected.

举例而言,可复写式非易失性存储器模块406包括1000个超实体单元,其中好超实体单元为980个,而部分好超实体单元为20个。存储器控制电路单元404根据可复写式非易失性存储器模块406中好超实体单元与部分好超实体单元的个数比率从多个超实体单元VB0~VBn中选择出第一超实体单元集合。换句话说,可复写式非易失性存储器模块406中好超实体单元与部分好超实体单元的个数比率为49:1,存储器控制电路单元404从多个超实体单元VB0~VBn的好超实体单元中选择49个好超实体单元,再从多个超实体单元VB0~VBn的部分好超实体单元中选择1个部分好超实体单元。此49个好超实体单元与1个部分好超实体单元构成第一超实体单元集合(例如超实体单元VB0~VB49,其中超实体单元VB0~VB48为好超实体单元,超实体单元VB49为部分好超实体单元)。存储器控制电路单元404再继续从剩余超实体单元之中选择出第二超实体单元集合,存储器控制电路单元404根据可复写式非易失性存储器模块406中除第一超实体单元集合以外的剩余超实体单元之中的多个好超实体单元的个数与多个部分好超实体单元的个数动态地更新个数比率,并且根据更新的个数比率从可复写式非易失性存储器模块406中除第一超实体单元集合以外的剩余超实体单元之中选择出第二超实体单元集合。也就是说,此时,可复写式非易失性存储器模块406中除第一超实体单元集合以外的剩余超实体单元之中的多个好超实体单元的个数与多个部分好超实体单元的个数分别为931个与19个,更新的个数比率为49:1,存储器控制电路单元404继续从剩余的超实体单元VB50~VBn的好超实体单元中选择49个好超实体单元,再从超实体单元VB50~VBn的部分好超实体单元中选择1个部分好超实体单元。同样地,此49个好超实体单元与1个部分好超实体单元构成第二超实体单元集合(例如超实体单元VB50~VB99,其中超实体单元VB50~VB98为好超实体单元,超实体单元VB99为部分好超实体单元)。以此类推,存储器控制电路单元404将多个超实体单元VB0~VBn选择出多个超实体单元集合,并且将主机系统的数据依序写入至选择出的多个超实体单元集合的好实体抹除单元中,上述动态地更新个数比率是由于可复写式非易失性存储器模块406中的好超实体单元会因程序化操作而变为部分好超实体单元,甚至会变为坏超实体单元,因此,在写入数据的过程中,好超实体单元的个数会逐渐减少,部分好超实体单元的个数会逐渐增加。For example, the rewritable non-volatile memory module 406 includes 1000 superphysical units, including 980 good superphysical units and 20 partial good superphysical units. The memory control circuit unit 404 selects a first set of super-physical units from the plurality of super-physical units VB0 -VBn according to the ratio of good super-physical units to some good super-physical units in the rewritable non-volatile memory module 406 . In other words, the ratio of the number of good super-physical units to some good super-physical units in the rewritable non-volatile memory module 406 is 49:1, and the memory control circuit unit 404 is good from a plurality of super-physical units VB0-VBn. Select 49 good super-solid units among the super-solid units, and then select one partial good super-solid unit from some good super-solid units of multiple super-solid units VB0-VBn. These 49 good super-substance units and 1 part good super-substance units constitute the first super-substance unit set (such as super-substance units VB0~VB49, wherein supersubstance units VB0~VB48 are good supersubstance units, and supersubstance unit VB49 is a part good supersolid element). The memory control circuit unit 404 continues to select the second set of super-entity units from the remaining super-entity units, and the memory control circuit unit 404 selects the second set of super-entity units according to the remaining The number of a plurality of good super-solid units among the super-solid units and the number of a plurality of good super-solid units dynamically update the number ratio, and according to the updated number ratio from the rewritable non-volatile memory module In step 406, a second set of super-physical units is selected from the remaining super-physical units except the first set of super-physical units. That is to say, at this moment, in the rewritable non-volatile memory module 406, the number of a plurality of good superentity units among the remaining superentity units except the first superentity unit set and a plurality of partial good superentity The number of units is 931 and 19 respectively, and the ratio of the updated number is 49:1. The memory control circuit unit 404 continues to select 49 good super-solid units from the good super-solid units of the remaining super-solid units VB50~VBn , and then select one partial good super-solid unit from the partial good super-solid units of super-solid units VB50~VBn. Equally, these 49 good super-substance units and 1 part good super-substance units constitute the second super-substance unit set (such as super-substance units VB50~VB99, wherein supersubstance units VB50~VB98 are good supersubstance units, supersubstance units VB99 is part of the good super-solid element). By analogy, the memory control circuit unit 404 selects a plurality of sets of super-entity units from a plurality of super-entity units VB0-VBn, and sequentially writes the data of the host system into good entities of the selected sets of super-entity units. In the erasing unit, the above-mentioned dynamic update number ratio is because the good super-physical unit in the rewritable non-volatile memory module 406 will become part of the good super-physical unit due to the programming operation, or even become a bad super-physical unit. Therefore, in the process of writing data, the number of good super-solid units will gradually decrease, and the number of some good super-solid units will gradually increase.

图10是一范例实施例中单位时间内快闪存储器的存取速度平稳的示意图。FIG. 10 is a schematic diagram of a stable access speed of the flash memory per unit time in an exemplary embodiment.

请参照图10,存储器控制电路单元404将多个超实体单元VB0~VBn中的好超实体单元与部分好超实体单元以固定的比例(个数比率)选择出多个超实体单元集合来使用,避免了过多的部分好超实体单元集中在某一时刻被使用,使得可复写式非易失性存储器模块406中的实体抹除单元使用次数较为平均,并且存取速度较为平稳。Please refer to FIG. 10 , the memory control circuit unit 404 selects a plurality of super-solid unit sets from good super-solid units and some good super-solid units in a plurality of super-solid units VB0-VBn at a fixed ratio (number ratio) for use. , avoiding too many good super-physical units being used concentratedly at a certain moment, so that the times of use of the physical erasing units in the rewritable non-volatile memory module 406 are relatively average, and the access speed is relatively stable.

值得一提的是,虽然本发明范例实施例是以包括4个通道、2个区块面的可复写式非易失性存储器模块406为例来描述,但本发明不限于此。在其他范例实施例中,可复写式非易失性存储器模块406也可以包括更多或更少的通道或者更多或更少的区块面。It should be noted that although the exemplary embodiment of the present invention is described by taking the rewritable non-volatile memory module 406 including 4 channels and 2 block planes as an example, the present invention is not limited thereto. In other exemplary embodiments, the rewritable non-volatile memory module 406 may also include more or less channels or more or less block planes.

图11是根据一范例实施例所示出的存储器管理方法的流程图。Fig. 11 is a flow chart of a memory management method according to an exemplary embodiment.

请参照图11,在步骤S1101中,存储器控制电路单元404接收主机写入指令。Referring to FIG. 11 , in step S1101 , the memory control circuit unit 404 receives a host write command.

在步骤S1103中,存储器控制电路单元404根据可复写式非易失性存储器模块406中多个好超实体单元与多个部分好超实体单元的个数比率从多个超实体单元选择出第一超实体单元集合,其中第一超实体单元集合包括按个数比率从多个超实体单元选择出的多个第一好超实体单元及至少一个第一部分好超实体单元。In step S1103, the memory control circuit unit 404 selects the first super-solid unit from the multiple super-solid units according to the ratio of the number of good super-solid units in the rewritable non-volatile memory module 406 to a plurality of partial good super-solid units. A set of super-physical units, wherein the first set of super-physical units includes a plurality of first good super-physical units and at least one first partial good super-physical unit selected from the plurality of super-physical units according to the number ratio.

在步骤S1105中,存储器控制电路单元404根据多个好超实体单元的个数与多个部分好超实体单元的个数动态地更新个数比率。In step S1105 , the memory control circuit unit 404 dynamically updates the number ratio according to the number of good supersolid units and the number of partial good supersolid units.

在步骤S1107中,存储器控制电路单元404根据可复写式非易失性存储器模块406中好超实体单元与部分好超实体单元的个数比率从可复写式非易失性存储器模块406除第一超实体单元集合以外的剩余超实体单元之中选择出第二超实体单元集合,其中第二超实体单元集合包括按个数比率从剩余超实体单元选择出的多个第二好超实体单元及至少一个第二部分好超实体单元。In step S1107, the memory control circuit unit 404 divides the first super-physical unit from the rewritable non-volatile memory module 406 according to the ratio of the number of good super-physical units to some good super-physical units in the rewritable non-volatile memory module 406. Select the second super entity unit set among the remaining super entity units outside the super entity unit set, wherein the second super entity unit set includes a plurality of second best super entity units selected from the remaining super entity units according to the number ratio and At least one second-part good super-solid unit.

在步骤S1109中,存储器控制电路单元404将主机系统的数据写入至第一超实体单元集合的好实体抹除单元中。In step S1109, the memory control circuit unit 404 writes the data of the host system into the good physical erase unit of the first super-physical unit set.

在步骤S1111中,存储器控制电路单元404将主机系统的数据继续写入至第二超实体单元集合的好实体抹除单元中,以回应主机写入指令。In step S1111, the memory control circuit unit 404 continues to write the data of the host system into the good physical erase unit of the second super-physical unit set in response to the host write command.

图12是根据一范例实施例所示出的实体抹除单元与逻辑地址重新映射的流程图。FIG. 12 is a flowchart showing the remapping between physical erase units and logical addresses according to an exemplary embodiment.

请参照图12,在步骤S1201中,存储器控制电路单元404从多个超实体单元之中选择第一部分好超实体单元及第二部分好超实体单元。Referring to FIG. 12 , in step S1201 , the memory control circuit unit 404 selects a first part of good superphysical units and a second part of good superphysical units from a plurality of superphysical units.

在步骤S1203中,存储器控制电路单元404将第一部分好超实体单元的好实体抹除单元映射至第二部分好超实体单元的坏实体抹除单元的逻辑地址,第二部分好超实体单元的坏实体抹除单元不再映射至逻辑地址,其中,第一部分好超实体单元的好实体抹除单元与第二部分好超实体单元的坏实体抹除单元属于同一通道且属于同一区块面。In step S1203, the memory control circuit unit 404 maps the good physical erasing units of the first part of good superphysical units to the logical addresses of the bad physical erasing units of the second part of good superphysical units, and the logical addresses of the bad physical erasing units of the second part of good superphysical units. Bad physical erase units are no longer mapped to logical addresses, wherein the good physical erase units of the first part of good super-physical units and the bad physical erase units of the second part of good super-physical units belong to the same channel and belong to the same block plane.

在步骤S1205中,存储器控制电路单元404更新逻辑-实体映射表。In step S1205, the memory control circuit unit 404 updates the logic-entity mapping table.

图13是根据另一范例实施例所示出的存储器管理方法的流程图。Fig. 13 is a flowchart of a memory management method according to another exemplary embodiment.

请参照图13,在步骤S1301中,存储器控制电路单元404将多个超实体单元至少分组为坏超实体单元、部分好超实体单元以及好超实体单元。Referring to FIG. 13 , in step S1301 , the memory control circuit unit 404 at least groups a plurality of superentity units into bad superentity units, some good superentity units and good superentity units.

在步骤S1303中,存储器控制电路单元404对坏超实体单元、部分好超实体单元以及好超实体单元分别作标记。In step S1303, the memory control circuit unit 404 marks the bad super-entity units, some good super-entity units and good super-entity units respectively.

在步骤S1305中,存储器控制电路单元404更新超实体单元伫列表。In step S1305, the memory control circuit unit 404 updates the super-physical unit queue table.

在步骤S1307中,存储器控制电路单元404依据超实体单元伫列表选择出第一超实体单元集合。In step S1307, the memory control circuit unit 404 selects a first set of super-physical units according to the super-physical unit queue table.

在步骤S1309中,存储器控制电路单元404对第一超实体单元集合中的多个第一好超实体单元的个数及至少一个第一部分好超实体单元的个数计数。In step S1309, the memory control circuit unit 404 counts the number of multiple first good superphysical units and the number of at least one first partial good superphysical unit in the first superphysical unit set.

综上所述,本发明提供一种存储器管理方法、存储器控制电路单元与存储器存储装置,依据好超实体单元与部分好超实体单元的个数比率选择超实体单元集合以供主机系统的数据写入,平均了部分好超实体单元中坏实体抹除单元出现的机率,使得单位时间内可复写式非易失性存储器模块速度稳定,并且可复写式非易失性存储器模块的实体抹除单元使用次数较为平均,减少了平均磨损的机率,提高了可复写式非易失性存储器模块的使用寿命。In summary, the present invention provides a memory management method, a memory control circuit unit, and a memory storage device. According to the ratio of the number of good super-physical units to some good super-physical units, a set of super-physical units is selected for data writing by the host system. input, which averages the probability of bad physical erasing units in some good super-physical units, so that the speed of the rewritable non-volatile memory module is stable per unit time, and the physical erasing unit of the rewritable non-volatile memory module The number of times of use is relatively average, which reduces the probability of average wear and improves the service life of the rewritable non-volatile memory module.

虽然本发明已以实施例揭示如上,然其并非用以限定本发明,任何所属技术领域中技术人员,在不脱离本发明的精神和范围内,当可作些许的更改与润饰,故本发明的保护范围当视权利要求所界定的为准。Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall prevail as defined by the claims.

Claims (15)

1.一种存储器管理方法,用于包括多个超实体单元的可复写式非易失性存储器模块,所述多个超实体单元至少包括多个好超实体单元及多个部分好超实体单元,其中每一个所述好超实体单元包括多个好实体抹除单元,每一个所述部分好超实体单元包括至少一个坏实体抹除单元,其特征在于,所述存储器管理方法包括:1. A memory management method, used for a rewritable non-volatile memory module comprising a plurality of super-substance units, said plurality of super-substance units at least comprising a plurality of good super-substance units and a plurality of partial good super-substance units , wherein each of the good super-physical units includes a plurality of good physical erasing units, and each of the part of good super-physical units includes at least one bad physical erasing unit, it is characterized in that the memory management method includes: 接收主机写入指令;Receive host write command; 根据所述可复写式非易失性存储器模块中所述多个好超实体单元与所述多个部分好超实体单元的个数比率从所述多个超实体单元选择出第一超实体单元集合,其中所述第一超实体单元集合包括按所述个数比率从所述多个超实体单元选择出的多个第一好超实体单元及至少一个第一部分好超实体单元;Selecting a first super-solid unit from the plurality of super-solid units according to the number ratio of the plurality of good super-solid units to the plurality of good super-solid units in the rewritable non-volatile memory module A collection, wherein the first set of superphysical units includes a plurality of first good superphysical units and at least one first part of good superphysical units selected from the plurality of superphysical units according to the number ratio; 将数据写入至所述第一超实体单元集合的好实体抹除单元中,以回应所述主机写入指令;以及writing data into a good physical erase unit of the first set of super-physical units in response to the host write command; and 根据所述多个好超实体单元的个数与所述多个部分好超实体单元的个数动态地更新所述个数比率。The number ratio is dynamically updated according to the number of the plurality of good super-substance units and the number of the plurality of partial good super-substance units. 2.根据权利要求1所述的存储器管理方法,其特征在于,还包括:2. The memory management method according to claim 1, further comprising: 根据所述可复写式非易失性存储器模块中所述好超实体单元与所述部分好超实体单元的所述个数比率从所述可复写式非易失性存储器模块中除所述第一超实体单元集合以外的剩余超实体单元之中选择出第二超实体单元集合,其中所述第二超实体单元集合包括按所述个数比率从所述剩余超实体单元选择出的多个第二好超实体单元及至少一个第二部分好超实体单元;以及According to the number ratio of the good super-substance units and the part of good super-substance units in the rewritable non-volatile memory module, divide the second from the rewritable non-volatile memory module Selecting a second set of super-entity units from the remaining super-entity units other than the set of super-entity units, wherein the second set of super-entity units includes a plurality of super-entity units selected from the remaining super-entity units according to the number ratio the second best supersolid element and at least one second partial best supersolid element; and 将所述数据继续写入至所述第二超实体单元集合的好实体抹除单元中。The data is continuously written into the good physical erase unit of the second super-physical unit set. 3.根据权利要求1所述的存储器管理方法,其特征在于,还包括:3. The memory management method according to claim 1, further comprising: 将所述多个超实体单元至少分组为坏超实体单元、部分好超实体单元以及好超实体单元;grouping the plurality of superphysical units into at least bad superphysical units, some good superphysical units, and good superphysical units; 对所述坏超实体单元、所述部分好超实体单元以及所述好超实体单元分别作标记;以及Marking said bad super-substance unit, said part of good super-substance unit and said good super-substance unit respectively; and 更新超实体单元伫列表。Update the supersolid element queue list. 4.根据权利要求3所述的存储器管理方法,其特征在于,还包括:4. The memory management method according to claim 3, further comprising: 依据每一所述超实体单元中坏实体抹除单元的个数与每一所述超实体单元中实体抹除单元的总个数的比例将所述多个超实体单元至少分组为所述坏超实体单元、所述部分好超实体单元以及所述好超实体单元。According to the ratio of the number of bad physical erasing units in each of the super-physical units to the total number of physical erasing units in each of the super-physical units, the multiple super-physical units are at least grouped into the bad a superphysical element, the partial good superphysical element, and the good superphysical element. 5.根据权利要求3所述的存储器管理方法,其特征在于,所述根据所述可复写式非易失性存储器模块中所述多个好超实体单元与所述多个部分好超实体单元的所述个数比率从所述多个超实体单元选择出所述第一超实体单元集合的步骤包括:5. The memory management method according to claim 3, characterized in that, according to the plurality of good super-physical units and the plurality of partial good super-physical units in the rewritable non-volatile memory module The step of selecting the first set of super-substance units from the plurality of super-substance units according to the number ratio includes: 依据所述超实体单元伫列表选择出所述第一超实体单元集合;以及selecting the first super-solid unit set according to the super-solid unit queue table; and 对所述第一超实体单元集合中的多个第一好超实体单元的个数及至少一个第一部分好超实体单元的个数计数。Counting the number of multiple first good super-substance units and the number of at least one first partial good super-substance unit in the first super-substance unit set. 6.一种存储器控制电路单元,用于包括多个超实体单元的可复写式非易失性存储器模块,所述多个超实体单元至少包括多个好超实体单元及多个部分好超实体单元,其中每一个所述好超实体单元包括多个好实体抹除单元,每一个所述部分好超实体单元包括至少一个坏实体抹除单元,其特征在于,所述存储器控制电路单元包括:6. A memory control circuit unit, used for a rewritable non-volatile memory module comprising a plurality of super-entity units, said plurality of super-entity units at least comprising a plurality of good super-entity units and a plurality of partial good super-entity units Units, wherein each of the good super-physical units includes a plurality of good physical erasing units, and each of the part of the good super-physical units includes at least one bad physical erasing unit, wherein the memory control circuit unit includes: 主机接口,用以电性连接至主机系统;a host interface for electrically connecting to a host system; 存储器接口,用以电性连接至所述可复写式非易失性存储器模块;以及a memory interface for electrically connecting to the rewritable non-volatile memory module; and 存储器管理电路,电性连接至所述主机接口与所述存储器接口,a memory management circuit electrically connected to the host interface and the memory interface, 其中所述存储器管理电路用以接收主机写入指令,所述存储器管理电路用以根据所述可复写式非易失性存储器模块中所述多个好超实体单元与所述多个部分好超实体单元的个数比率从所述多个超实体单元选择出第一超实体单元集合,其中所述第一超实体单元集合包括按所述个数比率从所述多个超实体单元选择出的多个第一好超实体单元及至少一个第一部分好超实体单元,Wherein the memory management circuit is used to receive the write command from the host, and the memory management circuit is used to according to the multiple good super-physical units and the multiple partial good super-physical units in the rewritable non-volatile memory module The number ratio of the physical units selects a first set of super-physical units from the plurality of super-physical units, wherein the first set of super-physical units includes the selected super-physical units according to the number ratio a plurality of first good supersolid elements and at least one first partial good supersolid element, 其中所述存储器管理电路还用以将对应所述主机写入指令的数据写入至所述第一超实体单元集合的好实体抹除单元中,以回应所述主机写入指令,Wherein the memory management circuit is further configured to write data corresponding to the host write command into the good physical erase unit of the first super-physical unit set in response to the host write command, 其中所述存储器管理电路还用以根据所述多个好超实体单元的个数与所述多个部分好超实体单元的个数动态地更新所述个数比率。Wherein the memory management circuit is further configured to dynamically update the number ratio according to the number of the plurality of good super-physical units and the number of the plurality of partial good super-physical units. 7.根据权利要求6所述的存储器控制电路单元,其特征在于,7. The memory control circuit unit according to claim 6, wherein: 所述存储器管理电路还用以根据所述可复写式非易失性存储器模块中所述好超实体单元与所述部分好超实体单元的所述个数比率从所述可复写式非易失性存储器模块中除所述第一超实体单元集合以外的剩余超实体单元之中选择出第二超实体单元集合,其中所述第二超实体单元集合包括按所述个数比率从所述剩余超实体单元选择出的多个第二好超实体单元及至少一个第二部分好超实体单元,The memory management circuit is also used to select from the rewritable nonvolatile memory module according to the number ratio of the good superphysical units and the part of good superphysical units. Select a second set of super-entity units from the remaining super-entity units in the memory module except the first set of super-entity units, wherein the second set of super-entity units includes the remaining super-entity units according to the number ratio A plurality of second-best super-substance units selected by super-substance units and at least one second part of the best super-substance units, 所述存储器管理电路还用以将所述数据继续写入至所述第二超实体单元集合的好实体抹除单元中。The memory management circuit is further configured to continue writing the data into a good physical erase unit of the second super-physical unit set. 8.根据权利要求6所述的存储器控制电路单元,其特征在于,8. The memory control circuit unit according to claim 6, wherein: 所述存储器管理电路还用以将所述多个超实体单元至少分组为坏超实体单元、部分好超实体单元以及好超实体单元,The memory management circuit is further configured to group the plurality of superphysical units into at least bad superphysical units, some good superphysical units, and good superphysical units, 所述存储器管理电路还用以对所述坏超实体单元、所述部分好超实体单元以及所述好超实体单元分别作标记,以及The memory management circuit is also used to mark the bad super entity unit, the part of the good super entity unit and the good super entity unit respectively, and 所述存储器管理电路还用以更新超实体单元伫列表。The memory management circuit is also used for updating the super-physical unit queue table. 9.根据权利要求8所述的存储器控制电路单元,其特征在于,9. The memory control circuit unit according to claim 8, wherein: 所述存储器管理电路还用以依据每一所述超实体单元中坏实体抹除单元的个数与每一所述超实体单元中实体抹除单元的总个数的比例将所述多个超实体单元至少分组为所述坏超实体单元、所述部分好超实体单元以及所述好超实体单元。The memory management circuit is also used to divide the multiple super physical units according to the ratio of the number of bad physical erasing units in each super physical unit to the total number of physical erasing units in each super physical unit The physical units are grouped into at least the bad super-physical units, the part of the good super-physical units, and the good super-physical units. 10.根据权利要求8所述的存储器控制电路单元,其特征在于,所述存储器管理电路还用以根据所述可复写式非易失性存储器模块中所述多个好超实体单元与所述多个部分好超实体单元的所述个数比率从所述多个超实体单元选择出所述第一超实体单元集合的操作包括,10. The memory control circuit unit according to claim 8, characterized in that, the memory management circuit is also used for according to the plurality of good super-entity units in the rewritable non-volatile memory module and the The operation of selecting the first set of super-physical units from the plurality of super-physical units according to the number ratio of a plurality of partial good super-physical units includes, 所述存储器管理电路还用以依据所述超实体单元伫列表选择出所述第一超实体单元集合,以及The memory management circuit is also used to select the first set of super-physical units according to the super-physical unit queue table, and 所述存储器管理电路还用以对所述第一超实体单元集合中的多个第一好超实体单元的个数及至少一个第一部分好超实体单元的个数计数。The memory management circuit is also used for counting the number of multiple first good super-physical units and the number of at least one first partial good super-physical unit in the first super-physical unit set. 11.一种存储器存储装置,其特征在于,包括:11. A memory storage device, comprising: 连接接口单元,用以电性连接至主机系统;connecting the interface unit for electrically connecting to the host system; 可复写式非易失性存储器模块,包括多个超实体单元,所述多个超实体单元至少包括多个好超实体单元及多个部分好超实体单元,其中每一个所述好超实体单元包括多个好实体抹除单元,每一个所述部分好超实体单元包括至少一个坏实体抹除单元;以及The rewritable non-volatile memory module includes a plurality of super-substance units, and the plurality of super-substance units at least include a plurality of good super-substance units and a plurality of partial good super-substance units, wherein each of the good super-substance units comprising a plurality of good physical erasure units, each of said portion of good super-physical units comprising at least one bad physical erasure unit; and 存储器控制电路单元,电性连接至所述连接接口单元与所述可复写式非易失性存储器模块,a memory control circuit unit electrically connected to the connection interface unit and the rewritable non-volatile memory module, 其中所述存储器控制电路单元用以接收主机写入指令,所述存储器控制电路单元用以根据所述可复写式非易失性存储器模块中所述多个好超实体单元与所述多个部分好超实体单元的个数比率从所述多个超实体单元选择出第一超实体单元集合,其中所述第一超实体单元集合包括按所述个数比率从所述多个超实体单元选择出的多个第一好超实体单元及至少一个第一部分好超实体单元,Wherein the memory control circuit unit is used to receive the write instruction from the host, and the memory control circuit unit is used to operate according to the plurality of good super-entity units and the plurality of parts in the rewritable non-volatile memory module. The number ratio of good super-substance units selects a first set of super-substance units from the plurality of super-substance units, wherein the first collection of super-substance units includes selecting from the plurality of super-substance units according to the number ratio Multiple first good super-entity units and at least one first part of good super-entity units, 其中所述存储器控制电路单元用以将对应所述主机写入指令的数据写入至所述第一超实体单元集合的好实体抹除单元中,以回应所述主机写入指令,wherein the memory control circuit unit is used to write data corresponding to the host write command into the good physical erase unit of the first super-physical unit set in response to the host write command, 其中所述存储器控制电路单元用以根据所述多个好超实体单元的个数与所述多个部分好超实体单元的个数动态地更新所述个数比率。Wherein the memory control circuit unit is configured to dynamically update the number ratio according to the number of the plurality of good super-physical units and the number of the plurality of partial good super-physical units. 12.根据权利要求11所述的存储器存储装置,其特征在于,12. The memory storage device of claim 11 , wherein 所述存储器控制电路单元还用以根据所述可复写式非易失性存储器模块中所述好超实体单元与所述部分好超实体单元的所述个数比率从所述可复写式非易失性存储器模块中除所述第一超实体单元集合以外的剩余超实体单元之中选择出第二超实体单元集合,其中所述第二超实体单元集合包括按所述个数比率从所述剩余超实体单元选择出的多个第二好超实体单元及至少一个第二部分好超实体单元,The memory control circuit unit is also used to select from the rewritable non-volatile memory module according to the number ratio of the good super-physical units and the part of good super-physical units in the rewritable non-volatile memory module. Select a second set of super-solid units from the remaining super-solid units in the volatile memory module except for the first set of super-solid units, wherein the second set of super-solid units includes the number ratio from the a plurality of second-best super-substance units selected from the remaining super-substance units and at least one second part of the best super-substance units, 所述存储器控制电路单元还用以将所述数据继续写入至所述第二超实体单元集合的好实体区块中。The memory control circuit unit is also used for continuing to write the data into the good physical block of the second super-physical unit set. 13.根据权利要求11所述的存储器存储装置,其特征在于,13. The memory storage device of claim 11 , wherein 所述存储器控制电路单元还用以将所述多个超实体单元至少分组为坏超实体单元、部分好超实体单元以及好超实体单元,The memory control circuit unit is further configured to at least group the plurality of super-entity units into bad super-entity units, some good super-entity units, and good super-entity units, 所述存储器控制电路单元还用以对所述坏超实体单元、所述部分好超实体单元以及所述好超实体单元分别作标记,以及The memory control circuit unit is also used to mark the bad super-entity unit, the part of the good super-entity unit and the good super-entity unit respectively, and 所述存储器控制电路单元还用以更新超实体单元伫列表。The memory control circuit unit is also used for updating the super-physical unit queue table. 14.根据权利要求13所述的存储器存储装置,其特征在于,14. The memory storage device of claim 13, wherein 所述存储器控制电路单元还用以依据每一所述超实体单元中坏实体抹除单元的个数与每一所述超实体单元中实体抹除单元的总个数的比例将所述多个超实体单元至少分组为所述坏超实体单元、所述部分好超实体单元以及所述好超实体单元。The memory control circuit unit is also used for dividing the number of bad physical erasing units in each super-physical unit to the total number of physical erasing units in each super-physical unit. The superphysical units are grouped at least into said bad superphysical units, said part of good superphysical units, and said good superphysical units. 15.根据权利要求13所述的存储器存储装置,其特征在于,所述存储器控制电路单元还用以根据所述可复写式非易失性存储器模块中所述多个好超实体单元与所述多个部分好超实体单元的所述个数比率从所述多个超实体单元选择出所述第一超实体单元集合的操作包括,15. The memory storage device according to claim 13, wherein the memory control circuit unit is further configured to combine the plurality of good super-entity units and the The operation of selecting the first set of super-substance units from the plurality of super-substance units according to the number ratio of a plurality of partial good super-substance units includes, 所述存储器控制电路单元还用以依据所述超实体单元伫列表选择出所述第一超实体单元集合,以及The memory control circuit unit is also used to select the first super-physical unit set according to the super-physical unit queue table, and 所述存储器控制电路单元还用以对所述第一超实体单元集合中的多个第一好超实体单元的个数及至少一个第一部分好超实体单元的个数计数。The memory control circuit unit is also used for counting the number of multiple first good super-physical units and the number of at least one first partial good super-physical unit in the first super-physical unit set.
CN201810612079.1A 2018-06-14 2018-06-14 Memory management method, memory control circuit unit and memory storage device Active CN110609795B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810612079.1A CN110609795B (en) 2018-06-14 2018-06-14 Memory management method, memory control circuit unit and memory storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810612079.1A CN110609795B (en) 2018-06-14 2018-06-14 Memory management method, memory control circuit unit and memory storage device

Publications (2)

Publication Number Publication Date
CN110609795A CN110609795A (en) 2019-12-24
CN110609795B true CN110609795B (en) 2022-11-22

Family

ID=68887559

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810612079.1A Active CN110609795B (en) 2018-06-14 2018-06-14 Memory management method, memory control circuit unit and memory storage device

Country Status (1)

Country Link
CN (1) CN110609795B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104765695A (en) * 2015-04-03 2015-07-08 上海交通大学 NAND FLASH bad block management system and method
CN106920572A (en) * 2015-12-25 2017-07-04 群联电子股份有限公司 Memory management method, memory control circuit unit and memory storage device
CN106959818A (en) * 2016-01-11 2017-07-18 群联电子股份有限公司 Data writing method, memory control circuit unit and memory storage device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050144516A1 (en) * 2003-12-30 2005-06-30 Gonzalez Carlos J. Adaptive deterministic grouping of blocks into multi-block units
KR20100094241A (en) * 2009-02-18 2010-08-26 삼성전자주식회사 Nonvolatile memory device not including reserved blocks
US8832507B2 (en) * 2010-08-23 2014-09-09 Apple Inc. Systems and methods for generating dynamic super blocks
US8700961B2 (en) * 2011-12-20 2014-04-15 Sandisk Technologies Inc. Controller and method for virtual LUN assignment for improved memory bank mapping
US9239781B2 (en) * 2012-02-07 2016-01-19 SMART Storage Systems, Inc. Storage control system with erase block mechanism and method of operation thereof
US20150339223A1 (en) * 2014-05-22 2015-11-26 Kabushiki Kaisha Toshiba Memory system and method
TWI596477B (en) * 2015-12-18 2017-08-21 群聯電子股份有限公司 Memory management method, memory control circuit unit and memory storage device
TWI584291B (en) * 2015-12-28 2017-05-21 群聯電子股份有限公司 Memory management method, memory control circuit unit and memory storage device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104765695A (en) * 2015-04-03 2015-07-08 上海交通大学 NAND FLASH bad block management system and method
CN106920572A (en) * 2015-12-25 2017-07-04 群联电子股份有限公司 Memory management method, memory control circuit unit and memory storage device
CN106959818A (en) * 2016-01-11 2017-07-18 群联电子股份有限公司 Data writing method, memory control circuit unit and memory storage device

Also Published As

Publication number Publication date
CN110609795A (en) 2019-12-24

Similar Documents

Publication Publication Date Title
TWI731338B (en) Memory control method, memory storage device and memory control circuit unit
CN109491588B (en) Memory management method, memory control circuit unit and memory storage device
CN111078146B (en) Memory management method, memory storage device and memory control circuit unit
TWI688953B (en) Memory management method, memory storage device and memory control circuit unit
US10564862B2 (en) Wear leveling method, memory control circuit unit and memory storage apparatus
TWI664528B (en) Memory management method, memory control circuit unit and memory storage apparatus
CN107045890B (en) Data protection method, memory control circuit unit and memory storage device
CN109273033B (en) Memory management method, memory control circuit unit and memory storage device
CN106959818A (en) Data writing method, memory control circuit unit and memory storage device
CN106920572B (en) Memory management method, memory control circuit unit and memory storage device
CN109032957B (en) Memory management method, memory control circuit unit and memory storage device
CN110275668B (en) Block management method, memory control circuit unit and memory storage device
CN107103930A (en) Data writing method, memory control circuit unit and memory storage device
CN107132989B (en) Data programming method, memory control circuit unit and memory storage device
CN111831210B (en) Memory management method, memory control circuit unit and memory storage device
CN110609795B (en) Memory management method, memory control circuit unit and memory storage device
CN109522236B (en) Memory management method, memory control circuit unit and memory storage device
TW201723848A (en) Memory management method, memory control circuit unit and memory storage device
CN107102814B (en) Memory management method, memory control circuit unit and memory storage device
TWI591641B (en) Data programming method, memory control circuit unit and memory storage device
CN112053724B (en) Memory control method, memory storage device and memory control circuit unit
CN114527941B (en) Memory control method, memory storage device and memory control circuit unit
CN103425594B (en) Data processing method, memory controller and memory storage device
CN112181859B (en) Effective data merging method, memory control circuit unit and storage device
CN110389708B (en) Wear leveling method, memory control circuit unit and memory storage device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant