CN110609583A - A circuit for stabilizing grid voltage of driving tube for buzzer - Google Patents

Abstract

The invention provides a circuit for stabilizing the gate voltage of the driving tube for the buzzer, including a logic control circuit, an NMOS tube MN1, and an NMOS tube MN2. Wherein, the input F of the logic control circuit is a frequency signal, the output N1 of the logic control circuit is connected to the gate of the NMOS transistor MN1, the output N2 of the logic control circuit is connected to the gate of the NMOS transistor MN2, and the drain of the NMOS transistor MN1 is connected to Power line, the source of the NMOS transistor MN1 is connected to the gate G of the buzzer NMOS driving transistor, the substrate of the NMOS transistor MN1 is connected to the ground wire, and the drain of the NMOS transistor MN2 is connected to the gate of the buzzer NMOS driving transistor G, the source of the NMOS transistor MN2 is connected to the ground, and the substrate of the NMOS transistor MN2 is connected to the ground. The invention controls the turn-on time of the gates of the two NMOS transistors MN1 and MN2 through a logic control circuit, so as to prevent the gate voltage of the buzzer NMOS drive transistor from dropping together with the power supply voltage. The circuit has the advantages of simple structure and low cost.

Description

A circuit for stabilizing grid voltage of driving tube for buzzer

technical field

The invention relates to the field of a buzzer circuit, in particular to a circuit used for the buzzer to stabilize the grid voltage of a drive tube.

Background technique

As shown in Figure 6, the gate drive circuit of the traditional buzzer drive tube, when the power line voltage drops, the grid voltage of the buzzer drive tube drops along with the power line voltage, resulting in the buzzer drive tube Insufficient drive capability may even cause instability in the output frequency of the buzzer.

Contents of the invention

The invention provides a circuit for stabilizing the gate voltage of the buzzer drive tube, which solves the problem that the grid voltage of the buzzer drive tube drops together with the voltage of the power line when the voltage of the power line drops, and prevents the power supply voltage from dropping , the drive capability of the buzzer drive tube is insufficient, and may even cause instability in the output frequency of the buzzer.

In order to solve the above technical problems, the present invention provides a circuit for stabilizing the gate voltage of the buzzer driving transistor, including a logic control circuit, NMOS transistor MN1, and NMOS transistor MN2. Wherein, the input F of the logic control circuit is a frequency signal, the output N1 of the logic control circuit is connected to the gate of the NMOS transistor MN1, the output N2 of the logic control circuit is connected to the gate of the NMOS transistor MN2, and the drain of the NMOS transistor MN1 is connected to Power line, the source of the NMOS transistor MN1 is connected to the gate G of the buzzer NMOS driving transistor, the substrate of the NMOS transistor MN1 is connected to the ground wire, and the drain of the NMOS transistor MN2 is connected to the gate of the buzzer NMOS driving transistor G, the source of the NMOS transistor MN2 is connected to the ground, and the substrate of the NMOS transistor MN2 is connected to the ground.

Preferably, the sources and drains of the NMOS transistors MN1 and MN2 are switched.

Beneficial effects brought by the present invention: a circuit for stabilizing the gate voltage of the buzzer drive tube provided by the present invention controls the turn-on time of the gates of the two NMOS tubes of MN1 and MN2 through a logic control circuit to prevent The gate voltage of the buzzer NMOS drive tube drops along with the power supply voltage. Moreover, the circuit has the advantages of simple structure and low cost.

Description of drawings

FIG. 1 is a structural schematic diagram of a circuit for stabilizing the gate voltage of a buzzer drive tube according to the present invention.

FIG. 2 is a schematic diagram of the timing of the circuit used for the buzzer to stabilize the gate voltage of the driving tube according to the first embodiment of the present invention.

FIG. 3 is a schematic diagram of the circuit timing for the buzzer to stabilize the gate voltage of the driving tube according to the second embodiment of the present invention.

FIG. 4 is a schematic diagram of circuit timing for a buzzer to stabilize the gate voltage of a driving tube according to a third embodiment of the present invention.

FIG. 5 is a schematic diagram of the circuit timing for the buzzer to stabilize the gate voltage of the driving tube according to the fourth embodiment of the present invention.

Figure 6 is a schematic diagram of the background technology.

Detailed ways

In order to make the purpose, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

As shown in FIG. 1 , a circuit for stabilizing the gate voltage of a buzzer driving transistor provided by the present invention includes a circuit control circuit, an NMOS transistor MN1 , and an NMOS transistor MN2 . Wherein, the input F of the logic control circuit is a frequency signal, the output N1 of the logic control circuit is connected to the gate of the NMOS transistor MN1, the output N2 of the logic control circuit is connected to the gate of the NMOS transistor MN2, and the drain of the NMOS transistor MN1 is connected to Power line, the source of the NMOS transistor MN1 is connected to the gate G of the buzzer NMOS driving transistor, the substrate of the NMOS transistor MN1 is connected to the ground wire, and the drain of the NMOS transistor MN2 is connected to the gate of the buzzer NMOS driving transistor G, the source of the NMOS transistor MN2 is connected to the ground, and the substrate of the NMOS transistor MN2 is connected to the ground.

The first embodiment of the present invention: the working sequence is shown in Figure 2, combined with Figure 1, F is the frequency signal generated inside the chip, when the F level changes and the buzzer NMOS drive tube is turned on, that is, the beginning of t1 At this time, the output N1 of the logic control circuit is at low level, the NMOS tube MN1 remains in the off state, the output N2 of the logic control circuit changes from high level to low level, the NMOS tube MN2 changes from the on state to the off state, and the buzzer The gate G of the NMOS drive tube of the device keeps low level. At the last moment of t1, the output N1 of the logic control circuit changes from low level to high level. Since the NMOS tube MN2 is in the off state at this time, the power supply passes through the MOS tube MN1 charges the gate G of the buzzer NMOS drive tube, and the buzzer NMOS drive tube is turned on. When the power supply voltage drops below the gate voltage of the buzzer NMOS drive tube, the NMOS tube MN1 is cut off, so the buzzer The gate voltage of the NMOS drive tube of the device will not drop along with the power supply voltage.

The second embodiment of the present invention: the working sequence is as shown in Figure 3. In conjunction with Figure 1, F is the frequency signal generated inside the chip. When the F level changes and the buzzer NMOS drive tube is turned on, the output of the logic control circuit N1 changes from low level to high level, the NMOS transistor MN1 changes from the off state to the on state, the output N2 of the logic control circuit changes from high level to low level, and the NMOS transistor MN2 changes from the on state to the off state , so the power supply charges the gate G of the buzzer NMOS drive tube through the MOS tube MN1, and the buzzer NMOS drive tube is turned on. When the power supply voltage drops below the gate voltage of the buzzer NMOS drive tube, the NMOS tube MN1 is off, so the gate voltage of the buzzer NMOS drive tube will not drop along with the power supply voltage.

The third embodiment of the present invention: the working sequence is shown in Figure 4, combined with Figure 1, F is the frequency signal generated inside the chip, when the F level changes and the buzzer NMOS drive tube is turned on, that is, the beginning of t1 At this time, the output N1 of the logic control circuit is at a high level, the NMOS transistor MN1 changes from the off state to the on state, the output N2 of the logic control circuit is at a low level, and the NMOS transistor MN2 remains in the on state. and the NMOS transistor MN2 are both in the conduction state, so the current charged to the gate G of the buzzer NMOS drive transistor is related to the on-resistance resistance of the NMOS transistor MN1 and the NMOS transistor MN2, and the NMOS transistor MN1 and the NMOS transistor MN2 The sum of the on-resistance values of the on-resistance cannot be too small, too small will cause a large drop in the internal power supply of the chip. At the end of t1, the output N2 of the logic control circuit changes from high level to low level, and the NMOS tube MN2 From the on state to the off state, so the power supply charges the gate G of the buzzer NMOS drive tube through the MOS tube MN1, and the buzzer NMOS drive tube is turned on to a greater extent. When the power supply voltage drops to the buzzer NMOS drive tube When the gate voltage of the transistor is lower than that, since the NMOS transistor MN1 is cut off, the gate voltage of the NMOS drive transistor of the buzzer will not drop along with the power supply voltage.

The fourth embodiment of the present invention: the working sequence is shown in Figure 5, combined with Figure 1, F is the frequency signal generated inside the chip, when the F level changes and the buzzer NMOS drive tube is turned on, that is, the beginning of t1 At this moment, the output N1 of the logic control circuit changes from low level to high level, the NMOS transistor MN1 changes from the off state to the on state, the output N2 of the logic control circuit changes from high level to low level, and the NMOS transistor MN2 changes from the off state to the on state. The conduction state changes to the cut-off state, so the power supply charges the grid G of the buzzer NMOS drive tube through the MOS tube MN1, and the buzzer NMOS drive tube is turned on. At the last moment of t1, the output N1 of the logic control circuit changes from high to high. The level becomes low level, and the NMOS tube MN1 changes from the on state to the off state. When the power supply voltage drops below the gate voltage of the buzzer NMOS drive tube, the NMOS tube MN1 is off, so the buzzer NMOS drive The tube grid voltage will not drop with the power supply voltage.

The fourth embodiment of the present invention is an improved embodiment of the second embodiment of the present invention. Similarly, the first embodiment of the present invention and the third embodiment of the present invention can also be improved, that is, the buzzer After the grid G of the NMOS drive tube of the buzzer is charged, the NMOS tube MN1 is quickly turned off to reduce the leakage current of the gate of the NMOS drive tube of the buzzer when the power supply voltage drops.

In summary, the present invention provides a circuit for stabilizing the gate voltage of the buzzer drive tube, which controls the turn-on time of the gates of the two NMOS tubes MN1 and MN2 through a logic control circuit to prevent the buzzer from The gate voltage of the NMOS drive tube drops along with the power supply voltage. Moreover, the circuit has the advantages of simple structure and low cost.

The above description is only an embodiment of the present invention, and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the scope of the claims of the present invention.

Claims (2)

1. A circuit for stabilizing the gate voltage of a buzzer drive tube, a logic control circuit, an NMOS tube MN1, and an NMOS tube MN2. Wherein, the input F of the logic control circuit is a frequency signal, the output N1 of the logic control circuit is connected to the gate of the NMOS transistor MN1, the output N2 of the logic control circuit is connected to the gate of the NMOS transistor MN2, and the drain of the NMOS transistor MN1 is connected to Power line, the source of the NMOS transistor MN1 is connected to the gate G of the buzzer NMOS driving transistor, the substrate of the NMOS transistor MN1 is connected to the ground wire, and the drain of the NMOS transistor MN2 is connected to the gate of the buzzer NMOS driving transistor G, the source of the NMOS transistor MN2 is connected to the ground, and the substrate of the NMOS transistor MN2 is connected to the ground. 2 . The circuit for stably driving the gate voltage of the buzzer as claimed in claim 1 , wherein the positions of the source terminals and the drain terminals of the NMOS transistors MN1 and MN2 are reversed without affecting the normal operation of the circuit. 3 .