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CN110571201B - High-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure and preparation method thereof - Google Patents

High-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure and preparation method thereof Download PDF

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Publication number
CN110571201B
CN110571201B CN201910932010.1A CN201910932010A CN110571201B CN 110571201 B CN110571201 B CN 110571201B CN 201910932010 A CN201910932010 A CN 201910932010A CN 110571201 B CN110571201 B CN 110571201B
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Prior art keywords
layer
heat dissipation
plastic package
carrier plate
plastic
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CN110571201A (en
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雷珍南
贺姝敏
林挺宇
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Guangdong Fozhixin Microelectronics Technology Research Co ltd
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Guangdong Fozhixin Microelectronics Technology Research Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The invention discloses a high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure and a preparation method thereof, wherein the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure comprises: the chip plastic package body comprises a carrier plate, a wafer with copper columns and a plastic package layer, wherein the wafer with copper columns and the plastic package layer are attached to two sides of the carrier plate through a heat dissipation layer, the wafer is packaged in the plastic package layer, the chip plastic package body is provided with a plurality of through holes along the thickness direction of the chip plastic package body, and the copper columns of the wafer face to one side away from the carrier plate and are exposed out of the plastic package layer; the seed layer is positioned on one side of the plastic sealing layer far away from the carrier plate and extends into the through hole so as to cover the inner wall of the through hole; the conductive copper column is positioned in the through hole and is electrically connected with the rewiring layer on the seed layer, and the rewiring layer is provided with a bonding pad area and a non-bonding pad area; the solder mask layer is positioned on one side of the plastic sealing layer away from the carrier plate and covers the non-pad area of the rewiring layer; and the metal bump is welded with the bonding pad area of the rewiring layer. The invention has small outline dimension, large three-dimensional stacking density and good heat dissipation effect, and can effectively reduce warping.

Description

High-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure and preparation method thereof
Technical Field
The invention relates to the technical field of electronic packaging, in particular to a fan-out type three-dimensional heterogeneous double-sided plastic packaging structure with high heat dissipation and a preparation method thereof.
Background
In recent years, high density, multifunction, low power consumption and miniaturization have become the trend of semiconductor packaging development, and three-dimensional fan-out type wafer level packaging can better meet the development requirement and also better meet the requirements of the terminal market on product efficiency and volume. However, the existing three-dimensional fan-out type packages are mostly packaged in a stacking manner, and the fan-out type packages adopting a plastic package process are very difficult in terms of warpage control, and the solutions in the prior art also mostly reduce warpage in terms of material characteristics and final molding of plastic packages.
In the existing chip heat dissipation technology, the heat dissipation function is mostly based on the heat dissipation function set in the traditional packaging mode, meanwhile, the heat dissipation mode is often based on the heat dissipation structure added on the chip after the chip is subjected to plastic packaging, and a layer of plastic packaging material (usually epoxy resin and other materials) is further arranged in the middle, so that the heat dissipation efficiency of the chip is low due to poor heat conductivity.
In summary, the existing fan-out type package has the problems of high warpage and insufficient heat dissipation capacity, and seriously affects the quality and performance of the semiconductor chip.
Disclosure of Invention
The invention aims to provide a high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure and a preparation method thereof, which can effectively reduce the warpage of the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure and can rapidly lead out heat emitted by a wafer.
To achieve the purpose, the invention adopts the following technical scheme:
in one aspect, a three-dimensional heterogeneous double-sided plastic packaging structure of high heat dissipation fan-out formula is provided, includes:
The chip plastic package body comprises a carrier plate, a wafer with copper columns and a plastic package layer, wherein the wafer is attached to two sides of the carrier plate through a heat dissipation layer, the wafer is packaged in the plastic package layer, the chip plastic package body is provided with a plurality of through holes along the thickness direction of the chip plastic package body, and the copper columns of the wafer face to one side away from the carrier plate and are exposed out of the plastic package layer;
the seed layer is positioned on one side of the plastic sealing layer away from the carrier plate and extends into the through hole so as to cover the inner wall of the through hole;
The conductive copper column is positioned in the through hole and is electrically connected with the rewiring layer on the seed layer, and the rewiring layer is provided with a bonding pad area and a non-bonding pad area;
The solder mask layer is positioned on one side of the plastic sealing layer away from the carrier plate and covers the non-bonding pad area of the rewiring layer;
And the metal bump is welded with the bonding pad area of the rewiring layer.
As a preferred scheme of the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic packaging structure, the heat dissipation layer comprises heat dissipation glue attached to the carrier plate and heat dissipation metal layers attached to the heat dissipation glue, the heat dissipation metal layers are hollow structures, and the wafer is attached to the heat dissipation glue and packaged in the plastic packaging layer.
As a preferable scheme of the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure, the heat dissipation metal layer is any one of copper foil, aluminum foil, silver foil or gold foil.
As a preferable scheme of the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure, the seed layer comprises a titanium metal layer positioned on the plastic package layer and the inner wall of the through hole and a copper metal layer positioned on the titanium metal layer.
As a preferable scheme of the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure, the solder mask layer is a photosensitive ink layer.
On the other hand, the preparation method of the high-heat-dissipation fan-out type three-dimensional isomerism double-sided plastic package structure comprises the following steps:
S10, providing a carrier plate, a heat dissipation layer and a plurality of wafers with copper columns, enabling the front faces of the wafers to face away from the carrier plate, respectively attaching the wafers to two sides of the carrier plate through the heat dissipation layer, and packaging and fixing the wafers by adopting a plastic package material to obtain a chip plastic package body;
s20, carrying out hole opening treatment on the chip plastic package body to form a through hole penetrating through the chip plastic package body;
s30, manufacturing seed layers on two sides of the chip plastic package body and on the inner wall of the through hole;
S40, manufacturing a conductive copper column in the through hole, and manufacturing a rewiring layer which is electrically connected with the conductive copper column on the seed layer;
s50, providing a metal bump, and manufacturing a solder mask layer on the rerouting layer to expose a bonding pad area of the rerouting layer and electrically connect the metal bump.
As a preferred scheme of the preparation method of the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure, the step S10 specifically comprises the following steps:
s11, providing a carrier plate and first heat dissipation glue, and attaching the first heat dissipation glue to a first side of the carrier plate along the thickness direction of the carrier plate;
s12, providing a first heat dissipation metal layer with a hollowed-out structure, and attaching the first heat dissipation metal layer to the first heat dissipation adhesive;
S13, providing a plurality of first wafers with copper columns, and attaching the front sides of the first wafers to the first heat-dissipating adhesive towards the side away from the carrier plate;
S14, packaging the first wafer by using a plastic packaging material, and forming a first plastic packaging layer after the plastic packaging material is solidified;
s15, providing a second heat dissipation adhesive, and attaching the second heat dissipation adhesive to a second side of the carrier plate opposite to the first side;
S16, providing a second heat dissipation metal layer with a hollowed-out structure, and attaching the second heat dissipation metal layer to the second heat dissipation adhesive;
s17, providing a plurality of second wafers with copper columns, and attaching the front sides of the second wafers to the second heat-dissipating adhesive towards the side away from the carrier plate;
s18, packaging the second wafer by adopting a plastic packaging material, and forming a second plastic packaging layer after the plastic packaging material is solidified;
And S19, carrying out grinding treatment on the first plastic sealing layer and the second plastic sealing layer, so that the copper columns of the wafer are flush with the surface of the first plastic sealing layer after grinding, and the copper columns of the second wafer 12 are flush with the surface of the second plastic sealing layer after grinding.
As a preferred scheme of the preparation method of the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure, the step S40 specifically comprises the following steps:
S41, manufacturing a conductive copper column in the through hole through electroplating treatment, and manufacturing a copper plating layer on the seed layer;
S42, providing a photosensitive dry film, and attaching the photosensitive dry film to the copper plating layer;
s43, exposing and developing to form a pattern which exposes part of the copper plating layer to the photosensitive dry film on the photosensitive dry film;
S44, etching the copper plating layer and the seed layer exposed out of the photosensitive dry film to form the rewiring layer electrically connected with the conductive copper column;
S45, removing the residual photosensitive dry film.
As a preferred scheme of the preparation method of the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure, the step S50 specifically comprises the following steps:
S51, coating photosensitive ink on the surface of the chip plastic package body and the rewiring layer;
s52, exposing, developing and curing to form a solder mask layer exposing the pad area of the rewiring layer;
and S53, providing a metal bump, and implanting the metal bump into the pad area to be electrically connected with the rewiring layer.
As a preferred scheme of the preparation method of the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure, the components of the first heat dissipation adhesive and the second heat dissipation adhesive are the same, and the first heat dissipation adhesive and the second heat dissipation adhesive comprise graphene, silica gel, silicone grease, methyl vinyl polysiloxane mixture, methyl hydrogen polysiloxane mixture and aluminum oxide.
The invention has the beneficial effects that: the invention respectively sticks a heat dissipation layer on two sides of the carrier plate along the thickness direction, sticks a wafer with copper columns on the heat dissipation layer and encapsulates the wafer in a plastic layer to form a chip plastic package body; the through holes are formed in the chip plastic package body and used for electroplating the conductive copper columns, the circuit communication of the wafers at the two sides of the carrier plate is realized through the conductive copper columns, and the heat of the wafers is rapidly led out of the plastic package layer through the heat dissipation layer. Compared with the prior art, the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure has the advantages of small outline dimension, high three-dimensional stacking density and good heat dissipation effect, can keep the running smoothness of the functional chip, further improve the quality and performance of the semiconductor chip, and can effectively reduce the warpage.
Drawings
In order to more clearly illustrate the technical solution of the embodiments of the present invention, the drawings that are required to be used in the embodiments of the present invention will be briefly described below. It is evident that the drawings described below are only some embodiments of the present invention and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic cross-sectional view of an intermediate product with a heat dissipating adhesive attached to one side of a carrier according to an embodiment of the invention.
Fig. 2 is a schematic cross-sectional view of an intermediate product with a heat dissipating metal layer attached to a heat dissipating adhesive according to an embodiment of the invention.
Fig. 3 is a schematic cross-sectional view of an intermediate product with a heat dissipating metal layer attached to a heat dissipating adhesive according to an embodiment of the invention.
Fig. 4 is a schematic cross-sectional view of an intermediate product with a copper pillar die attached to a heat spreader according to an embodiment of the invention.
Fig. 5 is a schematic cross-sectional view of an intermediate product of a copper pillar die encapsulated in a plastic package according to an embodiment of the invention.
Fig. 6 is a schematic cross-sectional view of an intermediate product with another heat dissipation layer attached to the other side of the carrier according to an embodiment of the invention.
Fig. 7 is a schematic cross-sectional view of an intermediate product of another copper pillar die attached to another heat spreader according to an embodiment of the present invention.
Fig. 8 is a schematic cross-sectional view of an intermediate product of a wafer with copper pillars encapsulated in another plastic package according to an embodiment of the invention.
Fig. 9 is a schematic cross-sectional view of an intermediate product after grinding plastic sealing layers on both sides of a carrier according to an embodiment of the invention.
Fig. 10 is a schematic cross-sectional view of an intermediate product after drilling a hole and fabricating a seed layer in a chip molding compound according to an embodiment of the invention.
FIG. 11 is a schematic cross-sectional view of an intermediate product after fabrication of an EDL layer according to an embodiment of the present invention.
Fig. 12 is a schematic cross-sectional view of a product after manufacturing a solder mask layer and soldering a metal bump according to an embodiment of the invention.
In the figure:
1. A chip plastic package body; 11. a carrier plate; 12. a wafer; 13. a plastic sealing layer; 14. a heat-dissipating adhesive; 15. a heat-dissipating metal layer;
2. A seed layer;
3. Conductive copper pillars;
4. a rewiring layer;
5. A solder mask layer;
6. And a metal bump.
Detailed Description
The technical scheme of the invention is further described below by the specific embodiments with reference to the accompanying drawings.
Wherein the drawings are for illustrative purposes only and are shown in schematic, non-physical, and not intended to be limiting of the present patent; for the purpose of better illustrating embodiments of the invention, certain elements of the drawings may be omitted, enlarged or reduced and do not represent the size of the actual product; it will be appreciated by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The same or similar reference numbers in the drawings of embodiments of the invention correspond to the same or similar components; in the description of the present invention, it should be understood that, if the terms "upper", "lower", "left", "right", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, only for convenience in describing the present invention and simplifying the description, rather than indicating or implying that the apparatus or elements being referred to must have a specific orientation, be constructed and operated in a specific orientation, so that the terms describing the positional relationships in the drawings are merely for exemplary illustration and should not be construed as limiting the present patent, and that the specific meaning of the terms described above may be understood by those of ordinary skill in the art according to specific circumstances.
In the description of the present invention, unless explicitly stated and limited otherwise, the term "coupled" or the like should be interpreted broadly, as it may be fixedly coupled, detachably coupled, or integrally formed, as indicating the relationship of components; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between the two parts or interaction relationship between the two parts. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
If not specified, various raw materials used in the preparation method of the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure can be purchased commercially or prepared according to a conventional method in the technical field.
As shown in fig. 12, an embodiment of the present invention provides a high heat dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure, including:
The chip plastic package body 1 comprises a carrier plate 11, a wafer 12 with copper columns and a plastic package layer 13, wherein the wafer 12 is adhered to two sides of the carrier plate 11 through a heat dissipation layer, the wafer 12 is packaged in the plastic package layer 13, a plurality of through holes are formed in the chip plastic package body 1 along the thickness direction of the chip plastic package body, and the copper columns of the wafer 12 face to one side away from the carrier plate 11 and are exposed out of the plastic package layer 13;
A seed layer 2 located at a side of the plastic sealing layer 13 away from the carrier plate 11 and extending into the through hole to cover an inner wall of the through hole;
A conductive copper pillar 3 and a rerouting layer 4, wherein the conductive copper pillar 3 is positioned in the through hole and is electrically connected with the rerouting layer 4 on the seed layer 2, and the rerouting layer 4 is provided with a pad area and a non-pad area;
A solder resist layer 5 located on a side of the plastic sealing layer 13 away from the carrier 11 and covering a non-pad region of the rewiring layer 4;
and the metal bump 6 is welded with the bonding pad area of the rerouting layer 4.
In this embodiment, unless otherwise specified, the term "cover" refers to the outer surface that encloses a component in non-contact with other components. For example, the solder resist layer 5 covers the non-pad region of the rewiring layer 4, which means that the solder resist layer 5 wraps around the surface of the non-pad region of the rewiring layer 4 that is not in contact with the seed layer 2.
Alternatively, the metal bump 6 is a tin solder, a silver solder, or a gold-tin alloy solder, and the specific shape of the metal bump 6 is not limited.
In the embodiment, heat dissipation layers are respectively attached to two side surfaces of a carrier plate 11 along the thickness direction of the carrier plate, and a chip 12 with copper columns is attached to the heat dissipation layers and packaged in a plastic layer 13 to form a chip plastic package body 1; the through holes are formed in the chip plastic package body 1 and used for electroplating the conductive copper columns 3, the circuit communication of the wafers 12 on two sides of the carrier plate 11 is realized through the conductive copper columns 3, and the heat of the wafers 12 is rapidly led out of the plastic package layer 13 through the heat dissipation layer, and the wafers 12 are respectively packaged on two sides of the carrier plate 11, and the carrier plate 11 does not need to be disassembled after the packaging is completed, so that the warping can be effectively reduced. Compared with the prior art, the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure is small in outline dimension, large in three-dimensional stacking density and good in heat dissipation effect, can keep the running smoothness of the wafer 12, further improves the quality and performance of a semiconductor chip, and can effectively reduce warpage.
Further, the heat dissipation layer includes a heat dissipation adhesive 15 attached to the carrier 11 and a heat dissipation metal layer 16 attached to the heat dissipation adhesive 15, the heat dissipation metal layer 16 is in a hollow structure, and the die 12 is attached to the heat dissipation adhesive 15 and encapsulated in the plastic sealing layer 13. Because the heat dissipation metal layer 16 is a hollow structure, the heat dissipation metal layer 16 can be directly embedded into the heat dissipation glue 15, so that the heat dissipation metal layer 16 does not protrude from the surface of the heat dissipation glue 15, and the chip 12 can be attached to the heat dissipation glue 15, thereby facilitating subsequent packaging treatment.
Optionally, the heat dissipation metal layer 16 is any one of copper foil, aluminum foil, silver foil or gold foil, but is not limited thereto, and any metal layer having high thermal conductivity is suitable for the present invention.
Wherein the seed layer 2 comprises a titanium metal layer positioned on the plastic sealing layer 13 and the inner wall of the through hole and a copper metal layer positioned on the titanium metal layer. The titanium metal layer has high adhesion, excellent conductivity and uniform thickness, and the copper metal layer can be stably attached to the plastic layer 13 through the titanium metal layer.
Of course, the seed layer 2 of the present embodiment is not limited to a two-layer structure (titanium metal layer, copper metal layer), and may have a single layer or a structure of two or more layers. The material of the seed layer 2 is not limited to a lamination combination of two single metal materials, but may be a single metal material or an alloy material, so that the redistribution layer 4 can be stably attached to the chip plastic package 1, which is not described in detail.
In this embodiment, the solder mask layer 5 is a photosensitive ink layer. The photosensitive ink is used as the solder mask layer 5, which not only plays a role in protecting the rewiring layer 4, but also can remove part of the seed layer 2 and the copper plating layer through exposure, development and etching.
The redistribution layer 4 has at least one layer structure, i.e. can be designed into one layer, two layers, three layers or even more than three layers according to actual requirements.
The copper columns of the wafer 12 are flush with the surface of the plastic layer 13, so that the subsequent heat dissipation glue 15 is stably attached to the surface of the plastic layer 13 and covers the copper columns of the wafer 12.
Optionally, the carrier 11 is BT, FR4, FR5, PP, EMC, ABF or PI.
Optionally, the material of the plastic layer 13 includes polyimide, silica gel and EMC (Epoxy Molding Compound ), and in this embodiment, EMC is preferred, that is, the plastic layer 13 is an epoxy resin packaging layer, so that the wafer 12 can be stably attached to the carrier 11, and the effect of protecting the wafer 12 is achieved.
As shown in fig. 1 to 12, the embodiment of the invention further provides a preparation method of the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure, which comprises the following steps:
S10, providing a carrier plate 11, a heat dissipation layer and a plurality of wafers 12 with copper columns, enabling the front faces of the wafers 12 to face away from the carrier plate 11, respectively attaching the wafers 12 to two sides of the carrier plate 11 through the heat dissipation layer, and packaging and fixing the wafers 12 by adopting a plastic package material to obtain a chip plastic package body 1, wherein the chip plastic package body is shown in fig. 1-9;
S20, carrying out hole opening treatment on the chip plastic package body 1 to form a through hole penetrating through the chip plastic package body 1; specifically, the chip plastic package body 1 is subjected to hole opening treatment by laser, and Plasma cleaning is needed after the hole opening treatment so as to remove residues generated during laser hole opening;
S30, manufacturing seed layers 2 on two sides of the chip plastic package body 1 and the inner wall of the through hole, referring to FIG. 10;
S40, manufacturing a conductive copper column 3 in the through hole and manufacturing a rewiring layer 4 electrically connected with the conductive copper column 3 on the seed layer 2, referring to FIG. 11;
s50, providing a metal bump 6, and manufacturing a solder mask layer 5 on the rerouting layer 4, so that a pad area of the rerouting layer 4 is exposed and electrically connected with the metal bump 6, referring to FIG. 12.
The chip 12 is respectively attached to the two sides of the carrier plate 11 through the heat dissipation layers, and the chip 12 is respectively packaged on the two sides of the carrier plate 11 by adopting plastic packaging materials, so that the heat dissipation rate of the chip 12 is improved; then, the prepared chip package body 1 is subjected to hole opening treatment, and the seed layer 2 and the conductive copper column 3 are manufactured in the formed through hole, so that the circuit conduction of the rewiring layer 4 corresponding to the wafers 12 on two sides of the carrier plate 11 is realized, the carrier plate is not required to be dismantled after the prepared high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure is divided, and the warping problem of the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure is effectively solved.
In this embodiment, the plastic package materials used for packaging the wafer 12 are identical on both sides of the carrier 11, so that warpage can be further reduced.
Further, the step S10 specifically includes the following steps:
S11, providing a carrier 11 and a heat-dissipating adhesive 15 (first heat-dissipating adhesive), and attaching the heat-dissipating adhesive 15 to a first side of the carrier 11 along a thickness direction thereof, referring to FIG. 1; the material of the carrier 11 may be one of BT (Bismaleimide Triazine Resin), FR4, FR5, PP, EMC or PI, but is not limited thereto.
S12, providing a heat dissipation metal layer 16 (a first heat dissipation metal layer) with a hollow structure, and attaching the heat dissipation metal layer 16 to the heat dissipation glue 15, referring to FIG. 2 and FIG. 3; fig. 3a shows a mounting position of the wafer 12.
S13, providing a plurality of wafers 12 with copper columns, and attaching the front side of the wafers 12 facing away from the carrier plate 11 to the heat dissipation glue 15, referring to FIG. 4;
s14, packaging the wafer 12 by using a plastic packaging material, and forming a plastic packaging layer 13 (a first plastic packaging layer) after the plastic packaging material is solidified, referring to FIG. 5;
s15, providing another heat-dissipating adhesive 15 (second heat-dissipating adhesive), and attaching the heat-dissipating adhesive 15 to a second side of the carrier 11 opposite to the first side;
S16, providing a heat dissipation metal layer 16 (a second heat dissipation metal layer) with another hollow structure, and attaching the heat dissipation metal layer 16 to the heat dissipation glue 15, referring to FIG. 6;
S17, providing a plurality of wafers 12 (second wafers) with copper columns, and attaching the front sides of the wafers 12 to the heat dissipation glue 15 towards the side away from the carrier plate 11, referring to FIG. 7;
And S18, packaging the wafer 15 by using a plastic packaging material, and forming a plastic packaging layer 13 (a second plastic packaging layer) after the plastic packaging material is solidified, referring to FIG. 8.
And S19, grinding the two plastic sealing layers 13 (the first plastic sealing layer and the second plastic sealing layer) to enable copper columns of the wafers 12 (the first wafer and the second wafer) on two sides of the carrier plate 11 to be respectively flush with the surfaces of the corresponding ground plastic sealing layers 13, and referring to FIG. 9.
Further, step S40 in the present embodiment adopts a subtractive method to manufacture the redistribution layer 4, and specifically includes the following steps:
S41, manufacturing a conductive copper column 3 in the through hole through electroplating treatment, and manufacturing a copper plating layer on the seed layer 2;
S42, providing a photosensitive dry film, and attaching the photosensitive dry film to the copper plating layer;
s43, exposing and developing to form a pattern which exposes part of the copper plating layer to the photosensitive dry film on the photosensitive dry film;
S44, etching the copper plating layer and the seed layer 2 exposed out of the photosensitive dry film to form the rewiring layer 4 electrically connected with the conductive copper column 3;
S45, removing the residual photosensitive dry film.
The method for preparing the conductive copper pillars 3 and the copper plating layer by electroplating, the method for etching the seed layer 2 and the copper plating layer, and the like are all the prior art, and are not described in detail.
Further, the step S50 specifically includes the following steps:
S51, coating photosensitive ink on the surface of the chip plastic package body 1 and the rewiring layer 4;
s52, exposing, developing and curing to form a solder mask layer 5 exposing the pad area of the rewiring layer 4;
And S53, providing a metal bump 6, and implanting the metal bump 6 into the pad area to be electrically connected with the rewiring layer 4.
In this embodiment, the first heat-dissipating glue and the second heat-dissipating glue are permanent heat-dissipating glue, and the two heat-dissipating glue and the permanent heat-dissipating glue have the same components and include graphene, silica gel, silicone grease, methyl vinyl polysiloxane mixture, methyl hydrogen polysiloxane mixture and alumina.
In another embodiment of the present invention, the same as the above embodiment is basically different in that the redistribution layer 4 is fabricated by a half-additive method, which is not described in detail.
The high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure manufactured based on the fan-out type packaging technology not only can realize larger stacking density in the three-dimensional direction and smaller overall dimension, but also can simultaneously arrange heat dissipation glue and a heat dissipation metal covering layer on the back surfaces of a plurality of wafers in the size range of hundreds of millimeters, thereby greatly improving the heat dissipation performance of the wafers, further improving the quality and performance of semiconductor chips and effectively reducing warping.
The above examples are only for illustrating the detailed method of the present invention, and the present invention is not limited to the above detailed method, i.e., it does not mean that the present invention must be implemented depending on the above detailed method. It should be apparent to those skilled in the art that any modification of the present invention, equivalent substitution of raw materials for the product of the present invention, addition of auxiliary components, selection of specific modes, etc., falls within the scope of the present invention and the scope of disclosure.

Claims (8)

1. High heat dissipation fan-out type three-dimensional isomerism double-sided plastic envelope structure, its characterized in that includes:
The chip plastic package body comprises a carrier plate, a wafer with copper columns and a plastic package layer, wherein the wafer is attached to two sides of the carrier plate through a heat dissipation layer, the wafer is packaged in the plastic package layer, the chip plastic package body is provided with a plurality of through holes along the thickness direction of the chip plastic package body, and the copper columns of the wafer face to one side away from the carrier plate and are exposed out of the plastic package layer;
the seed layer is positioned on one side of the plastic sealing layer away from the carrier plate and extends into the through hole so as to cover the inner wall of the through hole;
The conductive copper column is positioned in the through hole and is electrically connected with the rewiring layer on the seed layer, and the rewiring layer is provided with a bonding pad area and a non-bonding pad area;
The solder mask layer is positioned on one side of the plastic sealing layer away from the carrier plate and covers the non-bonding pad area of the rewiring layer;
A metal bump welded with the pad area of the re-wiring layer, wherein the metal bump is tin solder, silver solder or gold-tin alloy solder;
the heat dissipation layer comprises heat dissipation glue attached to the carrier plate and a heat dissipation metal layer attached to the heat dissipation glue, the heat dissipation metal layer is of a hollow structure, and the wafer is attached to the heat dissipation glue and packaged in the plastic package layer.
2. The high heat dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure of claim 1, wherein the heat dissipation metal layer is any one of copper foil, aluminum foil, silver foil or gold foil.
3. The high heat dissipation fan-out three-dimensional heterogeneous double-sided plastic package structure of claim 1, wherein the seed layer comprises a titanium metal layer positioned on the plastic package layer and the inner wall of the through hole and a copper metal layer positioned on the titanium metal layer.
4. The high heat dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure of claim 1, wherein the solder mask layer is a photosensitive ink layer.
5. The preparation method of the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure is characterized by comprising the following steps of:
S10, preparing a chip plastic package body, which specifically comprises the following steps:
s11, providing a carrier plate and first heat dissipation glue, and attaching the first heat dissipation glue to a first side of the carrier plate along the thickness direction of the carrier plate;
s12, providing a first heat dissipation metal layer with a hollowed-out structure, and attaching the first heat dissipation metal layer to the first heat dissipation adhesive;
S13, providing a plurality of first wafers with copper columns, and attaching the front sides of the first wafers to the first heat-dissipating adhesive towards the side away from the carrier plate;
S14, packaging the first wafer by using a plastic packaging material, and forming a first plastic packaging layer after the plastic packaging material is solidified;
s15, providing a second heat dissipation adhesive, and attaching the second heat dissipation adhesive to a second side of the carrier plate opposite to the first side;
S16, providing a second heat dissipation metal layer with a hollowed-out structure, and attaching the second heat dissipation metal layer to the second heat dissipation adhesive;
s17, providing a plurality of second wafers with copper columns, and attaching the front sides of the second wafers to the second heat-dissipating adhesive towards the side away from the carrier plate;
s18, packaging the second wafer by adopting a plastic packaging material, and forming a second plastic packaging layer after the plastic packaging material is solidified;
S19, grinding the first plastic sealing layer and the second plastic sealing layer to enable copper columns of the first wafer to be flush with the surface of the first plastic sealing layer after grinding, and enable copper columns of the second wafer to be flush with the surface of the second plastic sealing layer after grinding;
s20, carrying out hole opening treatment on the chip plastic package body to form a through hole penetrating through the chip plastic package body;
s30, manufacturing seed layers on two sides of the chip plastic package body and on the inner wall of the through hole;
S40, manufacturing a conductive copper column in the through hole, and manufacturing a rewiring layer which is electrically connected with the conductive copper column on the seed layer;
s50, providing a metal bump, and manufacturing a solder mask layer on the rerouting layer to expose a bonding pad area of the rerouting layer and electrically connect the metal bump.
6. The method for preparing the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure according to claim 5, wherein the step S40 specifically comprises the following steps:
S41, manufacturing a conductive copper column in the through hole through electroplating treatment, and manufacturing a copper plating layer on the seed layer;
S42, providing a photosensitive dry film, and attaching the photosensitive dry film to the copper plating layer;
s43, exposing and developing to form a pattern which exposes part of the copper plating layer to the photosensitive dry film on the photosensitive dry film;
S44, etching the copper plating layer and the seed layer exposed out of the photosensitive dry film to form the rewiring layer electrically connected with the conductive copper column;
S45, removing the residual photosensitive dry film.
7. The method for preparing the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure according to claim 5, wherein the step S50 specifically comprises the following steps:
S51, coating photosensitive ink on the surface of the chip plastic package body and the rewiring layer;
s52, exposing, developing and curing to form a solder mask layer exposing the pad area of the rewiring layer;
and S53, providing a metal bump, and implanting the metal bump into the pad area to be electrically connected with the rewiring layer.
8. The method for preparing the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure according to claim 5, wherein the first heat dissipation glue and the second heat dissipation glue have the same components and comprise graphene, silica gel, silicone grease, methyl vinyl polysiloxane mixture, methyl hydrogen polysiloxane mixture and aluminum oxide.
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