CN110571157B - Method for manufacturing fine circuit capable of preventing lateral etching - Google Patents
Method for manufacturing fine circuit capable of preventing lateral etching Download PDFInfo
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- CN110571157B CN110571157B CN201910737646.0A CN201910737646A CN110571157B CN 110571157 B CN110571157 B CN 110571157B CN 201910737646 A CN201910737646 A CN 201910737646A CN 110571157 B CN110571157 B CN 110571157B
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 238000005530 etching Methods 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 73
- 229910052751 metal Inorganic materials 0.000 claims abstract description 73
- 238000004544 sputter deposition Methods 0.000 claims abstract description 21
- 239000007788 liquid Substances 0.000 claims abstract description 9
- 238000004806 packaging method and process Methods 0.000 claims abstract description 7
- 238000001312 dry etching Methods 0.000 claims abstract description 6
- 238000009713 electroplating Methods 0.000 claims abstract description 3
- 239000005022 packaging material Substances 0.000 claims abstract description 3
- 239000000463 material Substances 0.000 claims description 14
- 238000011161 development Methods 0.000 claims description 6
- 238000002844 melting Methods 0.000 claims description 3
- 238000012545 processing Methods 0.000 claims description 3
- 239000010949 copper Substances 0.000 abstract description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052802 copper Inorganic materials 0.000 abstract description 8
- 230000003628 erosive effect Effects 0.000 abstract description 6
- 239000000126 substance Substances 0.000 description 6
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 239000000654 additive Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000002585 base Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000000135 prohibitive effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a method for manufacturing a fine circuit for preventing lateral erosion, which comprises the following steps: providing a chip, and plastically packaging the chip by using a plastic packaging material to form a plastic mould plate; measuring the offset of the chip, and sputtering a first metal seed layer and a second metal seed layer on the plastic mould plate; pasting a photosensitive dry film on the surface of the second metal seed layer, correcting exposure parameters by combining the previously measured chip offset, and obtaining a groove through developing treatment; electroplating thick copper in the groove to fill the groove, and removing the photosensitive dry film by adopting a film removing liquid to form a fine circuit; sputtering a third metal seed layer on the surface of the fine circuit to ensure that the third metal seed layer is attached to the surface and the side wall of the fine circuit; and etching the third metal seed layer in the horizontal direction by adopting a dry etching method, and then performing flash etching on the first metal seed layer and the second metal seed layer at the bottom by adopting a wet method. The method for manufacturing the fine circuit capable of preventing the side etching can effectively solve the side etching problem of manufacturing the high-precision circuit.
Description
Technical Field
The invention relates to the technical field of board-level fan-out type packaging, in particular to a manufacturing method of a fine circuit for preventing lateral erosion.
Background
Since the last 60's of the century, the development of semiconductor technology has followed moore's law, but as the feature size of integrated circuits has decreased below 14nm, semiconductor technology has gradually approached the limits of silicon technology, thereby requiring the expense of more development and equipment for upgrading wafer fabrication, making the cost of providing such in the manufacture of semiconductor devices prohibitive. The development direction of future products is high-density integration and volume miniaturization, the improvement of product performance in the post-Mole era is a technical breakthrough depending on advanced packaging, board-level fan-out type packaging is one of advanced packaging representatives, and if the high-density integration of chip products is to be realized, the fine circuit manufacturing aspect becomes a difficult point needing breakthrough.
In the fabrication of thin lines for high-end package substrates, SAP (Semi-Additive Process) Semi-Additive method is generally adopted, while in the board-level fan-out package, fine lines are prepared by Semi-Additive method, and chemical copper with a thickness of about 1 μm is generally deposited on the material, and then copper wires with patterns are electroplated on the chemical copper. The loose texture of the chemical copper layer causes the weak bonding force between the circuit and the base material, and the problem of circuit peeling easily occurs when a fine circuit pattern is manufactured. In order to increase the bonding force of the electroless copper layer, the roughness of the surface of the material must be increased, which increases the difficulty in making fine lines. The other method is to deposit Ti/Cu by using PVD equipment, wherein the deposition thickness is only 100nm/300nm, and the bonding force of the deposition layer and the dielectric material is far better than that of the chemical copper layer; and the thickness of the deposited metal is thinner and is only 0.4 mu m, so that when the Seed Layer is removed, the smaller Under Cut (side etching) of the circuit can be ensured, and the appearance and the reliability of the circuit are better.
However, the two methods cannot fundamentally solve the problem of Under Cut, and the problem is particularly important in the preparation of circuits with the line width and the line distance of 15 μm/15 μm and below, which affects the yield of the whole product.
Disclosure of Invention
The invention provides a method for manufacturing a fine circuit capable of preventing lateral erosion, which can effectively solve the lateral erosion problem of manufacturing a high-precision circuit.
The technical scheme adopted by the invention is as follows: a method for manufacturing a fine circuit for preventing undercut comprises the following steps:
s1: providing a chip, and plastically packaging the chip by using a plastic packaging material to form a plastic mould plate;
s2: measuring the offset of the chip by using a chip offset (die shift) AOI device, and then sputtering a first metal seed layer and a second metal seed layer on the upward surface of the front side of the chip of the plastic mould plate in sequence by using a vacuum sputtering device;
s3: adhering a photosensitive dry film on the surface of the second metal seed layer, correcting exposure parameters by combining the chip offset measured in S2, and then carrying out development processing to obtain a groove;
s4: electroplating the same material as the second metal seed layer in the groove to fill the groove, and removing the photosensitive dry film by adopting a film removing liquid to form a fine circuit;
s5: sputtering a third metal seed layer on the surface of the fine circuit by using vacuum sputtering equipment, so that the third metal seed layer is attached to the surface and the side wall of the fine circuit;
s6: and etching the third metal seed layer in the horizontal direction by adopting a dry etching method, and then performing flash etching on the first metal seed layer and the second metal seed layer at the bottom by adopting a wet method.
Further, in S2, the first metal seed layer is a Ti layer, a Ni layer, an Al layer, or a Pd layer.
Further, in S2, the thickness of the first metal seed layer is 0.1nm to 10 um.
Further, in S2, the second metal seed layer is a Cu layer, an Ag layer, an Al layer, or an Au layer.
Further, in S2, the thickness of the second metal seed layer is 0.1nm to 10 um.
Further, in S4, the method of removing is an organic-inorganic method or an organic-melting method.
Further, in S5, the third metal seed layer and the first metal seed layer have the same structure and material.
Further, in S2 and S5, the temperature of sputtering is controlled to 150 ℃ or less.
Further, in S6, the flash etching solution used in the wet flash etching is H2SO4-H2O2And (4) etching liquid.
Further, in S2, the first metal seed layer and the second metal seed layer are different in structure and material.
Compared with the prior art, the manufacturing method of the fine line for preventing the side etching can etch the third seed layer in the Z direction quickly by sputtering the third metal seed layer and adopting dry etching to etch downwards, at the moment, the third metal seed layer on the side wall is remained to protect the fine line, and then the first metal seed layer and the second metal seed layer are etched quickly by adopting a flash etching mode, so that the defect of line shape and position size caused by the fact that the material of the second metal seed layer is consistent with that of the fine line and an etching liquid bites the fine line on the side simultaneously in the downward biting process in the wet etching process is avoided, the integrity of the fine line is ensured to the maximum extent, the reliability of a packaged component is further ensured, and the problem of the side etching (Under Cut) is fundamentally solved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings, there is shown in the drawings,
FIG. 1: the invention prevents the step flow chart of the manufacturing approach of the fine circuit of the side etching;
FIG. 2: the invention discloses a flow diagram of a manufacturing method of a fine circuit for preventing lateral erosion.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.
As shown in fig. 1 and 2, the method for fabricating a fine line for preventing undercut of the present invention comprises the steps of:
s1: providing a chip 1, and carrying out plastic package on the chip 1 by a plastic package material to form a plastic mold plate 2.
S2: measuring the offset of the chip 1 by using a chip offset (die shift) AOI device, and then sputtering a first metal seed layer 3 and a second metal seed layer 4 on the upward front surface of the chip 1 of the molding plate 2 in sequence by using a vacuum sputtering device. The first metal seed layer 3 is a Ti layer, a Ni layer, an Al layer, a Pd layer, etc., and the thickness of the first metal seed layer 3 is 0.1nm-10 um. The second metal seed layer 4 is a Cu layer, an Ag layer, an Al layer or an Au layer, and the thickness of the second metal seed layer 4 is 0.1nm-10 um. The temperature of sputtering is controlled below 150 ℃.
S3: the photosensitive dry film 5 is attached to the surface of the second metal seed layer 4, and the exposure parameters are corrected by combining the offset of the chip 1 measured before (in S2), and then the groove 6 is obtained through development processing.
S4: the same material as the second metal seed layer 4 is electroplated in the groove 6 to fill the groove 6, and the photosensitive dry film 5 is removed by using a stripping solution to form a fine line 8. The film removing method can adopt an organic and inorganic film removing method or an organic and melting film removing method according to the film removing difficulty, and the used film removing solution is NaOH solution.
S5: and sputtering a third metal seed layer 7 on the surface of the fine line 8 by using vacuum sputtering equipment, so that the third metal seed layer 7 is attached to the surface and the side wall of the fine line 8. The structure and material of the third metal seed layer 7 are the same as those of the first metal seed layer 3, and are different from those of the second metal seed layer 4. The temperature of sputtering is controlled below 150 ℃.
S6: and etching the third metal seed layer 7 in the horizontal direction by adopting a dry etching method, and then performing flash etching on the first metal seed layer 3 and the second metal seed layer 4 at the bottom by adopting a wet method to finish the manufacture of the fine circuit 8. Wherein the flash etching solution used in the wet flash etching is H2SO4-H2O2And (4) etching liquid.
In summary, the method for manufacturing the fine circuit for preventing the lateral erosion has the following beneficial effects:
1. the third metal seed layer 7 is sputtered, the third seed layer 7 can be quickly etched in the Z direction by adopting dry etching, at the moment, the third metal seed layer 7 on the side wall is remained to protect the fine line 8, and then the first metal seed layer 3 and the second metal seed layer 4 are quickly etched by adopting a flash etching mode, so that the defect of line shape and position size caused by the fact that the material of the second metal seed layer 4 is consistent with the fine line 8 and the etching liquid simultaneously bites the fine line 8 on the side in the downward biting process in the wet etching process is avoided, the integrity of the fine line 8 is furthest ensured, the reliability of the packaged component is further ensured, and the problem of side etching (Under Cut) is fundamentally solved.
2. The first metal seed layer 3 and the second metal seed layer 4 are prepared by adopting a vacuum sputtering method, and the first seed layer and the second seed layer are partially arranged on the photosensitive dry film 5, and the photosensitive dry film 5 is acid-resistant and alkali-resistant, so that the chemical coating liquid is prevented from corroding the photosensitive dry film 5 during chemical copper plating by adopting the low-temperature vacuum sputtering method for the first metal seed layer 3 and the second metal seed layer 4, and the photosensitive dry film 5 can be protected from being influenced in the preparation process.
Any combination of the various embodiments of the present invention should be considered as disclosed in the present invention, unless the inventive concept is contrary to the present invention; within the scope of the technical idea of the invention, any combination of various simple modifications and different embodiments of the technical solution without departing from the inventive idea of the present invention shall fall within the protection scope of the present invention.
Claims (10)
1. A method for manufacturing a fine circuit capable of preventing lateral etching is characterized by comprising the following steps:
s1: providing a chip, and plastically packaging the chip by using a plastic packaging material to form a plastic mould plate;
s2: measuring the offset of the chip by using a chip offset (die shift) AOI device, and then sputtering a first metal seed layer and a second metal seed layer on the upward surface of the front side of the chip of the plastic mould plate in sequence by using a vacuum sputtering device;
s3: adhering a photosensitive dry film on the surface of the second metal seed layer, correcting exposure parameters by combining the chip offset measured in S2, and then carrying out development processing to obtain a groove;
s4: electroplating the same material as the second metal seed layer in the groove to fill the groove, and removing the photosensitive dry film by adopting a film removing liquid to form a fine circuit;
s5: sputtering a third metal seed layer on the surface of the fine circuit by using vacuum sputtering equipment, so that the third metal seed layer is attached to the surface and the side wall of the fine circuit;
s6: and etching the third metal seed layer in the horizontal direction by adopting a dry etching method, and then performing flash etching on the first metal seed layer and the second metal seed layer at the bottom by adopting a wet method.
2. The method of manufacturing a fine line for preventing undercut as claimed in claim 1, wherein: in S2, the first metal seed layer is a Ti layer, a Ni layer, an Al layer, or a Pd layer.
3. The method of manufacturing a fine line for preventing undercut as claimed in claim 1, wherein: in S2, the thickness of the first metal seed layer is 0.1nm-10 um.
4. The method of manufacturing a fine line for preventing undercut as claimed in claim 1, wherein: in S2, the second metal seed layer is a Cu layer, an Ag layer, an Al layer, or an Au layer.
5. The method of manufacturing a fine line for preventing undercut as claimed in claim 1, wherein: in S2, the thickness of the second metal seed layer is 0.1nm-10 um.
6. The method of manufacturing a fine line for preventing undercut as claimed in claim 1, wherein: in S4, the method for removing a film is an organic-inorganic method for removing a film or an organic-melting method for removing a film.
7. The method of manufacturing a fine line for preventing undercut as claimed in claim 1, wherein: in S5, the third metal seed layer and the first metal seed layer have the same structure and material.
8. The method of manufacturing a fine line for preventing undercut as claimed in claim 1, wherein: in S2 and S5, the temperature of sputtering is controlled to 150 ℃ or lower.
9. The method of manufacturing a fine line for preventing undercut as claimed in claim 1, wherein: in S6, the flash etching solution used in the wet flash etching is H2SO4-H2O2And (4) etching liquid.
10. The method of manufacturing a fine line for preventing undercut as claimed in claim 1, wherein: in S2, the first metal seed layer and the second metal seed layer are different in structure and material.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910737646.0A CN110571157B (en) | 2019-08-12 | 2019-08-12 | Method for manufacturing fine circuit capable of preventing lateral etching |
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| CN201910737646.0A CN110571157B (en) | 2019-08-12 | 2019-08-12 | Method for manufacturing fine circuit capable of preventing lateral etching |
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| CN110571157A CN110571157A (en) | 2019-12-13 |
| CN110571157B true CN110571157B (en) | 2020-12-18 |
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| CN112626472A (en) * | 2020-10-26 | 2021-04-09 | 威科赛乐微电子股份有限公司 | Preparation method of VCSEL array chip P-surface connecting metal |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101572244A (en) * | 2005-05-18 | 2009-11-04 | 米辑电子股份有限公司 | Circuit assembly manufacturing method |
| CN104411106A (en) * | 2014-11-14 | 2015-03-11 | 电子科技大学 | Manufacturing method of fine circuit of printed-circuit board |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1212753C (en) * | 2001-06-19 | 2005-07-27 | 华通电脑股份有限公司 | Method for forming high-density ultra-fine lines on fiber substrate |
| CN101312620B (en) * | 2007-05-24 | 2011-06-22 | 巨擘科技股份有限公司 | Manufacturing method and structure of multilayer substrate metal circuit |
| CN201892523U (en) * | 2010-11-05 | 2011-07-06 | 久元电子股份有限公司 | Detection device for detecting offset of light-emitting diode chips |
| CN103745937B (en) * | 2014-02-08 | 2016-06-01 | 华进半导体封装先导技术研发中心有限公司 | The manufacture craft of fan-out wafer level package |
| US10297551B2 (en) * | 2016-08-12 | 2019-05-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing redistribution circuit structure and method of manufacturing integrated fan-out package |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101572244A (en) * | 2005-05-18 | 2009-11-04 | 米辑电子股份有限公司 | Circuit assembly manufacturing method |
| CN104411106A (en) * | 2014-11-14 | 2015-03-11 | 电子科技大学 | Manufacturing method of fine circuit of printed-circuit board |
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Effective date of registration: 20230410 Address after: Room A107, scientific research building, block a, neifo high tech think tank center, Nanhai Software Science Park, Shishan town, Nanhai District, Foshan City, Guangdong Province, 528225 Patentee after: Guangdong fozhixin microelectronics technology research Co.,Ltd. Address before: 528225 room 208, scientific research building, block A1, Buddha high tech think tank center, Nanhai software technology park, Shishan town, Foshan City, Guangdong Province Patentee before: Guangdong fozhixin microelectronics technology research Co.,Ltd. Patentee before: Guangdong Xinhua Microelectronics Technology Co.,Ltd. |
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