CN110570803A - A system for increasing effective display digits - Google Patents

Abstract

The invention discloses a system for increasing effective display digits. The display system for increasing effective display digits mainly includes an address/data receiving and processing module, a row and column drive control logic module, a DAC module, a data latch/drive module, and an address decoding module. Modules, pixel units, common electrodes and modules for increasing the number of effective display bits. The length of the display time in the frame period of the pixel unit is controlled by digital data information, so as to realize the adjustment of grayscale brightness.

Description

A system for increasing effective display digits

technical field

The invention relates to the technical field of digital pixel driving, in particular to a novel system for increasing effective display digits.

Background technique

With the continuous development of micro-display products such as AR (Augmented Reality) and projection products, people begin to pay attention to the research on improving the performance of micro-display chips. Micro-display chips are mainly divided into micro-display technology and micro-display driving technology. Good driving technology, especially good pixel driving technology, can improve the display effect of micro-display chips.

At present, pixel driving methods are mainly divided into two types: analog driving and digital driving. Analog-driven displays use analog signals to represent grayscale information of pixels, but analog signals are prone to noise, making it difficult to achieve high grayscale value accuracy. Digital drive mainly produces grayscale by modulating pulse width. Due to the stable and reliable digital signal and fast switching speed, the digital drive has high picture quality, low image noise, high gray scale level, and can display richer colors.

Contents of the invention

In order to overcome the defects in the prior art, the present invention provides a system for increasing the number of effective display digits, which can realize the adjustment of grayscale brightness and avoid inter-frame interference displayed by display devices.

The invention provides a system for increasing the number of effective display digits, and the content of the invention is as follows:

The system of a novel digital pixel driving mode mainly includes an address/data receiving and processing module, a row and column driving control logic module, a DAC module, a data latch/driving module, an address decoding module, a pixel unit, a common electrode and an effective display module. number of modules.

The address/data receiving and processing module extracts the received address and data signals, extracts the address signals and transmits them to the row and column drive control logic module, extracts the data signals and transmits them to the data latch/drive module;

The row and column drive control logic module receives the address signal transmitted by the address/data receiving and processing module, encodes the address signal, and generates the corresponding row data control signal, common electrode signal and in-phase/inversion selection signal according to the address signal, and converts the row data The control signal is sent to the data latch/drive module; the address signal is sent to the address decoding module; the common electrode signal is sent to the common electrode; the in-phase/inversion selection signal is sent to the pixel unit;

The data latch/drive module latches and sends data to the pixel unit according to the received row data control signal;

The DAC module converts the digital signal into a voltage value and sends it to the pixel unit to realize the display brightness control of the pixel unit;

The module that increases the number of effective display bits generates additional data bits based on the received data and sends them to the data latch/driver module.

Furthermore, the module for increasing the number of effective display bits generates extra data bits in addition to the 8-bit normal pixel data, which are used to compensate the threshold voltage of the display device in digital display mode and avoid inter-frame interference displayed by the display device.

Further, each bit of the normal 8-bit pixel data and the additional data bits generated by the module that increases the number of effective display bits is divided into multiple or continuous displays at any display moment of the same frame according to requirements, and the timing of the bits is fixed or random , or different timings are used for different frames.

Further, the address/data receiving and processing module can receive data transmitted by mipi interface, lvds interface and other types of interfaces, and the data signal mainly includes the row address and the data of the corresponding row.

The receiving end of the address/data receiving and processing module is connected to the high-speed interface, and receives the address and data signals transmitted by the high-speed interface. The address/data receiving and processing module extracts the received address and data signals, extracts the address signals and transmits them to the ranks The drive control logic module extracts the data signal and transmits it to the data latch/drive module.

The row and column drive control logic module receives the address signal transmitted by the address/data receiving and processing module, and sends the row data control signal to the data latch/drive module; sends the control signal to the address decoding module, the common electrode and the pixel unit .

All rows of pixels in the pixel unit share one DAC module, or several rows of pixels share one DAC module, or each row of pixels uses a separate DAC module.

The DAC (Digital-to-Analog Converter) module can convert the digital signal into a voltage value and send it to the pixel, and can control the magnitude of the voltage value, so that the brightness of the display screen can be controlled.

The data latch/drive module receives the control signal sent by the row and column drive control logic module, and latches and sends the data to the pixel according to the control signal. The data sent to the pixel can be sent row by row, and also includes combining several rows together send.

The address decoding module is composed of several input AND gates, and each line selects the corresponding address connection mode to connect to the address bus, and the address is driven to the address bus after encoding.

The pixel unit includes a storage unit, a logical operation unit, a driving unit, and a display unit. The storage unit receives the address signal and the data signal, has a storage function, and sends the signal to the logic operation unit. The logic operation unit receives the inverse and phase control commands, processes the signals sent by the storage unit, and sends them to the drive unit. The driving unit processes the received data signal of the driving unit and the voltage signal of the DAC (Digital-to-Analog Converter) module, and sends them to the display unit. The display unit displays corresponding images according to the received image data signals.

The common electrode is a common terminal electrode connected to one terminal of all pixels, one terminal of each pixel is connected to the common electrode, and one terminal is independently connected to the pixel driving circuit.

The module for increasing the number of effective display bits generates the required additional data bits according to the input 8-bit pixel data, sends them to the storage unit or the drive unit, and sends them to the corresponding pixel for display according to the address selection, so as to achieve the effect of increasing the effective display bits.

The beneficial effect that the present invention reaches:

The invention adjusts the digital data information by increasing the number of effective display digits to control the length of the display time in the frame period of the pixel unit, thereby realizing the adjustment of the gray scale brightness and avoiding the interframe interference displayed by the display device.

Description of drawings

FIG. 1 is a system frame diagram of Embodiment 1 of a new digital pixel driving method of the present invention.

FIG. 2 is a structural diagram of an address decoding module according to Embodiment 1 of the present invention.

FIG. 3 is a structural diagram of a pixel unit according to Embodiment 1 of the present invention.

FIG. 4 is a structural diagram of a storage unit in a pixel unit according to Embodiment 1 of the present invention.

FIG. 5 is a structural diagram of a logic operation unit in a pixel unit according to Embodiment 1 of the present invention.

FIG. 6 is a structural diagram of a driving unit in a pixel unit according to Embodiment 1 of the present invention.

FIG. 7 is a structural diagram of an LCOS display unit in a pixel unit according to Embodiment 1 of the present invention.

8A-8E are diagrams showing time distribution of data display for increasing effective display digits according to Embodiment 1 of the present invention.

FIG. 9 is a system frame diagram of Embodiment 2 of a new digital pixel driving method of the present invention.

FIG. 10 is a structural diagram of an address decoding module according to Embodiment 2 of the present invention.

FIG. 11 is a structural diagram of a pixel unit according to Embodiment 2 of the present invention.

FIG. 12 is a structural diagram of a storage unit in a pixel unit according to Embodiment 2 of the present invention.

FIG. 13 is a structural diagram of a logic operation unit in a pixel unit according to Embodiment 2 of the present invention.

FIG. 14 is a structural diagram of a driving unit in a pixel unit according to Embodiment 2 of the present invention.

FIG. 15 is a structural diagram of an OLED display unit in a pixel unit according to Embodiment 2 of the present invention.

16A-16E are data display time distribution diagrams for increasing effective display digits according to Embodiment 2 of the present invention.

Among them: 11. Address/data receiving and processing module, 12. Row and column drive control logic module, 13. DAC module, 14. Data latch/drive module, 15. Address decoding module, 16. Pixel unit, 17. Common electrode, 18. Storage unit, 19. Serial operation unit, 20. Module for increasing effective display digits, 110. Drive unit, 111. LCOS display unit, 1121, 1124, 1125, 1126, 1133, 1134, 1142 are N-type MOS tubes, 1122, 1123, 1131, 1132, 1141 are P-type MOS tubes, 1151, transparent electrode liquid crystal, 1152, liquid crystal, 1153, metal reflective layer, 1154, silicon substrate, 310, normal pixel data display time, 320, increase effective display bits Display time, 311, 312, 313, 314, segmented normal pixel data display time, 321, 322, 323, 324, segmented increased effective display bit display time;

21. Address/data receiving and processing module, 22. Row and column drive control logic module, 23. DAC (digital-to-analog converter) module, 24. Data latch/drive module, 25. Address decoding module, 26. Pixel unit, 27 , common electrode, 28, storage unit, 29, series operation unit, 30, module for increasing effective display digits, 210, drive unit, 211, LCOS display unit, 2121, 2124, 2125, 2126, 2133, 2134, 2142 are N Type MOS tubes, 2122, 2123, 2131, 2132, 2141 are P-type MOS tubes, 2156, silicon substrate, 2155, metal reflective layer, 2154, white OLED light-emitting layer, 2153, RGB color filter film, 2152, translucent cathode, 2151, transparent glass, 410, normal pixel data display time, 420, increase effective display bit display time, 411, 412, 413, 414, segmented normal pixel data display time, 421, 422, 423, 424, segmented Increase the effective display bit to display the time.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the embodiments of the present invention and the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

In order to describe this patent in detail, the following specific examples are used to illustrate.

Embodiment one

Embodiment 1 is a micro-display chip driven by digital pixels based on LCOS (liquid crystal on silicon), the pixel resolution is 1920*1080, and the color rendering method is sequential color.

As shown in Figure 1, the micro-display chip system based on LCOS digital pixel drive mainly includes an address/data receiving and processing module 11, a row and column drive control logic module 12, a DAC module 13, a data latch/drive module 14, and an address decoding module 15 , a pixel unit 16, a common electrode 17 and a module 20 for increasing the number of effective display bits.

The high-speed interface can use mipi interface or lvds interface, etc., and each time the row address and the data of the corresponding row are sent. The address/data receiving and processing module 11 receives one end connected to the high-speed interface, receives the address and data signals transmitted by the high-speed interface, the address/data receiving and processing module 11 extracts the received address and data signals, and extracts the address signals for transmission The row and column drive control logic module 12 extracts the data signal and transmits it to the data latch/drive module 14 .

The row and column drive control logic module 12 receives the address signal transmitted by the address/data receiving and processing module 11, encodes the address signal, and generates the corresponding row data control signal, common electrode signal and in-phase/inversion selection signal according to the address signal. Send the row data control signal to the data latch/drive module 14; send the address signal to the address decoding module 15; send the common electrode signal to the common electrode 17; send the in-phase/inversion selection signal to the pixel unit 16, which It is because the voltage at both ends of the liquid crystal has to be in a state of exchange, otherwise its characteristics will change.

The data latch/drive module 14 receives the row data control signal sent by the row and column drive control logic module 12, and latches and sends the data to the pixel unit 16 according to the row data control signal. What this embodiment uses is every 60 columns of data, a total of The transmission is completed by 32 data lines. The method of sending the patent data of the present invention to the pixel unit can be sent row by row, and also includes sending several rows together.

The common electrode 17 is a common electrode connected to one end of all the pixel units 16 . The common electrode 17 is a semi-transparent conductive electrode, and can be made of ITO, a semi-transparent metal element, a semi-transparent metal compound or other semi-transparent conductive materials.

As shown in Figure 2, the address decoding module 15, the address and the inversion signal of the address form the address bus, for the resolution of 1920*1080, a total of 1080 address decoding modules 15 are needed, and each address decoding module 15 is 11 Bit address data, the address bus has a total of 22 bits. The address decoding module 15 is composed of 6-way input AND gates, and each line selects the corresponding address connection mode to connect to the address bus. The address is encoded and driven onto the address bus. For 1080 address bits, four input options are required for each of the lower five bits, and two input options are required for the highest bit. A total of 22-bit address bus is required to realize all 1080 address bit encodings.

FIG. 3 is a structural diagram of the pixel unit 16 . The pixel unit 16 includes a storage unit 18 , a logical operation unit 19 , a driving unit 110 and an LCOS display unit 111 . The storage unit 18 receives the address signal and the data signal, has a storage function, and sends the signal to the logic operation unit 19 . The logic operation unit 19 receives the inverse and phase control commands, processes the signals sent by the storage unit 18 , and sends them to the drive unit 110 . The driving unit 110 processes the received data signal and the voltage signal of the DAC module 13 and sends it to the LCOS display unit 111 . The LCOS display unit 111 displays a corresponding image according to the received image data signal.

As shown in Figure 4, it is a structural diagram of the storage unit 18, wherein 1121, 1124, 1125, and 1126 are N-type MOS transistors, and 1122 and 1123 are P-type MOS transistors. The specific process for the storage unit 18 to realize the storage function is when address decoding The address signal ADDR sent by the module 15 is high, 1121 and 1124 are turned on, and the data signals Data 1 and Data 2 enter the storage devices 1122 , 1123 , 1125 , and 1126 through 1121 and 1124 respectively. Data 1 and data 2 are always opposite. When the data signal enters the storage device, ADDR becomes low level, and 1121 and 1124 are disconnected. At this time, the inverter composed of 1122 and 1125 and the inverter composed of 1123 and 1126 are composed The storage unit will store data 1 and data 2 in the storage unit without loss, and output the output signal 1 and output signal 2 of the storage unit 18 as the input signal 1 and input signal 2 of the logic operation unit 19.

Figure 5 is a structural diagram of the logical operation unit 19, wherein 1133 and 1134 are N-type MOS transistors, 1131 and 1132 are P-type MOS transistors, and the input signal 1 and input signal 2 are always opposite signals. When the phase selection signal is high, input signal 1 is high, and input signal 2 is low, the inverter composed of 1131 and 1133 works normally, the switch composed of 1132 and 1134 is disconnected, and the output signal is low. When the phase selection signal is high, input signal 1 is low, and input signal 2 is high, then the inverter composed of 1131 and 1133 does not work, the switch composed of 1132 and 1134 is turned on, and the output signal is high. When the in-phase and phase-inversion selection signal is low, input signal 1 is high, and input signal 2 is low, then the inverter composed of 1131 and 1133 works normally, the switch composed of 1132 and 1134 is disconnected, and the output signal is high level. When the phase selection signal is low, input signal 1 is low, and input signal 2 is high, then the inverter composed of 1131 and 1133 does not work, the switch composed of 1132 and 1134 is turned on, and the output signal is low. The output signal of the logic operation unit 19 is used as the input signal of the driving unit 110 .

As shown in Figure 6 is the structural diagram of the driving unit 110, wherein 1141 is a P-type MOS transistor, 1142 is an N-type MOS transistor, and 1141 and 1142 form an inverter driving unit. When the input signal of the driving unit 110 is at a high level, after The driving unit 110 performs reverse processing, and the output signal is low level, and the analog voltage values of high and low levels are determined by the signals Vhigh and Vlow output by the DAC module 13 . When the Vhigh output by the DAC module 13 is closer to the circuit high voltage and Vlow is closer to the circuit low voltage, the brightness displayed by the LCOS display unit 111 is higher; otherwise, the brightness displayed by the LCOS display unit 111 is lower, and the DAC module 13 can display The brightness of the environment is used to set and adjust the brightness of the LCOS display unit 111 .

As shown in Figure 7, it is a structural diagram of the LCOS display unit 111, which includes a silicon substrate 1154, a metal reflective layer 1153 is arranged above the silicon substrate 1154, a liquid crystal 1152 is arranged above the metal reflective layer 1153, and a liquid crystal 1152 is arranged on the top of the silicon substrate 1154. A transparent electrode 1151 is provided above. Types of the liquid crystal 1152 include parallel alignment liquid crystals and vertical alignment liquid crystals, and vertical alignment liquid crystals are used in this embodiment. One end of the liquid crystal 1152 is connected to the metal reflective layer 1153, and the other end is connected to the silicon substrate 1154 through the metal reflective layer 1153. Driven by the driving unit 110, external light enters the liquid crystal 1152 through the transparent electrode 1151, passes through the metal reflective layer 1153, the liquid crystal 1152 and the The transparent electrode 1151 is reflected back, so as to realize the display of images.

The module 20 for increasing the number of effective display bits can generate extra data bits besides 8-bit normal pixel data to increase the number of effective display bits, compensate the liquid crystal threshold voltage of the digital display mode, and avoid inter-frame interference.

Each bit of the normal 8-bit pixel data and the extra data bits generated by the module 20 that increases the number of effective display bits can be divided into multiple or continuously displayed at any display moment of the same frame, and the timing of the bits can be random , different frames can adopt different timings.

As shown in Figures 8A-8E, the display time distribution of the LCOS display chip after increasing the effective display bits includes normal pixel data bit display time 310, increased effective display bit display time 320, normal pixel data bit display times 311 and 312, and increased The effective display bits display the time 321 and 322 . The display time of the increased effective display bits and normal pixel data bits can be freely matched. As shown in Figure 8A, the normal pixel data is first displayed as 310, and then the increased effective display data bit 320 is displayed; or as shown in Figure 8B, the increased effective display data bit 320 is first displayed, and then the normal pixel data is displayed as 310 It can also be shown as 311 and 312 in normal pixel data segmentation as shown in Figure 8C, and the effective display data bit that increases is inserted in the middle and shows 320; It can also be shown in Figure 8D that normal pixel data segmentation is displayed as 311 and 312, the increased effective display data bits are segmented into 321 and 322, and then their display order is arbitrarily combined; even as shown in Figure 8E, the normal pixel data 311, 312, 313, 314 can be divided into any number of segments , divide the increased effective display data bits 321, 322, 323, 324 into any number of segments, and then display them in combination.

Embodiment two

Embodiment 2 is a micro-display chip driven by OLED digital pixels. The resolution of the pixels is 1280*540*RGB.

As shown in Figure 9, the micro-display chip system based on OLED digital pixel drive mainly includes an address/data receiving and processing module 21, a row and column drive control logic module 22, a DAC module 23, a data latch/drive module 24, and an address decoding module 25 , a pixel unit 26, a common electrode 27 and a module 28 for increasing the number of effective display bits.

The high-speed interface can use mipi interface or lvds interface, etc., and each time the row address and the data of the corresponding row are sent. The address/data receiving and processing module 21 receives one end connected to the high-speed interface, receives the address and data signals transmitted by the high-speed interface, and the address/data receiving and processing module 21 extracts the received address and data signals, and extracts the address signals for transmission The row and column drive control logic module 22 extracts the data signal and transmits it to the data latch/drive module 24 .

The row and column drive control logic module 22 receives the address signal transmitted by the address/data receiving and processing module 21, and sends the row data control signal to the data latch/drive module 24; sends the address signal to the address decoding module 25; sent to the common electrode 27.

The data latch/drive module 24 receives the control signal sent by the row and column drive control logic module 22, and latches and sends the data to the pixels according to the control signal. In this embodiment, every 60 columns of data are used, and a total of 96 data lines are used to complete the process. transmission. The method of sending the patented data of the present invention to the pixels can be sent row by row, and also includes sending several rows together.

As shown in Figure 10 is the address decoding module 25, for the pixel resolution of 1280*540*RGB OLED display screen, since the R, G, B sub-pixels are arranged in a square shape, the pixel drive data of the display screen Still 1920*1080, a total of 1080 address decoding modules 15, 11-bit address data, 22-bit address bus. Address decoding module 15 is composed of 11 input AND gates, and each line selects the corresponding address connection method to connect to the address bus. The address is encoded and driven onto the address bus. The address decoding module 15 is composed of 6-input AND gates. For 1080 address bits, each of the lower five bits has four input options, and the highest bit has two input options. A total of 22-bit address bus is needed to realize all 1080 Address bit encoding.

The common electrode 27 is a common electrode connected to one end of all the pixel units 26 . The common electrode 27 is a translucent conductive electrode, which can be made of ITO, a translucent metal element, a translucent metal compound or other translucent conductive materials.

FIG. 11 is a structural diagram of the pixel unit 26 . The pixel unit 26 includes a storage unit 28 , a logical operation unit 29 , a driving unit 210 and an OLED display unit 211 . The storage unit 28 receives the address signal and the data signal, has a storage function, and sends the signal to the logic operation unit 29 . The logical operation unit 29 receives the inverse and phase control commands, processes the signals sent by the storage unit 28 , and sends them to the drive unit 210 . The driving unit 210 processes the received data signal of the driving unit 210 and the voltage signal of the DAC module 23 , and sends them to the OLED display unit 211 . The OLED display unit 211 displays a corresponding image according to the received image data signal.

As shown in Figure 12, it is a structural diagram of the storage unit 28, wherein 2121, 2124, 2125, and 2126 are N-type MOS transistors, and 2122 and 2123 are P-type MOS transistors. The specific process for the storage unit 28 to realize the storage function is when the address signal ADDR is high, 2121 and 2124 are turned on, and the data signals data 1 and data 2 enter the storage devices 2122, 2123, 2125, 2126 through 2121 and 2124 respectively. Data 1 and data 2 are always opposite. When the data signal enters the storage device, ADDR becomes low level, and 2121 and 2124 are disconnected. At this time, the inverter composed of 2122 and 2125 and the inverter composed of 2123 and 2126 are composed The storage unit will store data 1 and data 2 in the storage unit without loss.

13 is a structural diagram of the logical operation unit 29, wherein 2133 and 2134 are N-type MOS transistors, 2131 and 2132 are P-type MOS transistors, and input signal 1 and input signal 2 are always opposite signals. Because the control signal is always connected to the high voltage of the circuit, when the input signal 1 is high and the input signal 2 is low, the inverter composed of 2131 and 2133 works normally, the switch composed of 2132 and 2134 is disconnected, and the output signal is low Level; when the input signal 1 is low and the input signal 2 is high, then the inverter composed of 2131 and 2133 does not work, the switch composed of 2132 and 2134 conducts, and the output signal is high.

As shown in Figure 14 is the structural diagram of the driving unit 210, wherein 2141 is a P-type MOS transistor, 2142 is an N-type MOS transistor, and 2141 and 2142 form an inverter driving unit. When the input signal of the driving unit 210 is at a high level, after The drive unit 210 performs reverse processing, and the output signal is at low level, and the analog voltage values of high and low levels are determined by Vhigh and Vlow output by the DAC module 23 . When the Vhigh output by the DAC module 23 is closer to the circuit high voltage, and the Vlow is closer to the circuit high voltage, the brightness displayed by the LCOS display unit 211 is higher; The brightness of the environment is used to set and adjust the brightness of the OLED display unit 211 .

As shown in FIG. 15 , it is a structural diagram of an OLED display unit 211, which includes a silicon substrate 2156, a metal reflective layer 2155 is disposed above the silicon substrate 2156, and a white OLED light-emitting layer 2154 is disposed above the metal reflective layer 2155. A color filter film 2153 is provided above the white OLED light-emitting layer 2154 , a translucent cathode 2152 is provided above the color filter film 2153 , and a transparent glass 2151 is provided above the semitransparent cathode 2152 . The white OLED light-emitting layer 2154 emits white light driven by the electrodes at both ends, and the white light becomes RGB color through the color filter film 2153 , and the OLED display unit 211 displays corresponding images according to the image data signal sent by the driving unit 210 .

As shown in Figure 16, the display time allocation after the effective display bit is added to the LCOS display chip includes the normal pixel data bit display time 410, the effective display bit display time 420, the normal pixel data bit display time 411 and 412, and the effective display bit increase Time 421 and 422 are displayed. The display time of the increased effective display bits and normal pixel data bits can be freely matched. As shown in Figure 16A, the normal pixel data is first displayed as 410, and then the increased effective display data bit 420 is displayed; or as shown in Figure 16B, the increased effective display data bit 420 is first displayed, and then the normal pixel data is displayed as 410 It can also be shown as 411 and 412 by segmenting the normal pixel data as shown in FIG. 8C, and the effective display data bit of the increase is inserted in the middle to display 420; it can also be shown as shown in FIG. 16D by segmenting the normal pixel data as 411 and 412, the increased effective display data bits are segmented into 421 and 422, and then their display order is arbitrarily combined; even as shown in FIG. For any number of segments, divide the display time 421, 422, 423, 424 of increasing effective display data bits into any number of segments, and then display them in combination.

The above two embodiments are only part of the present invention.

Above, the research on a novel way of increasing effective display digits provided by the present invention has been introduced in detail. In this paper, specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only used to help Understand the method of the present invention and its core idea; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation and scope of application. In summary, the content of this specification is not It should be understood as a limitation of the present invention.

Claims (10)

1. A system for increasing effective display digits, characterized in that it includes an address/data receiving and processing module, a row and column drive control logic module, a DAC module, a data latch/drive module, an address decoding module, a pixel unit, and a common electrode and modules that increase the number of effective display digits; The address/data receiving and processing module extracts the received address and data signals, extracts the address signals and transmits them to the row and column drive control logic module, extracts the data signals and transmits them to the data latch/drive module; The row and column drive control logic module receives the address signal transmitted by the address/data receiving and processing module, encodes the address signal, and generates the corresponding row data control signal, common electrode signal and in-phase/inversion selection signal according to the address signal, and converts the row data Send the control signal to the data latch/drive module; send the address signal to the address decoding module; send the common electrode signal to the common electrode; send the in-phase/inverted selection signal to the pixel unit; The data latch/drive module latches and sends data to the pixel unit according to the received row data control signal; The DAC module converts the digital signal into a voltage value and sends it to the pixel unit to realize the display brightness control of the pixel unit; The module that increases the number of effective display bits generates additional data bits based on the received data and sends them to the data latch/driver module. 2. The system for increasing effective display digits as claimed in claim 1 is characterized in that, the module for increasing effective display digits produces extra data bits outside 8 normal pixel data, which is used to compensate the digital display mode display device threshold voltage. 3. The system for increasing the number of effective display digits as claimed in claim 1 or 2, wherein each bit of the normal pixel data and the extra data bits produced by the module for increasing the effective display digits is divided into multiple or Continuously displayed at any display time in the same frame, the timing of the bits is fixed or random, or different timings are used for different frames. 4. The system for increasing the number of effective display digits according to claim 1, wherein the address/data receiving processing module receives the data signal transmitted by the mipi interface or the lvds interface, and the data signal mainly includes the row address and the data of the corresponding row. 5. The system for increasing effective display digits as claimed in claim 1, wherein the row and column drive control logic module receives the address signal transmitted by the address/data receiving processing module, and sends the row data control signal to the data lock storage/driving module; sending control signals to address decoding module, common electrode and pixel unit. 6. The system for increasing the number of effective display bits as claimed in claim 1, characterized in that, all rows of pixels in the pixel unit share one DAC module, or several rows of pixels share one DAC module, or each row of pixels uses a single DAC module module. 7. The system for increasing the number of effective display digits according to claim 1, characterized in that, when the data latch/drive module latches and sends data to the pixel unit, the data sending method adopts row-by-row sending or several rows Combine and send. 8. The system for increasing effective display digits as claimed in claim 1, wherein the address decoding module is composed of several AND gates, and each AND gate generates a row of pixel write signals; the address is driven to The address bus, the address connection mode corresponding to the AND gate selection of each row is connected to the address bus. 9. The system for increasing effective display digits as claimed in claim 1, wherein said pixel unit comprises a storage unit, a logic operation unit, a drive unit and a display unit; the storage unit receives and stores address signals and data signals, And send the signal to the logic operation unit; the logic operation unit receives the frame-by-frame inverted in-phase/inversion control command or the fixed single-phase control command, processes the signal sent by the storage unit and sends it to the drive unit; the display unit according to the drive The image data signal sent by the unit displays the corresponding image. 10. The system for increasing the number of effective display digits as claimed in claim 1, wherein the common electrode is a common terminal electrode connected to one end of all pixel units; the common electrode is a translucent conductive electrode, including ITO, translucent Elemental metals, translucent metal compounds or other translucent conductive materials.