CN110557121B - Multi-channel high-speed sampling data synchronous calibration method based on FPGA - Google Patents

Abstract

The invention discloses a multichannel high-speed sampling data synchronous calibration method based on FPGA (field programmable gate array), belonging to the field of digital signal processing, and the invention relates to a multichannel high-speed sampling data synchronous calibration method based on FPGA, which is a method for synchronously calibrating and implementing sampling data among channels implemented by multichannel high-speed sampling, and effectively solves the problem of data synchronization among the channels after multichannel high-speed ADC (analog to digital converter) sampling.

Description

A multi-channel high-speed sampling data synchronous calibration method based on FPGA

technical field

The invention belongs to the field of digital signal processing, and in particular relates to a multi-channel high-speed sampling data synchronous calibration method realized based on FPGA.

Background technique

With the advancement of chip integrated design technology and processing technology, the application of high-speed sampling above GSPS is becoming more and more common in large-bandwidth signal analysis. Due to the high sampling rate of high-speed sampling systems, front-end analog parts, sampling parts, and back-end signal processing Part of the design and implementation is difficult and demanding, and the amount of real-time data is large, which brings a great burden to the real-time processing and analysis of signals. In practical applications, due to the needs of use, multi-channel high-speed sampling is becoming more and more common. In multi-channel high-speed sampling applications, in addition to the problems caused by the above high speeds, there are also differences in design, processing, and processing. The synchronization problem between multi-channels caused by deviation, etc., and for the use of multi-channel sampling, the synchronization performance between channels is often the key link in the performance of the entire acquisition system, so synchronization performance is a difficult problem in the analysis and design of multi-channel high-speed sampling signals .

At present, due to the limitations of design layout and processing technology in the hardware implementation of multi-channel sampling synchronization, there is no way to ensure complete consistency among multiple channels, and there will always be deviations between channels. In terms of software implementation, due to the high data rate and large amount of data, the data can only be partially stored through large storage devices, and then subsequent analysis and processing can be performed, which cannot meet the requirements of real-time synchronous processing.

There is following shortcoming in prior art:

Due to limitations in design and processing technology, there is currently no way to adjust the differences between multi-channels in terms of hardware implementation. During the sampling operation, there is currently an operation method to adjust the data synchronization deviation by adjusting the phase relationship of the sampling clocks between channels, but to adjust the phase of the sampling clock, only one sampling clock period can be adjusted, and the adjustment range is narrow. Can solve some specific situations. In addition, the phase adjustment of the sampling clock will also bring about the asynchronous problem between the sampling clocks. Similarly, in the subsequent channel signal analysis and processing, the problem of asynchronous processing of clock domains between channels due to clock deviation is revealed. There are also measures to improve the synchronization performance between multiple channels by adjusting the ADC internal channel delay setting, but the adjustable capacity of the ADC internal channel delay setting is also relatively narrow, generally around a maximum sampling clock cycle, which cannot meet the needs of inter-channel The case of large deviation. Moreover, some ADCs do not have a channel delay adjustment function inside, which needs to be used depending on the specific device function of the ADC. There is also a measure of storing the collected multi-channel high-speed sampling data first, and then performing subsequent analysis through the host computer software. This method will not only increase the storage hardware cost, but also cannot meet the requirements of real-time signal processing. The subsequent synchronous processing and re-analysis of data between channels through the host computer software also increases the workload of the software.

Contents of the invention

Aiming at the above-mentioned technical problems existing in the prior art, the present invention proposes a multi-channel high-speed sampling data synchronous calibration method based on FPGA, which is reasonable in design, overcomes the deficiencies of the prior art, and has good effects.

In order to achieve the above object, the present invention adopts the following technical solutions:

A method for synchronous calibration of multi-channel high-speed sampling data realized based on FPGA is carried out according to the following steps:

Step 1: For a given n-channel high-speed acquisition system, set the high-speed ADC sampling frequency of each channel as f _s , the calibration test signal frequency as f _b , set the FIFO buffer depth of each channel as m, and set the channel signal level as the reference value is V; under the condition that the ADC and the sampling clock of each channel are working normally, input the synchronous calibration test signal to each channel, and carry out the data sampling of each channel. After the channel is full of FIFO data once, stop receiving ADC data, and then enter step 2;

Step 2: For the m-point FIFO data of each channel buffered by n channels, according to the channel signal level judgment reference value V, the signal rising edge is judged, and the data at the time t of the rising edge of each channel signal is obtained Sample point position, and calculate and determine the actual sample point length L ₁ , L ₂ ... L _n-1 , L _n of the data sample point buffered in the FIFO at the time t of the rising edge position in each channel, and then enter step 3;

Step 3: Determine the minimum and maximum values among L ₁ , L ₂ ... L _n-1 , L _n through cyclic comparison, the minimum value is recorded as L _mix , the maximum value is recorded as L _max , and then enter step 4;

Step 4: Reduce the length of L ₁ , L ₂ ... L _n-1 , L _n in turn by L _mix to form a new FIFO buffer depth of each channel, which is denoted as L' ₁ , L' ₂ ... L' _n-1 , L'_n; then enter step 5;

Step 5: According to the buffer depth of L' ₁ , L' ₂ ... L' _n-1 , L' _n , design the FIFO buffer length of each channel, and complete the synchronous calibration of the entire multi-channel high-speed sampling data.

Preferably, the FIFO buffer depth m of each channel described in step 1 needs to meet the conditions:

Preferably, in step 2, specifically follow the steps below:

Step 2.1: Let i be the channel index, let i=1; let c be the channel cache data index; go to step 2.2;

Step 2.2: Obtain the m-point sub-depth FIFO data of the i index channel, set c=1, and enter step 2.3;

Step 2.3: Obtain the channel FIFO data s _c indexed by c, and proceed to step 2.4;

Step 2.4: Judging the size of the channel FIFO data s _c and the channel signal level discrimination reference value V;

If: the judgment result is that s _c is less than V, then add 1 to c, and then enter step 2.5;

Or if the judgment result is that s _c is greater than or equal to V, then set L _i =mc, add 1 to i, and then enter step 2.6;

Step 2.5: Determine the size of the channel cache data index c and the FIFO cache depth m;

If: the judgment result is that c is greater than m, then set L _i =0, add 1 to i, and then enter step 2.6;

Or if the judgment result is that c is less than or equal to m, return to step 2.3;

Step 2.6: Determine the size of the channel index i and the number of channels n;

If: the judgment result is that i is less than or equal to n, return to step 2.2;

Or if the judgment result is that i is greater than n, then the entire process of obtaining L ₁ , L ₂ . . . L _n-1 , L _n ends.

Preferably, in step 3, specifically follow the steps below:

_Step 3.1 _: Let j _be the index of _{L 1 , L 2 .}

Step 3.2: Get the index data L _j of j, and then go to step 3.3;

Step 3.3: Determine the size of the index data L _j and the minimum value L _mix and the maximum value L _max respectively;

If: the judgment result is that L _j is less than or equal to L _mix , then set L _mix =L _j ; the judgment result is that L _j is greater than or equal to L _max , then set L _max =L _j ; then add 1 to j, and then enter step 3.4 ;

Or if the judgment result is that L _j is greater than L _mix or L _j is less than L _max , add 1 to j, and then enter step 3.4;

Step 3.4: Determine the size of j and the number of channels n;

If: the judgment result is that j is less than or equal to n, return to step 3.2;

Or if the judgment result is that j is greater than n, then the obtaining process is completed.

Preferably, the values of L' ₁ , L' ₂ ... L' _n-1 , L' _n described in step 4 are the corresponding values of L ₁ , L ₂ ... L _n-1 , L _n The value after subtracting L _mix .

Preferably, after each hard start of the acquisition system, because the FIFO needs to be filled to achieve the purpose of synchronous adjustment of each channel, the first L data output by each channel FIFO in the FPGA is asynchronous and needs to be discarded. Afterwards, the data output by the FIFO cache of each channel reaches consistent synchronization, and then the data output by the FIFO is received and provided to the back-end for processing.

Preferably, L = L _max - L _mix .

Preferably, the channel signal level judgment reference value V should be smaller than the maximum amplitude of the calibration test signal and greater than the minimum amplitude of the calibration test signal.

Preferably, the frequency f _b of the calibration test signal is at least one tenth of the sampling frequency f _s of the high-speed ADC of the channel.

Beneficial technical effects brought by the present invention:

The present invention is a multi-channel high-speed sampling data synchronous calibration method based on FPGA, which is a method for synchronous calibration and implementation of inter-channel sampling data implemented by multi-channel high-speed sampling, which effectively solves the problem of multi-channel high-speed ADC sampling. For the data synchronization problem between channels, the method of the present invention is realized inside the FPGA, and the processing method of sampling buffer calibration and specific synchronization process realization with FIFO has real-time response, fast speed and high efficiency, and does not depend on the hardware platform and does not rely on Changing the sampling clock or ADC core parameters of the existing hardware does not affect the existing hardware, but is a synchronous calibration at the high-speed sampling backend before signal processing and analysis.

Compared with other solutions for subsequent analysis through large-capacity storage, the method of the present invention effectively solves the problem of real-time processing of multi-channel high-speed acquisition signal synchronization, and at the same time effectively reduces the hardware cost of storage, reduces the workload of subsequent software, and has the advantages of The effect of cost reduction and efficiency improvement; compared with other schemes that implement the adjustment of sampling clock or ADC parameters, the method of the present invention is more flexible and accurate, has a wide adjustment range, and will not affect existing hardware conditions, and will not be affected by the implementation of the method of the present invention. Bring knock-on effects to the sampling and subsequent processing links.

Description of drawings

Fig. 1 is the realization process diagram of the method of the present invention.

Fig. 2 is a diagram of the realization process with minimum FPGA resource overhead.

Detailed ways

Below in conjunction with accompanying drawing and specific embodiment the present invention is described in further detail:

The present invention is a multi-channel high-speed sampling data synchronous calibration method based on FPGA, which is specially designed for the inter-channel data synchronization problem of multi-channel high-speed acquisition. Because FPGA is currently used as an ADC data processing device, most of the data collected by high-speed ADC needs to The processing, analysis or storage transmission is directly performed in the FPGA, so realizing synchronous calibration of multi-channel sampling data in the FPGA, so that the sampling data between channels is completely synchronized will bring great benefits to the subsequent signal processing in the FPGA. The method unit of the present invention directly receives high-speed ADC sampling input to the high-speed data of the FPGA interface, and then establishes a channel FIFO buffer in the FPGA, and adjusts and controls the relative time of buffer output interface data through the depth of the channel FIFO buffer, thereby realizing sampling data between multiple channels The time deviation adjustment can achieve the full synchronization function of multi-channel sampling data.

这里校准测试信号一般为给入的沿变化比较明显的脉冲信号或方波信号，在校准阶段每个通道使用FIFO的深度可确保能存储一个校准测试信号的采样数据周期。The realization process of the inventive method is as shown in Figure 1, assumes that n high-speed acquisition channels have been designed according to the synchronous design requirements in terms of hardware design, and the sampling data is input into the FPGA for signal analysis and processing, and the n sampling channels are respectively ch ₁ , ch ₂ . . . ch _n-1 , ch _n indicate that the sampling data width of each sampling channel is the same. In the channel calibration stage, set the channel FIFO buffer depth to m, as shown in Figure 1, s ₁ , s ₂ ... s _m-1 , s _m represent the sample data buffered in the channel FIFO, and the labels represent the time sequence It is buffered in the channel FIFO buffer in turn, and the buffered data follows the first-in-first-out rule. Let the sampling frequency be f _s , the calibration test signal frequency be f _b , and assume that the buffer depth m satisfies

Here, the calibration test signal is generally a pulse signal or a square wave signal with obvious edge changes. In the calibration phase, the depth of the FIFO used by each channel can ensure that a sampling data cycle of the calibration test signal can be stored.

In the calibration stage, when the ADC and sampling clock of each channel are working normally, input a synchronous calibration test signal to each channel for data sampling of each channel. The frequency of the calibration test signal is f _b , and the sampling frequency is f _s . The synchronous calibration test signals of the channels are fully synchronized. When the FIFO data is fully stored in the FPGA, the receiving of ADC data is suspended, and then the test signal data can be analyzed in the FPGA. For a given signal level judgment reference value V, compare and judge the data of each channel with the V value. When the sampled data value is less than V, it can be judged that the signal sampling is in the low-level stage of the calibration test signal. When the signal sampling When the data value is greater than or equal to V, it is determined that the signal sampling is in the high level stage of the calibration test signal, and when the sampling data changes from low level to high level, it is the rising edge change moment of the calibration test signal, and record is time t. Theoretically, in the case of no channel deviation, the time t of each channel should be kept at one sample point of signal sampling, but due to the hardware deviation in processing and manufacturing, the data sample points of each channel at time t cannot be kept consistent. Time, so it caused the asynchronous problem of multi-channel sampling data.

Through the above discrimination processing of the data of each channel, the actual position of the calibration signal rising edge position t of each channel in each FIFO in the FPGA can be determined, so that the data samples at the rising edge position t time of each channel can be determined in the FIFO _The actual sample point lengths buffered in the buffer are denoted as L ₁ , _{L 2} .

After determining the actual sample point lengths L ₁ , L ₂ ... L _n-1 , L _n of the data samples buffered in the FIFO at the time of rising edge position t in each channel, in order to satisfy the synchronization function of the data of each channel, Redesign the buffer depth of FIFO _of each channel as L ₁ , _{L 2} .

In order to reduce FPGA resource consumption, it is possible to determine which channel has the smallest buffer depth among L ₁ , L ₂ ... L _n-1 , and L _n obtained from the actual test, which is recorded as L _mix , and which channel has the largest buffer depth, which is recorded as L _max . The buffer depth of all channels can be correspondingly reduced by L _mix , that is, L ₁ -L _mix , L ₂ -L _mix ... L _n-1 -L _mix , L _n -L _mix , denoted as L' ₁ , L' ₂ ...L' _n-1 , L' _n . Then the buffer depth of the channel FIFO can be redesigned as L' ₁ , L' ₂ ... L' _n-1 , L' _n , and the channel with the least buffer will no longer use the FIFO, as shown in Figure 2, assuming ch After _{the n} channel is judged at time t, its L _n is the smallest in the channel, then the data of the ch _n channel is no longer FIFO buffered, which is also represented in each channel, and the data deviation of the ch _n channel is the last. The FIFO depth of other channels is reduced by L _mix . In FIG. 2 , the data depth of the specific cache is marked by the sample point information marked with the shadow inside the thick frame. In this case, the function of multi-channel high-speed sampling data synchronization can be achieved, and the consumption of FPGA resources can be minimized.

In the specific use process, the method of the present invention only needs to be calibrated once under the condition that the existing hardware and sampling frequency remain unchanged, and the L' ₁ , L' ₂ ... L ' _n-1 , L' _n- channel FIFO depth system achieves multi-channel data synchronization performance, no need to perform calibration operations. After the channel hardware or basic sampling parameters are adjusted, the method of the present invention can be implemented to calibrate again to correct the change deviation.

After each hard start _of the acquisition system, because the FIFO needs to be filled to achieve the purpose of synchronous adjustment of each channel, the first L _max -L _mix data output by the FIFO of each channel in the FPGA is not synchronized and needs to be discarded. -L _mix data and then receive FIFO output data for back-end processing.

Of course, the above descriptions are not intended to limit the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or replacements made by those skilled in the art within the scope of the present invention shall also belong to the present invention. protection scope of the invention.

Claims (9)

1. A multichannel high-speed sampling data synchronous calibration method based on FPGA is characterized in that: the method comprises the following steps:

step 1: for a given n-channel high-speed acquisition system, setting the sampling frequency of the high-speed ADC of each channel as f _s Frequency of calibration test signal f _b Setting FIFO buffer depth of each channel as m and channel signal level discrimination reference value as V; under the condition that the ADC and the sampling clock of each channel work normally, inputting a synchronous calibration test signal to each channel, sampling data of each channel, and if the synchronous calibration test signals input to each channel are completely synchronous, pausing to receive the ADC data after each channel of the FPGA is full of FIFO data, and then entering step 2;

step 2: judging a reference value V according to the signal level of the channel for m-time FIFO data of each channel cached by n channels, judging the rising edge of the signal to obtain the data sampling point position at the t moment of the rising edge of each channel signal, and calculating and determining the actual sampling point length L of the data sampling point at the t moment of the rising edge position in each channel cached in the FIFO ₁ 、L ₂ ...L _n-1 、L _n Then entering step 3;

and 3, step 3: by cyclic comparison, L is determined ₁ 、L ₂ ...L _n-1 、L _n Minimum and maximum of (3), minimum being denoted as L _mix And the maximum value is L _max Then entering step 4;

and 4, step 4: mixing L with ₁ 、L ₂ ...L _n-1 、L _n Is sequentially reduced by L _mix Form a new FIFO buffer depth of each channel, denoted L' ₁ 、L’ ₂ ...L’ _n-1 、L’ _n (ii) a Then entering step 5;

and 5: according to L' ₁ 、L’ ₂ ...L’ _n-1 、L’ _n The cache depth of the multi-channel data acquisition system is designed, the FIFO cache length of each channel is designed, and the synchronous calibration of the whole multi-channel high-speed sampling data is completed.

2. The method for synchronously calibrating the multi-channel high-speed sampling data based on the FPGA of claim 1, which is characterized in that: the FIFO cache depth m of each channel in the step 1 needs to satisfy the condition:

3. the method for synchronously calibrating the multi-channel high-speed sampling data based on the FPGA of claim 1, which is characterized in that: in step 2, the method specifically comprises the following steps:

step 2.1: let i be the channel index, let i =1; setting c as a channel cache data index; entering the step 2.2;

step 2.2: acquiring m-point depth FIFO data of an i index channel, enabling c =1, and entering step 2.3;

step 2.3: obtaining c-indexed channel FIFO data s _c Entering step 2.4;

step 2.4: determining channel FIFO data s _c Judging the size of the reference value V with the channel signal level;

if: the judgment result is s _c If the value is less than V, adding 1 to c, and then entering step 2.5;

or as a result of the judgment s _c If V is greater than or equal to L _i I is added by 1, and then step 2.6 is carried out;

step 2.5: judging the sizes of the channel cache data index c and the FIFO cache depth m;

if: if c is greater than m, let L _i =0, add 1 to i, then go to step 2.6;

or if the judgment result is that c is less than or equal to m, returning to the step 2.3;

step 2.6: judging the sizes of the channel index i and the channel number n;

if: if the judgment result is that i is less than or equal to n, returning to the step 2.2;

or if the judgment result is that i is larger than n, the whole L is obtained ₁ 、L ₂ ...L _n-1 、L _n The process of (2) ends.

4. The method for synchronously calibrating the multi-channel high-speed sampling data based on the FPGA of claim 1, which is characterized in that: in step 3, the method specifically comprises the following steps:

step 3.1: let j be L ₁ 、L ₂ ...L _n-1 、L _n Let j =2, let L _mix ＝L ₁ ，L _max ＝L ₁ Entering step 3.2;

step 3.2: obtain the index data L of j _j Then entering step 3.3;

step 3.3: separately judges the index data L _j And a minimum value L _mix Maximum value L _max The size of (d);

if: the judgment result is L _j Less than or equal to L _mix Then let L _mix ＝L _j (ii) a The judgment result is L _j Greater than or equal to L _max Then let L _max ＝L _j (ii) a Then adding 1 to j, and then entering step 3.4;

or L as a result of the judgment _j Greater than L _mix Or L _j Less than L _max If yes, adding 1 to j, and then entering step 3.4;

step 3.4: judging the sizes of j and the number n of channels;

if: if j is less than or equal to n, returning to the step 3.2;

or if j is larger than n, the solving process is finished.

5. The method for synchronously calibrating the multi-channel high-speed sampling data based on the FPGA of claim 1, which is characterized in that: described in step 4L’ ₁ 、L’ ₂ ...L’ _n-1 、L’ _n Is the corresponding value of L ₁ 、L ₂ ...L _n-1 、L _n Is subtracted by L _mix The latter value.

6. The method for synchronously calibrating the multi-channel high-speed sampling data based on the FPGA of claim 1, which is characterized in that: after the acquisition system is started up hard each time, the FIFO is filled to achieve the purpose of synchronous adjustment of each channel, the first L data output by the FIFO of each channel in the FPGA are asynchronous and need to be discarded, after the L data are delayed, the data output by the FIFO of each channel are cached to achieve consistency and synchronism, and then the data output by the FIFO are received and provided for the back-end processing.

7. The method for synchronously calibrating the multi-channel high-speed sampling data based on the FPGA as recited in claim 6, wherein: l = L _max -L _mix 。

8. The method for synchronously calibrating the multi-channel high-speed sampling data based on the FPGA of claim 1, which is characterized in that: the channel signal level discrimination reference value V should be smaller than the maximum amplitude of the calibration test signal and larger than the minimum amplitude of the calibration test signal.

9. The method for synchronously calibrating the multi-channel high-speed sampling data based on the FPGA of claim 1, which is characterized in that: calibrating the test signal frequency f _b At least less than the channel high-speed ADC sampling frequency f _s One tenth of the total.

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