CN110556297A - preparation method of silicon-based fin field effect transistor with size of below 10 nanometers - Google Patents

Abstract

The invention belongs to the technical field of integrated circuit manufacturing, in particular to a method for preparing a silicon-based fin field-effect transistor with a thickness below 10 nanometers. The invention adopts block copolymer oriented self-assembly materials to prepare silicon-based fin field effect transistors on a substrate, and the critical dimension of the silicon-based fin field effect transistor array is below 10nm; the substrate is silicon-on-insulator (SOI), The block copolymer directed self-assembly material is a block copolymer with two or more different monomers polymerized, and the block copolymer satisfies χN≥10, where N is the total degree of polymerization of the block copolymer, and χ is the total polymerization degree of each block copolymer. Flory-Huggins interaction parameters between segments; the present invention first forms the original pattern by the directed self-assembly technique of the block copolymer, and then transfers to the top layer silicon of the substrate by etching, through this photolithographic technique The obtained devices have a minimum critical dimension of 8 nm and exhibit high transconductance, extremely low off-current and high on-off ratio.

Description

A method for preparing silicon-based fin field effect transistors below 10 nanometers

technical field

The invention belongs to the technical field of semiconductor devices, and in particular relates to a method for preparing a silicon-based fin field effect transistor.

Background technique

In the semiconductor industry, it has always been the goal that people pursue to continuously reduce the size of transistors, reduce device costs and power consumption, and prolong the service life of chips. The capability of graphics, lithography technology is the key to realize the miniaturization strategy of devices. At present, the manufacturing of the world's most advanced 10nm node still relies on 193nm laser immersion lithography and multiple patterning technology. 193nm lithography multiple patterning technology has Reaching the limit of optical resolution. There are currently two lithography methods below 10 nm. One is the extreme ultraviolet lithography (EUV) technology. Although this technology has been tested, there are still many problems before the actual application due to the high price of the EUV exposure machine and the low production capacity. waiting to be solved. The other is Directed Self-Assembly (DSA; or Block Copolymer Lithography), which achieves smaller feature sizes through tailoring, surface modification, and size control of the microphase structure. Nano-patterns with higher density, higher density and better order are gradually becoming the most promising method of advanced photolithography. This technology makes full use of the advantages of self-assembly of block copolymers in thin films, and combines the "bottom-up" self-assembly technology of block copolymer films with "top-down" optical lithography or electron beam photolithography. Combining the technology of preparing oriented graphics such as engraving, because there is no need for light sources and masks, it has the essential advantages of low cost, high resolution, and high yield, and has become a research and development hotspot in semiconductor process technology.

Contents of the invention

The purpose of the present invention is to provide a method for preparing a silicon-based fin field effect transistor with a simple process and low cost.

The method for preparing a silicon-based fin field effect transistor below 10 nanometers proposed by the present invention uses a block copolymer directed self-assembly material to prepare a silicon-based fin field effect transistor on a substrate, and the silicon-based fin field effect transistor array critical The size is less than 10nm, the transconductance is more than 150 µS, the leakage current is less than ~60 pA, and the on-off ratio is more than 3×10 ⁶ ; where:

The substrate is silicon-on-insulator (SOI) with short channel effect and low parasitic capacitance, and the block copolymer-directed self-assembly material is a block copolymer with two or more different monomers polymerized , the block copolymer satisfies χN≥10, N is the total degree of polymerization of the block copolymer, and χ is the Flory-Huggins (Flory-Huggins) interaction parameter between each block;

The concrete steps of preparation are:

(1) Cleaning the substrate to obtain a clean surface substrate; preparing a guide pattern on the substrate;

(2) Spin-coat the block copolymer on the above-mentioned treated substrate; perform annealing treatment, and undergo self-guided self-assembly to form the original pattern; clean to remove unreacted materials;

(3) Use atomic layer deposition technology to deposit metal oxide materials, and carry out continuous cycle infiltration, so that the polar blocks form a hard mask and enhance the etching selectivity;

(4) Etching is then performed to transfer the pattern to the top silicon of the substrate;

(5) Then carry out silicide deposition to form ohmic contact; carry out atomic layer deposition on the dielectric layer (that is, the metal oxide layer deposited in step (3)), in which the top metal deposition forms the gate, and the source/drain is deposited on both sides contact electrodes; finally, an array of silicon-based fin field effect transistors is obtained.

In step (1), the preparation of the guide pattern includes using electron beam lithography technology or 193i lithography technology to perform pattern structure epitaxy or chemical substrate epitaxy.

In step (2), the block copolymer has the structural forms of AB, ABA, and ABC, wherein the mass content of one block component is controlled to be 30%-60%.

In step (2), for triblock copolymers, the Flory-Huggins interaction parameter χ ranges from 0.1 to 0.6; the period L ₀ of block copolymers is 5 nm to 30 nm, and the transferable characteristics Size less than or equal to 10 nanometers.

In step (2), the rotational speed of the spin-coated block copolymer is 2000-6000 rpm, and the time is 10-80 s.

In step (2), the annealing adopts a vacuum heating annealing method or a solvent vapor annealing method; during the vacuum heating annealing, the annealing temperature is controlled to be 100° C. to 250° C., and the annealing time is 1 min to 30 min. Solvent vapor annealing is carried out at room temperature, and the annealing time is 1 min~48 h.

In step (2), the solvent used for cleaning is selected from N-methyl-2-pyrrolidone and chlorobenzene, and blown dry with a nitrogen gun after cleaning.

In step (3), the deposited metal oxide is selected from titanium oxide, aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, copper oxide, tungsten oxide, and molybdenum oxide.

In step (4), the etching adopts dry or wet etching, including oxygen and argon plasma etching or fluorine-based plasma etching.

In step (5), the silicide is selected from nickel silicide.

Based on block copolymer-oriented self-assembly photolithography technology proposed in the present invention, a silicon-based fin field effect transistor array with a characteristic size below 10 nanometers is prepared. The photolithography technology cuts the block copolymer microphase structure, surface Modification and size control to obtain nano-patterns with small feature size, high density, and good order. Compared with traditional optical lithography technology, it has the characteristics of simple process, low cost, and smaller feature size.

In the present invention, the original pattern is first formed by the directed self-assembly technology of the block copolymer, and then the pattern is transferred to the top layer silicon of the substrate by etching. The minimum critical dimension of the device obtained by this photolithography technology can reach 8 nm, and the test device performance, showing high transconductance (150 µS), extremely low off current (~50 pA) and high on/off ratio (3×10 ⁶ ).

Description of drawings

Fig. 1 Flowchart of the prepared silicon-based fin field effect transistor array.

Fig. 2 SEM image of block copolymer self-assembly on SOI substrate.

Figure 3 is a diagram of the prepared 8nm silicon-based fin field effect transistor.

FIG. 4 is a DC test curve of the prepared 8nm silicon-based fin field effect transistor.

Detailed ways

The present invention is further described below by specific examples.

In Example 1, the tri-block copolymer P2VP- b -PS- b -P2VP was selected as the directed self-assembly lithography material, and the Flory-Huggins interaction parameter χ value between the blocks was 0.18. The substrate SOI is cleaned to obtain a clean surface. The three-block copolymer is formed by adjusting the PS component at 45%, and the pattern structure epitaxy is adopted; the three-block copolymer solution is spin-coated, and the block copolymer film is annealed by the room temperature solvent annealing method, the time is 8min, and the temperature is controlled. At 200°C, the period of the block copolymer is 16.4 nm, and the block copolymer is etched by atomic layer deposition technology; continuous cycle infiltration of alumina (Al ₂ O ₃ ) makes the polar block form a hard mask Then, plasma etching was performed to obtain a transferred feature size of 8 nm. The transconductance of the final fin field effect transistor was 180 µS, and the leakage current was very low ~60 pA and a high on-off ratio of 5×10 ⁶ . Figure 1 is a flowchart of the preparation process.

In Example 2, the tri-block copolymer P2VP- b -PS- b -P2VP was selected as the directed self-assembly lithography material, and the Flory-Huggins interaction parameter χ value between the blocks was 0.18. The substrate SOI is cleaned to obtain a clean surface. By adjusting the PS component at 80% to form a three-block copolymer, using a graph structure epitaxy; spin-coating a three-block copolymer solution, spin-coating a three-block copolymer solution, and using a room temperature solvent annealing method for the block copolymer film The annealing time is 15min, the temperature is controlled at 180°C, and the block copolymer is obtained with a period of 18 nm; the block copolymer is etched and enhanced by atomic layer deposition technology, and continuous cycle infiltration of alumina (Al ₂ O ₃ ) to make the polar block form a hard mask to improve the etching selectivity; then perform oxygen plasma etching to obtain a transferred feature size of 8 nm, and the final transconductance of the fin field effect transistor prepared is 160 µS. Figure 2 is the block copolymer self-assembly diagram obtained on the SOI substrate.

In Example 3, the tri-block copolymer P2VP- b -PS- b -P2VP was selected as the directed self-assembly lithography material, and the Flory-Huggins interaction parameter χ value between the blocks was 0.18. The substrate SOI is cleaned to obtain a clean surface. The three-block copolymer was formed by adjusting the PS component at 65%, and the chemical substrate epitaxy was used; the three-block copolymer solution was spin-coated, and the block copolymer film was annealed by the room temperature solvent annealing method, and the time was 1 min. The temperature is controlled at 150°C, and the period of the block copolymer is 20 nm. The block copolymer is etched and enhanced by atomic layer deposition technology, and the polar block is formed by continuous cycle infiltration of alumina (Al ₂ O ₃ ). A hard mask is used to improve the etching selectivity, and then oxygen plasma is used for etching to obtain a device with a minimum critical dimension of 8 nm and a transconductance of 150 µS. Fig. 3 is a diagram of the prepared silicon-based fin field effect transistor, and Fig. 4 is a DC test curve diagram of the prepared 8 nm silicon-based fin field effect transistor.

Example 4, select triblock copolymer P2VP- b -PS- b -P2VP as directed self-assembled lithography material, the Flory-Huggins (Flory-Huggins) interaction parameter χ value between blocks is 0.18. The substrate SOI is cleaned to obtain a clean surface. Adjust the PS component at 30% to form a tri-block copolymer; use graph structure epitaxy; spin-coat the tri-block copolymer solution, and use room temperature solvent annealing method to anneal the block copolymer film for 30 min, temperature control At 100 °C, the period of the block copolymer is 14 nm; the etching of the block copolymer is enhanced by atomic layer deposition technology, and continuous cycle penetration of tantalum oxide (Ta ₂ O ₅ ) makes the polar block form a hard mask The mold is used to improve the etching selectivity; then the oxygen plasma is used for etching, and the minimum critical dimension of the device can reach 6 nm.

Claims (10)

1. A method for preparing a silicon-based fin field-effect transistor below 10 nanometers, characterized in that, a silicon-based fin field-effect transistor is prepared on a substrate by using a block copolymer directed self-assembly material, and the silicon-based fin field effect transistor is The critical dimension of the effect transistor array is less than 10nm, the transconductance is more than 150 µS, the leakage current is less than ~60 pA, and the switching ratio is more than 3×10 ⁶ ; where: The substrate is silicon on an insulating layer with short channel effect and low parasitic capacitance, and the block copolymer directed self-assembly material is a block copolymer with two or more different monomers polymerized, and the block The copolymer satisfies χN≥10, N is the total degree of polymerization of the block copolymer, and χ is the Flory-Huggins interaction parameter between each block; The concrete steps of preparation are: (1) Cleaning the substrate to obtain a clean surface substrate; preparing a guide pattern on the substrate; (2) Spin-coat the block copolymer on the above-mentioned treated substrate; perform annealing treatment, and undergo self-guided self-assembly to form the original pattern; clean to remove unreacted materials; (3) Use atomic layer deposition technology to deposit metal oxide materials, and carry out continuous cycle infiltration, so that the polar blocks form a hard mask and enhance the etching selectivity; (4) Etching is then performed to transfer the pattern to the top silicon of the substrate; (5) Then silicide deposition is carried out to form ohmic contacts; atomic layer deposition is carried out on the dielectric layer, in which the top metal is deposited to form the gate, and the source/drain contact electrodes are deposited on both sides; finally, the silicon-based fin field effect transistor array is obtained . 2. The preparation method according to claim 1, characterized in that the preparation of the guide pattern in step (1) is carried out by electron beam lithography or 193i lithography for pattern structure epitaxy or chemical substrate epitaxy. 3. The preparation method according to claim 1 or 2, characterized in that, the block copolymer described in step (2) has the structural forms of AB, ABA, and ABC, wherein the control of a block component The mass content is 30% to 60%. 4. The preparation method according to claim 3, characterized in that, in step (2), for triblock copolymers, the Flory-Huggins interaction parameter χ ranges from 0.1 to 0.6; block copolymerization The period L ₀ of the object is 5 nm to 30 nm, and the transferable characteristic size is less than or equal to 10 nm. 5. The preparation method according to claim 1, 2 or 4, characterized in that the rotation speed of the spin-coated block copolymer in step (2) is 2000-6000rpm, and the time is 10-80s. 6. The preparation method according to claim 5, characterized in that the annealing in step (2) adopts a vacuum heating annealing method or a solvent vapor annealing method; when the vacuum heating annealing temperature is used, the annealing temperature is controlled to be 100°C-250°C , the annealing time is 1 min to 30 min; when solvent vapor annealing is carried out at room temperature, the annealing time is 1 min to 48 h. 7. The preparation method according to claim 1, 2, 4 or 6, characterized in that, in step (2), the solvent used for cleaning is selected from N-methyl-2-pyrrolidone, chlorobenzene, cleaning Blow dry with a nitrogen gun. 8. The preparation method according to claim 7, characterized in that the metal oxide deposited in step (3) is selected from titanium oxide, aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, copper oxide, tungsten oxide, molybdenum. 9. The preparation method according to claim 8, wherein the etching in step (4) adopts dry or wet etching, including oxygen and argon plasma etching or fluorine-based plasma etching. 10. The preparation method according to claim 9, characterized in that the silicide in step (5) is nickel silicide.