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CN110545047B - Low-power on-chip rectifier bridge circuit - Google Patents

Low-power on-chip rectifier bridge circuit Download PDF

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Publication number
CN110545047B
CN110545047B CN201910987973.1A CN201910987973A CN110545047B CN 110545047 B CN110545047 B CN 110545047B CN 201910987973 A CN201910987973 A CN 201910987973A CN 110545047 B CN110545047 B CN 110545047B
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Prior art keywords
nmos tube
tube
electrode
nmos
source electrode
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CN201910987973.1A
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CN110545047A (en
Inventor
赵寿全
刘桂芝
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Wuxi Linli Technology Co ltd
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Wuxi Linli Technology Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/02—Conversion of AC power input into DC power output without possibility of reversal
    • H02M7/04—Conversion of AC power input into DC power output without possibility of reversal by static converters
    • H02M7/12—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M7/219—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Rectifiers (AREA)

Abstract

The invention relates to the field of rectification circuits and discloses a low-power on-chip rectification bridge circuit which comprises a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a first PMOS tube, a second PMOS tube, a first drive control circuit and a second drive control circuit, wherein the grid electrode and the source electrode of the first PMOS tube are in short circuit, the grid electrode and the source electrode of the second PMOS tube are in short circuit, the source electrode of the first PMOS tube is electrically connected with the source electrode of the second PMOS tube, the drain electrode of the first PMOS tube is electrically connected with the drain electrode of the first NMOS tube, the drain electrode of the second PMOS tube is electrically connected with the drain electrode of the second NMOS tube, the source electrodes of the first NMOS tube and the second NMOS tube are grounded, the first drive control circuit controls the on-off of the first NMOS tube, the drain electrode of the first NMOS tube is electrically connected with a first alternating current input end, and the drain electrode of the second NMOS tube is electrically connected with a second alternating current input end. According to the invention, alternating current outputs a direct current signal through the first PMOS tube or the second PMOS tube respectively, so that the voltage drop is reduced, and the rectifying efficiency is improved.

Description

Low-power on-chip rectifier bridge circuit
Technical Field
The invention relates to the field of rectifier circuits, in particular to a low-power on-chip rectifier bridge circuit.
Background
The traditional rectifier bridge circuit mainly comprises four diodes, alternating current is rectified into direct current output by utilizing the unidirectional conduction characteristic of the diodes, but the diodes have conduction voltage drop of about 0.6V when being conducted, and the rectifier circuit formed by a plurality of diodes has great power loss and can raise the operating temperature.
The rectifier circuit of the switch MOSFET and the active rectifier bridge control chip combination utilizes the lower conduction voltage drop of the switch MOSFET to improve the power loss caused by the inherent voltage drop of the diode. However, in this architecture, there are defects of more separate devices and complex PCB layout, and the high complexity of the active rectifier bridge control chip brings about higher cost pressure.
Disclosure of Invention
In view of the shortcomings of the background technology, the invention provides a low-power on-chip rectifier bridge circuit, and the technical problem to be solved is that the existing diode rectifier bridge circuit has great power loss in operation due to the conduction voltage drop of a diode; the rectifier circuit of the combination of the switching MOSFET and the active rectifier bridge control chip is high in cost.
In order to solve the technical problems, the invention provides the following technical scheme: the low-power on-chip rectifier bridge circuit comprises a first NMOS tube, a second NMOS tube, a first PMOS tube, a second PMOS tube, a first drive control circuit and a second drive control circuit.
The grid electrode and the source electrode of the first PMOS tube are in short circuit, the grid electrode and the source electrode of the second PMOS tube are in short circuit, the source electrode of the first PMOS tube is electrically connected with the source electrode of the second PMOS tube, the drain electrode of the first PMOS tube is electrically connected with the drain electrode of the first NMOS tube, the drain electrode of the second PMOS tube is electrically connected with the drain electrode of the second NMOS tube, the source electrode of the first NMOS tube and the source electrode of the second NMOS tube are both grounded, the first drive control circuit controls the on-off of the first NMOS tube, the second drive control circuit controls the on-off of the second NMOS tube, the drain electrode of the first NMOS tube is electrically connected with the first alternating current input end, and the drain electrode of the second NMOS tube is electrically connected with the second alternating current input end.
Further, the first driving control circuit comprises a resistor R1, a third NMOS tube and a first voltage stabilizing unit, wherein the source electrode and the drain electrode of the third NMOS tube are connected in parallel with the resistor R1, the drain electrode of the third NMOS tube is electrically connected with the second alternating current input end, the source electrode of the third NMOS tube is respectively and electrically connected with the grid electrode of the first NMOS tube and the first voltage stabilizing unit, and the grid electrode and the source electrode of the third NMOS tube are in short circuit.
Preferably, the first voltage stabilizing unit is a voltage stabilizing diode D1, and the source electrode of the third NMOS transistor is grounded through the voltage stabilizing diode D1. The gate source voltage of the first NMOS tube is within the voltage-resistant controllable range of the device.
The third NMOS tube can be replaced by a third PMOS tube, and the grid electrode and the source electrode of the third PMOS tube are in short circuit.
Further, the second driving control circuit comprises a resistor R2, a fourth NMOS tube and a second voltage stabilizing unit, wherein the source electrode and the drain electrode of the fourth NMOS tube are connected in parallel with the resistor R2, the drain electrode of the fourth NMOS tube is electrically connected with the first alternating current input end, the source electrode of the fourth NMOS tube is respectively and electrically connected with the grid electrode of the second NMOS tube and the second voltage stabilizing unit, and the grid electrode and the source electrode of the fourth NMOS tube are in short circuit.
Preferably, the second voltage stabilizing unit is a voltage stabilizing diode D2, and the source of the fourth NMOS transistor is grounded through the voltage stabilizing diode D2. The gate source voltage of the second NMOS tube is within the voltage-resistant controllable range of the device.
The fourth NMOS tube can be replaced by a fourth PMOS tube, and the grid electrode and the source electrode of the fourth PMOS tube are in short circuit.
Furthermore, the small-power on-chip rectifier bridge circuit and the main chip circuit can be integrally arranged on the same wafer substrate, and the small-power on-chip rectifier bridge circuit provides working voltage for the main chip circuit, so that integrated and miniaturized production is realized.
In the first drive circuit and the second drive circuit, the grid electrode and the source electrode of the NMOS tube are in short circuit, the NMOS tubes of the two drive circuits can realize the quick connection and disconnection of the first NMOS tube and the second NMOS tube, so that the ringing phenomenon is effectively inhibited, and the improvement of the rectifying efficiency is realized.
After the grid electrodes and the source electrodes of the first PMOS tube and the second PMOS tube are in short circuit, when forward voltage is input to the drain electrodes, the first PMOS tube and the second PMOS tube are conducted, the forward voltage outputs voltage through a parasitic diode of the PMOS tube, and the voltage drop of the parasitic diode is smaller than the conduction voltage drop of the diode.
Compared with the prior art, the invention has the following beneficial effects: the output voltage drop during rectification can be effectively reduced through the first PMOS tube and the second PMOS tube, the conduction loss is reduced, and the rectification efficiency is improved. Secondly, potential leakage between components can be eliminated by using the first NMOS tube and the second NMOS tube. Finally, the first NMOS tube and the second NOMS tube can be opened and closed rapidly through the third NMOS tube and the fourth NMOS tube, the occurrence of ringing phenomenon is restrained, and the rectifying efficiency is further improved.
Drawings
The invention has the following drawings:
FIG. 1 is a schematic diagram of the structure of the present invention;
FIG. 2 is a schematic diagram of a first driving circuit according to the present invention;
FIG. 3 is a schematic diagram of a second driving circuit according to the present invention;
Fig. 4 is a circuit schematic of the present invention.
Detailed Description
The invention will now be described in further detail with reference to the accompanying drawings. The drawings are simplified schematic representations which merely illustrate the basic structure of the invention and therefore show only the structures which are relevant to the invention.
As shown in fig. 1 to 4, the low-power on-chip rectifier bridge circuit includes a first NMOS transistor M1, a second NMOS transistor M2, a first PMOS transistor M3, a second PMOS transistor M4, a first drive control circuit 100, and a second drive control circuit 102.
The grid electrode and the source electrode of the first PMOS tube M3 are in short circuit, the grid electrode and the source electrode of the second PMOS tube M4 are in short circuit, the source electrode of the first PMOS tube M3 is electrically connected with the source electrode of the second PMOS tube M4, the drain electrode of the first PMOS tube M3 is electrically connected with the drain electrode of the first NMOS tube M1, the drain electrode of the second PMOS tube M4 is electrically connected with the drain electrode of the second NMOS tube M2, the source electrode of the first NMOS tube M1 and the source electrode of the second NMOS tube M2 are grounded, the first drive control circuit 100 controls the on-off of the first NMOS tube M1, the second drive control circuit 102 controls the on-off of the second NMOS tube M2, the drain electrode of the first NMOS tube M1 is electrically connected with the first AC input end AC1, and the drain electrode of the second NMOS tube M2 is electrically connected with the second AC input end AC2.
Further, the first driving control circuit 100 includes a resistor R1, a third NMOS transistor M5, and a first voltage stabilizing unit 104, where a source and a drain of the third NMOS transistor M5 are connected in parallel to the resistor R1, a drain of the third NMOS transistor M5 is electrically connected to the second AC input AC2, a source of the third NMOS transistor M5 is electrically connected to the gate of the first NMOS transistor M1 and the first voltage stabilizing unit 104, and a gate and a source of the third NMOS transistor M5 are shorted.
Preferably, the first voltage stabilizing unit 104 is a voltage stabilizing diode D1, and the source of the third NMOS transistor M5 is grounded through the voltage stabilizing diode D1. The gate-source voltage of the first NMOS tube M1 is within the voltage-resistant controllable range of the device.
The third NMOS transistor M5 may be replaced by a third PMOS transistor, where the gate and the source of the third PMOS transistor are shorted, and after replacement, the source of the third PMOS transistor is electrically connected to the second AC input terminal AC2, and the drain of the third PMOS transistor is electrically connected to the gate of the first NMOS transistor M1 and the zener diode D1, respectively.
Further, the second driving control circuit 102 includes a resistor R2, a fourth NMOS transistor M6, and a second voltage stabilizing unit 105, where a source and a drain of the fourth NMOS transistor M6 are connected in parallel to the resistor R2, a drain of the fourth NMOS transistor M6 is electrically connected to the first AC input AC1, a source of the fourth NMOS transistor M6 is electrically connected to the gate of the second NMOS transistor M2 and the second voltage stabilizing unit 105, and a gate and a source of the fourth NMOS transistor M6 are shorted.
Preferably, the second voltage stabilizing unit 105 is a voltage stabilizing diode D2, and the source of the fourth NMOS transistor M6 is grounded through the voltage stabilizing diode D2. The gate-source voltage of the second NMOS tube M2 is within the voltage-resistant controllable range of the device.
The fourth NMOS transistor M6 may be replaced by a fourth PMOS transistor, where the gate and the source of the fourth PMOS transistor are shorted, and after replacement, the source of the fourth PMOS transistor is electrically connected to the first AC input terminal AC1, and the drain of the fourth PMOS transistor is electrically connected to the gate of the second NMOS transistor M2 and the zener diode D2, respectively.
Further, the small-power on-chip rectifier bridge circuit and the main chip circuit 101 can be integrally mounted on the same wafer substrate, and the small-power on-chip rectifier bridge circuit provides working voltage for the main chip circuit 101, so that integrated and miniaturized production is realized.
In the first driving circuit 100 and the second driving circuit 102, the gate and the source of the NMOS tube are short-circuited, and the first NMOS tube M1 and the second NMOS tube M2 can be rapidly turned on and off through the NMOS tubes of the two driving circuits, so that the ringing phenomenon is effectively inhibited, and the rectifying efficiency is improved.
After the grid electrodes and the source electrodes of the first PMOS tube M3 and the second PMOS tube M4 are in short circuit, when the forward voltage is input to the drain electrode, the first PMOS tube M3 and the second PMOS tube M4 are conducted, the forward voltage outputs voltage through a parasitic diode of the PMOS tube, and the voltage drop of the parasitic diode is smaller than the conduction voltage drop of the diode.
The working principle of the invention is as follows: when the first alternating current input end AC1 inputs a high level and the second alternating current input end AC2 inputs a low level, the first alternating current input end AC1 lifts the grid potential of the second NMOS tube M2 through a resistor R2, and the second NMOS tube M2 is started; the second alternating current input end AC2 pulls down the grid potential of the first NMOS tube M1 through a resistor R1, and the first NMOS tube M1 is closed; at this time, the first AC input AC1 transfers energy to VDC through the parasitic diode of the first PMOS transistor M3.
When the second alternating current input end AC2 inputs a high level and the first alternating current input end AC1 inputs a low level, the second alternating current input end AC2 lifts the grid potential of the first NMOS tube M1 through a resistor R1, and the first NMOS tube M1 is started; the first alternating current input end AC1 pulls down the grid potential of the second NMOS tube M2 through a resistor R2, and the second NMOS tube M2 is closed; at this time, the second AC input AC2 transfers energy to VDC through the parasitic diode of the second PMOS transistor M4.
The first PMOS tube M3 and the second PMOS tube M4 realize lower source-drain voltage which is far lower than the inherent voltage drop (about 0.6V) of the diode, thereby realizing lower power loss and improving the output efficiency of the system. The first NMOS tube M1 and the second NMOS tube M2 are used, and meanwhile, the potential problem of electric leakage between component isolation is eliminated.
The third NMOS tube M5 connected in parallel with R1 and the fourth NMOS tube M6 connected in parallel with R2 are short-circuited by adopting a grid electrode and a source electrode. The third NMOS transistor M5 and the fourth NMOS transistor M6 have two functions: firstly, when the first NMOS tube M1 or the second NMOS tube M2 is started, the parasitic capacitance between the gate drain and the parasitic capacitance between the source drain of the third NMOS tube M5 and the fourth NMOS tube M6 are utilized to quickly lift the grid electrode of the first NMOS tube M1 or the second NMOS tube M2, so that quick conduction is realized; second, when the first NMOS tube M1 or the second NMOS tube M2 is turned off, the parasitic diodes of the third NMOS tube M5 and the fourth NMOS tube M6 are used to rapidly discharge the gate of the first NMOS tube M1 or the second NMOS tube M2, so as to realize rapid disconnection. The third NMOS tube M5 and the fourth NMOS tube M6 realize the quick turn-on and turn-off of the first NMOS tube M1 or the second NMOS tube M2, thereby inhibiting the occurrence of ringing phenomenon and further improving the rectifying efficiency.
The present invention has been made in view of the above-described circumstances, and it is an object of the present invention to provide a portable electronic device capable of performing various changes and modifications without departing from the scope of the technical spirit of the present invention. The technical scope of the present invention is not limited to the description, but must be determined according to the scope of claims.

Claims (7)

1. The utility model provides a miniwatt piece internal rectifier bridge circuit which characterized in that: the device comprises a first NMOS tube, a second NMOS tube, a first PMOS tube, a second PMOS tube, a first drive control circuit and a second drive control circuit;
The grid electrode and the source electrode of the first PMOS tube are in short circuit, the grid electrode and the source electrode of the second PMOS tube are in short circuit, the source electrode of the first PMOS tube is electrically connected with the source electrode of the second PMOS tube, the drain electrode of the first PMOS tube is electrically connected with the drain electrode of the first NMOS tube, the drain electrode of the second PMOS tube is electrically connected with the drain electrode of the second NMOS tube, the source electrode of the first NMOS tube and the source electrode of the second NMOS tube are grounded, the first drive control circuit controls the on-off of the first NMOS tube, the first drive control circuit comprises a resistor R1, a third NMOS tube and a first voltage stabilizing unit, the source electrode and the drain electrode of the third NMOS tube are connected in parallel with the resistor R1, the drain electrode of the third NMOS tube is electrically connected with the second alternating current input end, the source electrode of the third NMOS tube is respectively and electrically connected with the grid electrode of the first NMOS tube and the first voltage stabilizing unit, and the grid electrode of the third NMOS tube is in short circuit; the second drive control circuit controls the on-off of the second NMOS tube, the drain electrode of the first NMOS tube is electrically connected with the first alternating current input end, and the drain electrode of the second NMOS tube is electrically connected with the second alternating current input end.
2. The low-power on-chip rectifier bridge circuit of claim 1, wherein: the first voltage stabilizing unit is a voltage stabilizing diode D1, and the source electrode of the third NMOS tube is grounded through the voltage stabilizing diode D1.
3. The low-power on-chip rectifier bridge circuit of claim 1, wherein: the third NMOS tube can be replaced by a third PMOS tube, and the grid electrode and the source electrode of the third PMOS tube are in short circuit.
4. The low-power on-chip rectifier bridge circuit of claim 1, wherein: the second drive control circuit comprises a resistor R2, a fourth NMOS tube and a second voltage stabilizing unit, wherein the source electrode and the drain electrode of the fourth NMOS tube are connected with the resistor R2 in parallel, the drain electrode of the fourth NMOS tube is electrically connected with the first alternating current input end, the source electrode of the fourth NMOS tube is respectively electrically connected with the grid electrode of the second NMOS tube and the second voltage stabilizing unit, and the grid electrode and the source electrode of the fourth NMOS tube are in short circuit.
5. The low-power on-chip rectifier bridge circuit of claim 4, wherein: the second voltage stabilizing unit is a voltage stabilizing diode D2, and the source electrode of the fourth NMOS tube is grounded through the voltage stabilizing diode D2.
6. The low-power on-chip rectifier bridge circuit of claim 4, wherein: the fourth NMOS tube can be replaced by a fourth PMOS tube, and the grid electrode and the source electrode of the fourth PMOS tube are in short circuit.
7. The low-power on-chip rectifier bridge circuit of claim 1, wherein:
The small-power on-chip rectifier bridge circuit and the main chip circuit can be integrally arranged on the same wafer substrate, and the small-power on-chip rectifier bridge circuit provides working voltage for the main chip circuit.
CN201910987973.1A 2019-10-17 2019-10-17 Low-power on-chip rectifier bridge circuit Active CN110545047B (en)

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CN111371443B (en) 2020-05-28 2020-08-28 上海南麟电子股份有限公司 Active rectifier bridge circuit and on-chip integrated system
CN118826575B (en) * 2024-09-19 2024-11-29 钰泰半导体股份有限公司 A shutdown control signal generating circuit for a motor drive circuit

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CN210444192U (en) * 2019-10-17 2020-05-01 无锡麟力科技有限公司 Small-power on-chip rectifier bridge circuit

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CN104201915A (en) * 2014-09-15 2014-12-10 西安电子科技大学 Wide-input range, efficient and voltage-multiplying AC/DC (alternating current/direct current) rectifying circuit applied to piezoelectric energy gaining
CN210444192U (en) * 2019-10-17 2020-05-01 无锡麟力科技有限公司 Small-power on-chip rectifier bridge circuit

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