CN110544701A - Semiconductor structures and methods of forming them - Google Patents

Abstract

A semiconductor structure and method of forming the same, the semiconductor structure comprising: the substrate comprises a first region, a second region and a third region, wherein the second region and the third region are positioned on two sides of the first region, the first region comprises a first sub-region and a second sub-region which are adjacent, the first sub-region is adjacent to the second region, the second sub-region is adjacent to the third region, the second region is provided with a photoelectric doped region in the substrate, and the third region is provided with a floating diffusion region in the substrate; a gate structure at a surface of the first region, a channel in the first sub-region having a first threshold voltage, a channel in the second sub-region having a second threshold voltage, and the first threshold voltage being greater than the second threshold voltage. The semiconductor structure can improve the performance of the image sensor.

Description

Semiconductor structures and methods of forming them

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof.

Background technique

An image sensor is a semiconductor device that converts an image signal into an electrical signal, and the image sensor is divided into a charge-coupled sensor (CCD) and a CMOS image sensor.

Although the charge-coupled sensor (CCD) has good imaging quality, due to the complex manufacturing process, only a few manufacturers can master it, so the manufacturing cost remains high, especially for large CCDs, the price is very high, and its complex drive mode, high energy consumption As well as the multi-level photolithography process, there are great difficulties in the manufacturing process, which cannot meet the needs of the product.

The low energy consumption of the CMOS image sensor and relatively few photolithography process steps make its manufacturing process relatively simple, and the CMOS image sensor allows the control circuit, signal processing circuit and analog-to-digital converter to be integrated on the chip, making it applicable to various Various sizes of products, and widely applicable to various fields.

However, the performance of image sensors needs to be further improved.

Contents of the invention

The technical problem solved by the present invention is to provide a semiconductor structure and its forming method to improve the performance of the image sensor.

In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate, the substrate includes a first region and a second region and a third region located on both sides of the first region, the first The area includes adjacent first sub-areas and second sub-areas, the first sub-area is adjacent to the second area, the second sub-area is adjacent to the third area, the base of the second area There is a photoelectric doped region inside, the base of the third region has a floating diffusion region; the gate structure located on the surface of the first subregion, the channel in the first subregion has a first threshold voltage, so The channel in the second sub-region has a second threshold voltage, and the first threshold voltage is greater than the second threshold voltage.

Optionally, the gate structure includes: a gate dielectric layer located on the surface of the first region, and in a direction perpendicular to the surface of the substrate, the thickness of the gate dielectric layer in the first subregion is greater than the The thickness of the gate dielectric layer in the second sub-region; the gate layer located on the surface of the gate dielectric layer.

Optionally, the difference between the thickness of the gate dielectric layer in the first subregion and the thickness of the gate dielectric layer in the second subregion is in a range of 5 nanometers to 7 nanometers.

Optionally, the gate structure includes: a gate dielectric layer located on the surface of the first region; a gate layer located on the surface of the gate dielectric layer, and the thickness of the gate layer in the first sub-region is greater than The thickness of the gate layer of the second sub-region.

Optionally, the material of the gate dielectric layer includes silicon oxide or a high dielectric constant material, and the dielectric constant of the high dielectric constant material is greater than 3.9.

Correspondingly, the technical solution of the present invention provides a method for forming any one of the above semiconductor structures, including: providing a substrate, the substrate including a first region and a second region and a third region located on both sides of the first region, The first area includes adjacent first sub-areas and second sub-areas, the first sub-area is adjacent to the second area, and the second sub-area is adjacent to the third area; in the A photoelectric doped region is formed in the second region; a floating diffusion region is formed in the third region; a gate structure is formed on the surface of the first region, and the channel in the first subregion has a first threshold voltage , the channel in the second sub-region has a second threshold voltage, and the first threshold voltage is greater than the second threshold voltage.

Optionally, the method for forming the gate structure includes: forming a first gate dielectric layer on a part of the substrate surface of the first sub-region; forming a first gate dielectric layer on the surface of the first gate dielectric layer and the substrate surface. Two gate dielectric material layers; form a gate material layer on the surface of the second gate dielectric material layer; form a first patterned layer on the surface of the gate material layer in the first region; The layer is a mask to etch the gate material layer and the second gate dielectric material layer until the surface of the substrate is exposed.

Optionally, the method for forming the first gate dielectric layer includes: forming a first gate dielectric material layer on the surface of the substrate; forming a first gate dielectric material layer on a part of the first sub-region surface A second patterned layer: using the second patterned layer as a mask to etch the first gate dielectric material layer until the surface of the substrate is exposed.

Optionally, the method for forming the gate structure includes: forming a gate dielectric material layer on the surface of the substrate; forming a gate material layer on the surface of the gate dielectric material layer; A dielectric material layer and a gate material layer to form a gate dielectric layer and an initial gate layer; a third patterned layer is formed on the surface of the initial gate layer in the first sub-region; the third patterned layer is used as The initial gate layer is etched with a mask to form a gate layer.

Optionally, the method for removing the gate dielectric material layer and the gate material layer outside the first region includes: forming a fourth patterned layer on the surface of the gate material layer in the first region; The patterned layer is a mask, and the gate dielectric material layer and the gate material layer are etched until the surface of the substrate is exposed.

Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

In the semiconductor structure provided by the technical solution of the present invention, on the one hand, since the first sub-region is adjacent to the second region, and there is a photoelectric doped region in the base of the second region, the second sub-region and the The third region is adjacent, and the base of the third region has a floating diffusion region, that is, the first subregion is close to the photoelectric doped region and the second subregion is close to the floating diffusion region, and the second subregion is close to the floating diffusion region. On the one hand, since the gate structure is formed on the substrate surface of the first region, the channel in the first subregion has a first threshold voltage, the channel in the second subregion has a second threshold voltage, and The first threshold voltage is greater than the second threshold voltage, and when a bias voltage is applied to the gate structure, the number of electrons in the channel of the first sub-region is less, that is, the first sub-region and There is a potential barrier difference between the second sub-regions, so it is difficult for electrons in the channel of the second sub-region to flow back into the channel of the first sub-region, which reduces the electrons flowing back in the channel and reduces the image quality. sensor noise and reduce image lag.

Further, since the thickness of the gate dielectric layer in the first subregion is greater than the thickness of the gate dielectric layer in the second subregion, it is realized that the threshold voltage of the channel in the first subregion is greater than that in the second subregion. The threshold voltage of the channel of the sub-region, so that it is difficult for the electrons in the channel of the second sub-region to flow back into the channel of the first sub-region, which reduces the electrons flowing back in the channel.

Further, since the difference between the thickness of the gate dielectric layer in the first subregion and the thickness of the gate dielectric layer in the second subregion is in the range of 5 nanometers to 7 nanometers, the first subregion can be made The difference between the threshold voltage of the channel and the threshold voltage of the channel of the second sub-region is large enough, so that the potential barrier difference between the first sub-region and the second sub-region is large enough to further reduce The probability that electrons in the channel of the second subregion flow back into the channel of the first subregion.

Further, since the thickness of the gate layer of the first sub-region is greater than the thickness of the gate layer of the second sub-region, it is realized that the threshold voltage of the channel of the first sub-region is lower than that of the second sub-region The threshold voltage of the channel, so that the electrons in the channel of the second sub-region are more difficult to flow back into the channel of the first sub-region, which reduces the electrons flowing back in the channel.

Description of drawings

Fig. 1 is a structural schematic diagram of an image sensor;

FIG. 2 is a schematic diagram of a potential barrier state when the image sensor of FIG. 1 is working;

3 to 7 are schematic cross-sectional structure diagrams of each step in the method for forming a semiconductor structure according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of a potential barrier state when the semiconductor structure of FIG. 7 is in operation;

9 to 13 are schematic cross-sectional structural views of various steps in a method for forming a semiconductor structure according to another embodiment of the present invention;

FIG. 14 is a schematic diagram of a potential barrier state when the semiconductor structure of FIG. 13 is in operation.

Detailed ways

As mentioned in the background, the performance of the image sensor needs to be further improved.

FIG. 1 is a schematic structural diagram of an image sensor.

Please refer to FIG. 1 , the image sensor includes: a substrate 100 with a well region (not shown); a gate structure 103 located on the surface of a part of the well region; well regions located on both sides of the gate structure 103 The photoelectric doped region 101 and the floating diffusion region 102 inside.

There are first dopant ions in the well region, and second dopant ions in the photoelectric doped region 101, and the conductivity type of the second dopant ions is opposite to that of the first dopant ions. Therefore, the photoelectric A photodiode is formed between the doped region 101 and the well region, and the photodiode is used to receive light and generate electrons. By applying a bias voltage on the gate structure 103, the electrons generated by the photodiode are transferred to the floating diffusion area 102 .

Please refer to the figure. FIG. 2 is a schematic diagram of the potential barrier state of the image sensor in FIG. The electrons are transported into the floating diffusion region 102 .

In the above image sensor, since there is no potential barrier difference in the channel at the bottom of the gate structure 103 , electrons in the channel are easy to flow back, which causes image delay in the image sensor.

In order to solve the above problems, the technical solution of the present invention provides a semiconductor structure and a method for forming the same. The method includes: providing a substrate, the substrate including a first region and a second region and a third region located on both sides of the first region , the first area includes adjacent first sub-areas and second sub-areas, the first sub-area is adjacent to the second area, the second sub-area is adjacent to the third area, the The substrate of the second region has a photoelectric doped region, and the substrate of the third region has a floating diffusion region; a gate structure is formed on the substrate surface of the first region, and when a bias voltage is applied to the gate structure , there is a potential barrier difference between the channel of the first sub-region and the channel of the second sub-region, and the semiconductor structure formed by the above method can improve the performance of the image sensor.

In order to make the above objects, features and beneficial effects of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

3 to 7 are schematic cross-sectional structure diagrams of various steps in the method for forming a semiconductor structure according to an embodiment of the present invention.

Please refer to FIG. 3 , a substrate 200 is provided, the substrate 200 includes a first region I and a second region II and a third region III located on both sides of the first region I, and the first region I includes adjacent A sub-area A and a second sub-area B, the first sub-area A is adjacent to the second area II, and the second sub-area B is adjacent to the third area III; in the second area II A photoelectric doped region 201 is formed in the third region III; a floating diffusion region 202 is formed in the third region III.

The substrate 200 has a well region (not shown), and the well region has first dopant ions.

There are second doping ions in the photoelectric doping region 201, the conductivity type of the second doping ions is opposite to that of the first doping ions, therefore, a photodiode is formed, so that the photons in the incident light can be converted into electrons.

There are third dopant ions in the floating diffusion region 202, the conductivity type of the third dopant ions is opposite to that of the first dopant ions, and the floating diffusion region 202 is used to store the electronic.

The first sub-area A is adjacent to the second area II, and the second sub-area B is adjacent to the third area III, which is conducive to subsequent contact with the second sub-area B on the surface of the first sub-area A The gate structure formed on the surface transmits the electrons in the photodiode to the floating diffusion region 202 .

In this embodiment, the base 200 is a silicon substrate.

In another embodiment, the base is a semiconductor substrate; the material of the semiconductor substrate includes silicon carbide, silicon germanium, multiple semiconductor materials composed of III-V group elements, silicon-on-insulator (SOI) or germanium-on-insulator . Wherein, the multiple semiconductor materials composed of III-V group elements include InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

In this embodiment, the first dopant ions are P-type ions, the second dopant ions are N-type ions, and the third dopant ions are N-type ions.

The P-type ions include boron ions or BF ²⁺ ions, and the N-type ions include phosphorus ions or arsenic ions.

In this embodiment, the method for forming the photoelectric doped region 201 includes: forming a fifth patterned layer (not shown) on the surface of the substrate 200, the fifth patterned layer exposing part of the second The surface of region II: performing ion implantation using the fifth patterned layer as a mask to form a photoelectric doped region 201 in the second region II.

In this embodiment, the formation process of the photoelectric doped region 201 includes: a first ion implantation process.

In this embodiment, the material of the fifth patterned layer includes photoresist.

In another embodiment, the material of the fifth patterned layer includes silicon nitride.

In this embodiment, after the photoelectric doped region 201 is formed, the fifth patterned layer is removed, and the method for removing the fifth patterned layer is an ashing process.

In this embodiment, the method for forming the floating diffusion region 202 includes: forming a sixth patterned layer (not shown) on the surface of the substrate 200, and the sixth patterned layer exposes part of the third The surface of region III: performing ion implantation using the sixth patterned layer as a mask to form a floating diffusion region 202 in the third region III.

In this embodiment, the formation process of the floating diffusion region 202 includes: a second ion implantation process.

In this embodiment, the material of the sixth patterned layer includes photoresist.

In another embodiment, the material of the sixth patterned layer includes silicon nitride.

In this embodiment, after the floating diffusion region 202 is formed, the sixth patterned layer is removed, and the method for removing the sixth patterned layer is an ashing process.

In this embodiment, the doping concentration of the floating diffusion region 202 is greater than the doping concentration of the photoelectric doped region 201 .

Referring to FIG. 4 , a first gate dielectric layer 203 is formed on a part of the surface of the first sub-region A. Referring to FIG.

In this embodiment, the method for forming the first gate dielectric layer 203 includes: forming a first gate dielectric material layer (not shown) on the surface of the substrate 200; Form a second patterned layer (not shown) on the surface of the first gate dielectric material layer; use the second patterned layer as a mask to etch the first gate dielectric material layer until the substrate 200 is exposed surface.

In this embodiment, the process of etching the first gate dielectric material layer includes a wet etching process or a dry etching process.

In this embodiment, the material of the second patterned layer includes photoresist.

In another embodiment, the material of the second patterned layer includes silicon nitride.

In this embodiment, after the first gate dielectric layer 203 is formed, the second patterned layer is removed, and the method for removing the second patterned layer is an ashing process.

In this embodiment, the material of the first gate dielectric layer 203 is silicon oxide.

In another embodiment, the material of the first gate dielectric layer is a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material includes hafnium oxide, oxide A combination of one or more of zirconium, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide and aluminum oxide.

Referring to FIG. 5 , a second gate dielectric material layer 204 is formed on the surface of the first gate dielectric layer 203 and the surface of the substrate 200 .

The second gate dielectric material layer 204 provides materials for subsequent formation of the second gate dielectric layer.

In this embodiment, the process of forming the second gate dielectric material layer 204 is an atomic layer deposition process.

In another embodiment, the process of forming the second gate dielectric material layer includes a chemical vapor deposition process or a spin coating process.

In this embodiment, the material of the second gate dielectric material layer 204 is silicon oxide.

In another embodiment, the material of the second gate dielectric material layer is a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material includes hafnium oxide, A combination of one or more of zirconia, hafnium silicon oxide, lanthanum oxide, zirconia silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide and aluminum oxide.

Referring to FIG. 6 , a gate material layer 205 is formed on the surface of the second gate dielectric material layer 204 ; and a first patterned layer 206 is formed on the surface of the gate material layer 205 in the first region I.

The gate material layer 205 provides materials for subsequent formation of gate layers.

In this embodiment, the method for forming the gate material layer 205 includes: forming an initial gate material layer (not shown) on the surface of the second gate dielectric material layer 204; A third ion implantation process is performed.

In this embodiment, the process of forming the initial gate material layer is a chemical vapor deposition process.

In another embodiment, the gate material layer is directly formed, and the process for forming the gate material layer includes a chemical vapor deposition process, a physical vapor deposition process, a spin coating process or an electroplating process.

In this embodiment, the material of the gate material layer 205 is doped polysilicon.

In another embodiment, the material of the gate material layer includes one or a combination of copper, tungsten or aluminum.

In this embodiment, the material of the first patterned layer 206 includes photoresist.

In another embodiment, the material of the first patterned layer includes silicon nitride.

Please refer to FIG. 7 on the basis of FIG. 6, using the first patterned layer 206 as a mask to etch the gate material layer 205 and the second gate dielectric material layer 204 until the surface of the substrate 200 is exposed. , to form the gate layer 208 and the second gate dielectric layer 207 .

The first gate dielectric layer 203, the second gate dielectric layer 207 and the gate layer 208 form a gate structure located on the surface of the first region I, wherein the first gate dielectric layer 203 and the second gate dielectric layer 207 together constitute the gate dielectric layer of the gate structure.

In a direction perpendicular to the surface of the substrate 200, the distance between the surface of the second gate dielectric layer 207 of the first subregion A and the surface of the substrate 200 is the distance M, and the second subregion B The distance between the surface of the second gate dielectric layer 207 and the surface of the substrate 200 is a distance N, and the distance M is greater than the distance N, that is, the thickness of the gate dielectric layer of the first sub-region A is greater than that of the first sub-region A. The thickness of the gate dielectric layer of the second sub-region B, so that the channel in the first sub-region A has a first threshold voltage, the channel in the second sub-region B has a second threshold voltage, and the The first threshold voltage is greater than the second threshold voltage.

In this embodiment, the process of etching the gate material layer 205 and the second gate dielectric material layer 204 includes a dry etching process or a wet etching process.

In this embodiment, after the gate layer 208 and the second gate dielectric layer 207 are formed, the first patterned layer 206 is removed, and the method for removing the first patterned layer 206 is an ashing process.

Correspondingly, an embodiment of the present invention also provides a semiconductor structure formed by the above forming method, please refer to FIG. 7, the semiconductor structure includes: a substrate 200, the substrate 200 includes a first region I and a The second area II and the third area III on both sides of I, the first area I includes the adjacent first sub-area A and the second sub-area B, the first sub-area A and the second area II Adjacent, the second sub-region B is adjacent to the third region III, the substrate 200 of the second region II has a photoelectric doped region 201, and the substrate 200 of the third region III has a floating diffusion region 202. The gate structure located on the surface of the first region I, the channel in the first subregion A has a first threshold voltage, the channel in the second subregion B has a second threshold voltage, and The first threshold voltage is greater than the second threshold voltage.

The gate structure includes: a gate dielectric layer located on the surface of the first region I, and the gate dielectric layer includes a first gate dielectric layer 203 and a second gate dielectric layer 207; The gate layer 208 on the surface of the dielectric layer 207 .

In a direction perpendicular to the surface of the substrate 200, the distance between the surface of the second gate dielectric layer 207 of the first subregion A and the surface of the substrate 200 is the distance M, and the second subregion B The distance between the surface of the second gate dielectric layer 207 and the surface of the substrate 200 is a distance N, and the distance M is greater than the distance N, that is, the thickness of the gate dielectric layer of the first sub-region A is greater than that of the first sub-region A. The thickness of the gate dielectric layer of the second sub-region B, so that the channel in the first sub-region A has a first threshold voltage, the channel in the second sub-region B has a second threshold voltage, and the The first threshold voltage is greater than the second threshold voltage.

FIG. 8 is a schematic diagram of a potential barrier state when the semiconductor structure of FIG. 7 is in operation.

Referring to FIG. 8 on the basis of FIG. 7 , the channel at the bottom of the gate structure is opened, so that the electrons in the photoelectric doped region 201 are transported into the floating diffusion region 202 through the channel.

The step of opening the channel at the bottom of the gate structure includes: applying a positive bias voltage on the gate structure.

When a positive bias is applied to the gate structure, since the first threshold voltage is greater than the second threshold voltage, the number of electrons in the channel of the first sub-region A is less, that is, the first There is a potential barrier difference between a sub-region A and the second sub-region B, so that electrons in the channel of the second sub-region B are difficult to flow back into the channel of the first sub-region A, reducing the channel Electrons reflow in the channel, which can reduce noise and reduce image delay.

In this embodiment, the range of the difference between the distance M and the distance N is 5 nanometers to 7 nanometers.

If the range of the difference between the distance M and the distance N is too small, the potential barrier difference between the channel of the first sub-region A and the channel of the second sub-region B may not be large enough, thereby increasing the The probability of the electrons in the channel of the second sub-region B flowing back into the channel of the first sub-region A; the range of the difference between the distance M and the distance N is too large, resulting in the formation of the gate dielectric Material waste during layering. Therefore, when the difference between the distance M and the distance N is in the range of 5 nanometers to 7 nanometers, on the one hand, the threshold voltage of the channel of the first sub-region A can be compared with the threshold voltage of the channel of the second sub-region B. The voltage difference is large enough, so that the potential barrier difference between the channel of the first subregion A and the channel of the second subregion B is large enough to further reduce the electrons in the channel of the second subregion B The possibility of reflowing into the channel of the first sub-region A can save the material of the gate dielectric layer used when forming the gate dielectric layer.

In another embodiment, the range of the difference between the distance M and the distance N is greater than 7 nanometers.

Since the difference range between the distance M and the distance N is greater than 7 nanometers, the probability of electrons in the channel of the second sub-region B flowing back into the channel of the first sub-region A can be further reduced.

It should be noted that the dotted line in FIG. 8 represents the range of the potential barrier size of the photoelectric doped region 201, wherein the maximum potential barrier of the photoelectric doped region 201 is when the number of charges in the photoelectric doped region 201 reaches the required value. The potential barrier when the number of charges of the full well capacity (Full Well Capacity, FWC) of the optoelectronic doped region 201 is described above.

9 to 13 are schematic cross-sectional structure diagrams of various steps in a method for forming a semiconductor structure according to another embodiment of the present invention.

Please refer to FIG. 9 , a substrate 300 is provided, the substrate 300 includes a first region I and a second region II and a third region III located on both sides of the first region I, and the first region I includes adjacent A sub-area A and a second sub-area B, the first sub-area A is adjacent to the second area II, and the second sub-area B is adjacent to the third area III; in the second area II A photoelectric doped region 301 is formed in the third region III; a floating diffusion region 302 is formed in the third region III.

The substrate 300 has a well region (not shown), and the well region has first dopant ions.

There are second doping ions in the photoelectric doping region 301, the conductivity type of the second doping ions is opposite to that of the first doping ions, therefore, a photodiode is formed, so that the photons in the incident light can be converted into electrons.

There are third dopant ions in the floating diffusion region 302, the conductivity type of the third dopant ions is opposite to that of the first dopant ions, and the floating diffusion region 302 is used to store the electronic.

The first sub-area A is adjacent to the second area II, and the second sub-area B is adjacent to the third area III, which is conducive to subsequent contact with the second sub-area B on the surface of the first sub-area A The gate structure formed on the surface transmits the electrons in the photodiode to the floating diffusion region 302 .

In this embodiment, the base 300 is a silicon substrate.

In another embodiment, the base is a semiconductor substrate; the material of the semiconductor substrate includes silicon carbide, silicon germanium, multiple semiconductor materials composed of III-V group elements, silicon-on-insulator (SOI) or germanium-on-insulator . Wherein, the multiple semiconductor materials composed of III-V group elements include InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

In this embodiment, the first dopant ions are P-type ions, the second dopant ions are N-type ions, and the third dopant ions are N-type ions.

The P-type ions include boron ions or BF ²⁺ ions, and the N-type ions include phosphorus ions or arsenic ions.

In this embodiment, the formation process of the photoelectric doped region 301 includes: a first ion implantation process.

In this embodiment, the formation process of the floating diffusion region 302 includes: a second ion implantation process.

In this embodiment, the doping concentration of the floating diffusion region 302 is greater than the doping concentration of the photoelectric doped region 301 .

Referring to FIG. 10 , a gate dielectric material layer 303 is formed on the surface of the substrate 300 , and a gate material layer 305 is formed on the surface of the gate dielectric material layer 303 .

The gate dielectric material layer 303 provides materials for subsequent formation of a gate dielectric material layer.

The gate material layer 305 provides material for subsequent formation of gate layers.

In this embodiment, the process of forming the gate dielectric material layer 303 is an atomic layer deposition process.

In another embodiment, the process of forming the gate dielectric material layer includes a chemical vapor deposition process or a spin coating process.

In this embodiment, the material of the gate dielectric material layer 303 is silicon oxide.

In another embodiment, the material of the gate dielectric material layer is a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material includes hafnium oxide, zirconium oxide , hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide and aluminum oxide.

In this embodiment, the method for forming the gate material layer 305 includes: forming an initial gate material layer (not shown) on the surface of the gate dielectric material layer 303; Three ion implantation process.

In this embodiment, the process of forming the initial gate material layer is a chemical vapor deposition process.

In another embodiment, the gate material layer is directly formed, and the process for forming the gate material layer includes a chemical vapor deposition process, a physical vapor deposition process, a spin coating process or an electroplating process.

In this embodiment, the material of the gate material layer 305 is doped polysilicon.

In another embodiment, the material of the gate material layer includes one or a combination of copper, tungsten or aluminum.

Please refer to FIG. 11 , a fourth patterned layer 306 is formed on the surface of the gate material layer 305 in the first region I; the gate dielectric material layer 303 is etched using the fourth patterned layer 306 as a mask. and the gate material layer 305 until the surface of the substrate 300 is exposed to form a gate dielectric layer 313 and an initial gate layer 315 .

In this embodiment, the process of etching the gate dielectric material layer 303 and the gate material layer 305 includes a dry etching process or a wet etching process.

In this embodiment, the material of the fourth patterned layer 306 includes photoresist.

In another embodiment, the material of the fourth patterned layer includes silicon nitride.

In this embodiment, after the gate dielectric layer 313 and initial gate layer 315 are formed, the fourth patterned layer 306 is removed, and the process of removing the fourth patterned layer 306 is an ashing process.

Referring to FIG. 12 , a third patterned layer 307 is formed on the surface of the initial gate layer 315 in the first sub-region A. Referring to FIG.

In this embodiment, the material of the third patterned layer 307 includes photoresist.

In another embodiment, the material of the third patterned layer includes silicon nitride.

Referring to FIG. 13 on the basis of FIG. 12 , the initial gate layer 315 is etched using the third patterned layer 307 as a mask to form a gate layer 325 .

The gate layer 325 and the gate dielectric layer 313 form a gate structure.

In this embodiment, in a direction perpendicular to the surface of the substrate 300, the gate layer 325 of the first sub-region A has a thickness Q, and the gate layer 325 of the second sub-region B has a thickness P, And the thickness Q is greater than the thickness P, so that the channel in the first sub-region A has a first threshold voltage, the channel in the second sub-region B has a second threshold voltage, and the The first threshold voltage is greater than the second threshold voltage.

In this embodiment, the process of etching the initial gate layer 315 is a dry etching process.

In another embodiment, the process of etching the initial gate layer is a wet etching process.

In this embodiment, after the gate layer 325 is formed, the third patterned layer 307 is removed, and the process of removing the third patterned layer 307 is an ashing process.

Correspondingly, an embodiment of the present invention also provides a semiconductor structure formed by the above forming method, please refer to FIG. 13, the semiconductor structure includes: a substrate 300, the substrate 300 includes a first region I and a The second area II and the third area III on both sides of I, the first area I includes the adjacent first sub-area A and the second sub-area B, the first sub-area A and the second area II Adjacent, the second sub-region B is adjacent to the third region III, the substrate 300 of the second region II has a photoelectric doped region 301, and the substrate 300 of the third region III has a floating diffusion region 302. The gate structure located on the surface of the first region I, the channel in the first subregion A has a first threshold voltage, the channel in the second subregion B has a second threshold voltage, and The first threshold voltage is greater than the second threshold voltage.

The gate structure includes: a gate dielectric layer 313 located on the surface of the first region I; and a gate layer 325 located on the surface of the gate dielectric layer 313 .

In the direction perpendicular to the surface of the substrate 300, the gate layer 325 of the first sub-region A has a thickness Q, the gate layer 325 of the second sub-region B has a thickness P, and the thickness Q is greater than The thickness P is such that the channel in the first sub-region A has a first threshold voltage, the channel in the second sub-region B has a second threshold voltage, and the first threshold voltage is greater than the the second threshold voltage.

In this embodiment, the difference between the thickness Q and the thickness P is adjusted according to the electrical characteristics of the gate layer 325, so as to ensure the difference between the first threshold voltage and the second threshold voltage When the difference between them reaches the preset difference, the material of the gate layer can be saved.

FIG. 14 is a schematic diagram of a potential barrier state when the semiconductor structure of FIG. 13 is in operation.

Referring to FIG. 14 on the basis of FIG. 13 , the channel at the bottom of the gate structure is opened, so that the electrons in the photoelectric doped region 301 are transported into the floating diffusion region 302 through the channel.

The step of opening the channel at the bottom of the gate structure includes: applying a positive bias voltage on the gate structure.

When a positive bias is applied to the gate structure, since the first threshold voltage is greater than the second threshold voltage, the number of electrons in the channel of the first sub-region A is less, that is, the first There is a potential barrier difference between a sub-region A and the second sub-region B, so that electrons in the channel of the second sub-region B are difficult to flow back into the channel of the first sub-region A, reducing the channel Electrons reflow in the channel, which can reduce noise and reduce image delay.

It should be noted that the dotted line in FIG. 14 represents the range of the potential barrier size of the photoelectric doped region 301, wherein the maximum potential barrier of the photoelectric doped region 301 is when the number of charges in the photoelectric doped region 301 reaches the required value. The potential barrier when the charge number of the full well capacity of the photoelectric doped region 301 is mentioned above.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (10)

1. A semiconductor structure, characterized in that, comprising: A substrate, the substrate includes a first region and a second region and a third region located on both sides of the first region, the first region includes adjacent first subregions and second subregions, the first The sub-region is adjacent to the second region, the second sub-region is adjacent to the third region, the substrate of the second region has a photoelectric doped region, and the substrate of the third region has a floating diffusion Area; A gate structure located on the surface of the first region, the channel in the first subregion has a first threshold voltage, the channel in the second subregion has a second threshold voltage, and the first threshold voltage greater than the second threshold voltage. 2. The semiconductor structure according to claim 1, wherein the gate structure comprises: a gate dielectric layer located on the surface of the first region, and in a direction perpendicular to the surface of the substrate, the first The thickness of the gate dielectric layer in a sub-region is greater than the thickness of the gate dielectric layer in the second sub-region; the gate layer located on the surface of the gate dielectric layer. 3. The semiconductor structure according to claim 2, wherein the difference range between the thickness of the gate dielectric layer in the first subregion and the thickness of the gate dielectric layer in the second subregion is 5 nanometers to 7 nm. 4. The semiconductor structure according to claim 1, wherein the gate structure comprises: a gate dielectric layer located on the surface of the first region; a gate layer located on the surface of the gate dielectric layer, the The thickness of the gate layer of the first sub-region is greater than the thickness of the gate layer of the second sub-region. 5. The semiconductor structure according to claim 2 or 4, wherein the material of the gate dielectric layer comprises silicon oxide or a high dielectric constant material, and the dielectric constant of the high dielectric constant material is greater than 3.9. 6. A method for forming a semiconductor structure as claimed in any one of claims 1 to 5, comprising: A substrate is provided, the substrate includes a first region and a second region and a third region located on both sides of the first region, the first region includes adjacent first subregions and second subregions, the first region a sub-area adjoins the second area, the second sub-area adjoins the third area; forming a photoelectrically doped region in the second region; forming a floating diffusion region within the third region; A gate structure is formed on the surface of the first region, the channel in the first subregion has a first threshold voltage, the channel in the second subregion has a second threshold voltage, and the first threshold voltage greater than the second threshold voltage. 7. The method for forming a semiconductor structure according to claim 6, wherein the method for forming the gate structure comprises: forming a first gate dielectric layer on a part of the substrate surface of the first sub-region; A second gate dielectric material layer is formed on the surface of the first gate dielectric layer and the surface of the substrate; a gate material layer is formed on the surface of the second gate dielectric material layer; the gate material layer in the first region forming a first patterned layer on the surface; using the first patterned layer as a mask to etch the gate material layer and the second gate dielectric material layer until the surface of the substrate is exposed. 8. The method for forming a semiconductor structure according to claim 7, wherein the method for forming the first gate dielectric layer comprises: forming a first gate dielectric material layer on the surface of the substrate; Forming a second patterned layer on the surface of a part of the first gate dielectric material layer in a sub-region; using the second patterned layer as a mask to etch the first gate dielectric material layer until the surface of the substrate is exposed . 9. The method for forming a semiconductor structure according to claim 6, wherein the method for forming the gate structure comprises: forming a gate dielectric material layer on the surface of the substrate; forming a gate dielectric material layer on the surface of the gate dielectric material layer Forming a gate material layer; removing the gate dielectric material layer and the gate material layer outside the first region to form a gate dielectric layer and an initial gate layer; forming a gate dielectric layer on the surface of the initial gate layer in the first sub-region a third patterned layer; using the third patterned layer as a mask to etch the initial gate layer to form a gate layer. 10. The method for forming a semiconductor structure according to claim 9, wherein the method for removing the gate dielectric material layer and the gate material layer outside the first region comprises: A fourth patterned layer is formed on the surface of the material layer; using the fourth patterned layer as a mask, the gate dielectric material layer and the gate material layer are etched until the surface of the substrate is exposed.