CN110544688B - Active array, method for manufacturing active array and random access memory - Google Patents
Active array, method for manufacturing active array and random access memory Download PDFInfo
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- CN110544688B CN110544688B CN201810529033.3A CN201810529033A CN110544688B CN 110544688 B CN110544688 B CN 110544688B CN 201810529033 A CN201810529033 A CN 201810529033A CN 110544688 B CN110544688 B CN 110544688B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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Abstract
本发明提供一种有源阵列、有源阵列的制造方法和随机存储器，有源阵列的制造方法包括提供一半导体衬底，在半导体衬底上形成间隔设置的光刻胶，沉积第一阻挡层、牺牲层和第二阻挡层，通过刻蚀形成由有源区单元和隔离间隙构成的间距单元，以构建有源阵列；有源阵列包括半导体基板及有源区单元和隔离间隙构成的间距单元，其中，光刻胶曝光显影的最小尺寸为间距单元的奇数倍；随机存储器包括有源阵列、器件单元和浅槽隔离结构，器件单元形成于有源区单元上，填充隔离间隙以形成浅槽隔离结构。本发明在制造有源阵列中通过改变材料的沉积方式和刻蚀方式，提高光刻极限精度，以获得更小尺寸的间距单元，从而满足随机存储器中特定的小间距单元需求。
The present invention provides an active array, a manufacturing method of the active array and a random access memory. The manufacturing method of the active array includes providing a semiconductor substrate, forming a spaced photoresist on the semiconductor substrate, depositing a first barrier layer, a sacrificial layer and a second barrier layer, and etching to form a spacing unit consisting of an active area unit and an isolation gap to construct an active array; the active array includes a semiconductor substrate and a spacing unit consisting of an active area unit and an isolation gap, wherein the minimum size of the photoresist exposure and development is an odd multiple of the spacing unit; the random access memory includes an active array, a device unit and a shallow trench isolation structure, the device unit is formed on the active area unit, and the isolation gap is filled to form a shallow trench isolation structure. The present invention improves the photolithography limit accuracy by changing the deposition method and etching method of the material in the manufacture of the active array to obtain a smaller spacing unit, thereby meeting the specific small spacing unit requirements in the random access memory.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuits, and more particularly, to an active array, a method for manufacturing the active array, and a random access memory.
Background
In the random access memory, as shown in fig. 1, a currently popular active array (ACTIVE ARRAY), in which a single device Cell 1 (Cell, formed by an active area Cell line) and its adjacent shallow trench isolation structure 2 (STI, formed by an isolation gap in the active array) are spaced apart by a spacing Cell 3 (Pitch).
In the prior art, a Pitch double process is adopted, and an original Pitch is divided into two pitches, so that the size of the Pitch is reduced, but the space cell size and the active region cell width obtained by photoetching in the prior art cannot meet the requirement of certain smaller space cell size due to the limitation of the exposure active region cell width.
Disclosure of Invention
The invention provides an active array, a manufacturing method of the active array and a random access memory, which are used for solving at least one technical problem in the prior art.
In order to achieve the above object, the present invention provides a method for manufacturing an active array, comprising:
Providing a semiconductor substrate, wherein photoresist is arranged on the semiconductor substrate at intervals;
Forming a first barrier layer on the semiconductor substrate and the photoresist;
Forming a sacrificial layer on the first barrier layer, wherein grooves are formed in the sacrificial layer between two adjacent photoresists;
forming a second barrier layer on the sacrificial layer to fill the groove;
Removing the second barrier layer downwards along the upper surface of the second barrier layer to expose the upper surface of the sacrificial layer, wherein the second barrier layer in the groove forms a shielding part;
etching the sacrificial layer and the first barrier layer downwards from the upper surface of the sacrificial layer by taking the shielding part as a mask until the upper surface of the photoresist is exposed, wherein the first barrier layer is provided with a mask part attached to the side surface of the photoresist and a protection part positioned between the sacrificial layer and the semiconductor substrate, and the longitudinal thickness of the mask part is larger than that of the protection part;
Removing the photoresist, etching the sacrificial layer downwards along the exposed part of the sacrificial layer until the protecting part of the first barrier layer is exposed, and continuing etching the exposed protecting part of the first barrier layer until the semiconductor substrate is exposed to form a plurality of barrier structures formed by the mask part of the first barrier layer and the shielding part comprising the second barrier layer on the semiconductor substrate, and
The method comprises the steps of forming a spacing unit for constructing an active array, etching the semiconductor substrate by taking the blocking structure as a mask to form an isolation gap, removing the blocking structure to form an active area unit, and forming a spacing unit by one active area unit and one adjacent isolation gap.
In one embodiment, the minimum dimension of the exposure development between adjacent ones of the photoresists is an odd multiple of the pitch cell dimension.
In one embodiment, the photoresist includes a first side and a second side opposite to the first side, and a distance between the first sides of two adjacent photoresists is a minimum dimension of exposure development, wherein three pitch units are included at positions corresponding to the minimum dimension of exposure development and the semiconductor substrate.
In one embodiment, the size of the pitch unit comprises 30nm.
In one embodiment, 1/2 of the thickness of the sacrificial layer is greater than or equal to the thickness of the first barrier layer, and the sum of the lateral thickness of the sacrificial layer at the first side and the lateral thickness of the first barrier layer at the first side is less than 1/2 of the spacing between adjacent photoresists.
In one embodiment, the dimensions of the photoresist, and the thicknesses of the first barrier layer and the sacrificial layer on the first side and the second side of the photoresist are adjusted to adjust the width of the active area unit and the dimension of the isolation gap.
In one embodiment, the first barrier layer and the second barrier layer each comprise silicon nitride, and the sacrificial layer comprises silicon oxide.
In one embodiment, the plurality of barrier structures including the barrier portion of the second barrier layer further includes the sacrificial layer and the first barrier layer under the barrier portion to form a mask stack layer.
To achieve the above object, the present invention provides an active array comprising:
Semiconductor substrate, and
A plurality of active region units formed on the semiconductor substrate and isolation gaps between adjacent ones of the active region units according to the manufacturing method described in the above embodiments;
The minimum feature size of the exposure development size of the photoresist is an odd multiple of the feature size of the spacing unit.
In one embodiment, the feature size of the pitch cell comprises 30nm
To achieve the above object, the present invention provides a random access memory comprising
An active array as described in the above embodiments;
a plurality of device units formed on the active region unit, and
A shallow trench isolation structure is formed in the semiconductor substrate by filling an isolation material into the isolation gap.
The invention improves the photoetching limit precision by changing the deposition mode and etching mode of materials in manufacturing the active array so as to obtain a spacing unit with smaller size, so that the active array and the random access memory obtain the spacing unit with smaller size, thereby meeting the specific small spacing unit requirement.
The foregoing summary is for the purpose of the specification only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present invention will become apparent by reference to the drawings and the following detailed description.
Drawings
In the drawings, the same reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily drawn to scale. It is appreciated that these drawings depict only some embodiments according to the disclosure and are not therefore to be considered limiting of its scope.
Fig. 1 is a block diagram of an active array in the prior art.
FIG. 2 is a flow chart of active array fabrication in accordance with an embodiment of the present invention.
Fig. 3 is a block diagram of step S10 of manufacturing an active array according to an embodiment of the present invention.
Fig. 4 is a block diagram of step S20 of manufacturing an active array according to an embodiment of the present invention.
Fig. 5 is a block diagram of step S30 of manufacturing an active array according to an embodiment of the present invention.
Fig. 6 is a block diagram of step S40 of manufacturing an active array according to an embodiment of the present invention.
Fig. 7 is a block diagram of step S50 of manufacturing an active array according to an embodiment of the present invention.
Fig. 8 is a block diagram of step S60 of manufacturing an active array according to an embodiment of the present invention.
Fig. 9 is a block diagram of step S70 of manufacturing an active array in an embodiment of the present invention.
Fig. 10 is a block diagram of an active array in a semiconductor device in accordance with an embodiment of the present invention.
Reference numerals in fig. 1:
1, a device unit, 2, a shallow slot isolation structure and 3, a spacing unit.
Reference numerals in fig. 3 to 10:
A semiconductor substrate is provided at 110 a semiconductor substrate,
120 A photoresist of the type described above,
A first side of 121 is provided,
122A second side of the first side,
130 A first barrier layer of the polymer film,
A mask portion 131 of the mask layer,
A protection portion 132 is provided for the protection portion,
140 The sacrificial layer,
141 Of the groove, the groove is provided with a groove,
A second barrier layer 150 is provided over the substrate,
A 151 shielding part is arranged at the bottom of the frame,
160 Pitch units of the pitch,
160A of the isolation gap is provided between the first and second electrodes,
160B active area cells.
Detailed Description
Hereinafter, only certain exemplary embodiments are briefly described. As will be recognized by those of skill in the pertinent art, the described embodiments may be modified in various different ways without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.
Example 1
The method for manufacturing an active array according to this embodiment, as shown in fig. 2, includes:
Step S10 referring to fig. 3, a semiconductor substrate 110 is provided, and photoresist 120 is formed on the semiconductor substrate 110 at intervals.
Step S20, referring to fig. 4, a first barrier layer 130 is formed on the semiconductor substrate 110 and the photoresist 120.
Step S30, referring to fig. 5, a sacrificial layer 140 is formed on the first barrier layer 130, wherein a groove 141 is formed in the sacrificial layer 140 between two adjacent photoresists 120. The materials of the first barrier layer 130 and the sacrificial layer 140 are different so that the individual etches do not affect each other.
Step S40, referring to fig. 6, a second barrier layer 150 is formed on the sacrificial layer 140 to fill the recess 141. The materials of the second barrier layer 150 and the sacrificial layer 140 are different so that the separate etches do not affect each other.
Step S50, referring to fig. 7, removing the second barrier layer 150 downward along the upper surface of the second barrier layer 150 to expose the upper surface of the sacrificial layer 140, wherein the second barrier layer 150 in the recess 141 forms a shielding portion 151.
Step S60, referring to fig. 8, etching the sacrificial layer 140 and the first barrier layer 130 downward from the upper surface of the sacrificial layer 140 using the shielding portion 151 as a mask until the upper surface of the photoresist 120 is exposed. The first barrier layer 130 has a mask portion 131 attached to a side surface of the photoresist 120 and a protection portion 132 located between the sacrificial layer 140 and the semiconductor substrate 110, and a longitudinal thickness of the mask portion 131 is greater than a longitudinal thickness of the protection portion 132. Etching stops etching the upper surface exposing all of the photoresist 120 to facilitate removal of all of the photoresist 120 on the semiconductor substrate 110.
Step S70, referring to fig. 9, removing the photoresist 120, and etching the sacrificial layer downward along the exposed portion of the sacrificial layer 140 until the protection portion 132 of the first barrier layer 130 is exposed, and continuing to etch the exposed protection portion 132 of the first barrier layer 130 until the semiconductor substrate 110 is exposed, so as to form a plurality of barrier structures on the semiconductor substrate 110, the barrier structures being composed of the mask portion 131 of the first barrier layer 130 and the shielding portion 151 including the second barrier layer 150. The barrier structure further includes the sacrificial layer 140 and the first barrier layer 130 under the shielding portion 151 to constitute a mask stack layer. Wherein, the etching process of the sacrificial layer 140 is recessed to both sides due to the large thickness, and the recessed portion does not affect the etched portion of the first barrier layer 130.
Step S80, referring to fig. 10, forming a pitch unit 160 for constructing an active array, includes etching the semiconductor substrate 110 using the blocking structure as a mask to form an isolation gap 160A, removing the blocking structure to form an active region unit 160B, and forming one pitch unit 160 by one of the active region units 160B and one of the isolation gaps 160A adjacent thereto. The spacing between one of the active area cells 160B and one of the isolation gaps 160A adjacent thereto is one cell spacing.
In the case that the size of the photoresist 120 cannot be reduced, the present embodiment forms a plurality of active area units 160B and isolation gaps 160A by changing the deposition and etching modes of the material on the semiconductor substrate 110, so as to improve the lithography limit accuracy, and further form smaller-sized spacing units 160, so that the active array obtains smaller-sized spacing units 160, thereby meeting the specific small-spacing unit 160 requirement.
In one embodiment, the minimum dimension of the exposure development between adjacent photoresists 120 is an odd multiple of the dimension of the spacing unit 160.
In one embodiment, referring to fig. 3 and 10, the photoresist 120 includes a first side 121 and a second side 122 opposite to the first side 121, and a distance between the first sides 121 of two adjacent photoresists 120 is a minimum size of exposure and development (the minimum size of exposure and development is a and has been marked in fig. 3 and 10), wherein three of the pitch units 160 are included at positions corresponding to the minimum size of exposure and development of the semiconductor substrate 110 (the pitch of the pitch units 160 is B and has been marked in fig. 10) so as to reduce the size of each pitch unit 160, thereby obtaining a smaller pitch unit 160 size. The minimum size of exposure development of the photoresist is 80-90 nm, and the size of the obtained interval unit is about 30 nm. In fig. 3 and 10, a and B each represent a distance, a is a separation distance of exposure and development, and B is a cell pitch.
In one embodiment, the size of the pitch unit 160 includes 30nm, and the minimum size of the pitch unit 160 manufactured in this embodiment may reach 30nm, so as to satisfy the 30nm requirement of the pitch unit 160.
In one embodiment, 1/2 of the thickness of the sacrificial layer 140 is greater than or equal to the thickness of the first barrier layer 130, and the sum of the lateral thickness of the sacrificial layer 140 at the first side and the lateral thickness of the first barrier layer 130 at the first side is less than 1/2 of the spacing between adjacent photoresists 120 to form the grooves 141.
In one embodiment, the dimensions of the photoresist 120, and the thicknesses of the first barrier layer 130 and the sacrificial layer 140 on the first side and the second side of the photoresist 120 are adjusted to adjust the width of the active area unit 160B and the dimension of the isolation gap 160A.
Specifically, the size of the photoresist 120 is proportional to the size of the isolation gap 160A, the thickness of the first barrier layer 130 is proportional to the active area cell width of the active area cell 160B, and the thickness of the sacrificial layer 140 is proportional to the size of the isolation gap 160A.
In this embodiment, changing the size of the photoresist 120 and the thickness of the deposited layer both affect the size of the finally formed pitch unit 160, and the specific size needs to be adjusted with more manufacturing requirements, and in this embodiment, only the size of the pitch unit 160 is qualitatively analyzed, but not quantitatively analyzed.
In one embodiment, the first barrier layer 130 comprises silicon nitride, the sacrificial layer 140 comprises silicon oxide, and the second barrier layer 150 comprises silicon nitride.
In one embodiment, the etching comprises dry etching and the removing comprises chemical mechanical polishing, and the position and the range of the etching can be controlled by the dry etching and the chemical mechanical polishing, so that the dimension meets the requirement in the manufacturing process of the active array.
Example two
Based on embodiment 1, referring to fig. 10, an active array of this embodiment includes:
Semiconductor substrate, and
A plurality of active region units 160B formed on the semiconductor substrate according to the manufacturing method described in the first embodiment and isolation gaps 160A between adjacent active region units 160B;
Wherein the minimum feature size of the exposed developed dimension of the photoresist is an odd multiple of the feature size of the pitch unit 160.
In one embodiment, the feature size of the pitch cell 160 comprises 30nm
The active array of the embodiment includes a semiconductor substrate, and a spacing unit 160 composed of an active area unit 160B and an isolation gap 160A, where the feature size of the spacing unit 160 includes 30nm, which improves the minimum precision of photolithography, so that the random access memory device can meet certain specific spacing unit 160 sizes.
Example III
To achieve the above object, the present invention provides a random access memory including an active array as described in the above embodiments, and a plurality of device units and shallow trench isolation structures.
A plurality of device cells are formed on the active region unit 160B.
A shallow trench isolation structure is formed in the semiconductor substrate 110 by filling an isolation material in the isolation gap 160A.
Wherein when the feature size of the spacing cell 160 comprises 30nm, the spacing between the cell and the shallow trench isolation structure also comprises 30nm.
The distance between the cell located on the semiconductor substrate 110 of the random access memory device and the shallow trench isolation structure in the random access memory of the embodiment may be 30nm, and meanwhile, the semiconductor substrate 110 of the random access memory device includes a memory array of the spacing cells 160 composed of the active area cells 160B and the isolation gaps 160A, so that the size requirement of some smaller spacing cells 160 of the random access memory is satisfied, and the performance of the random access memory is improved.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that various modifications and substitutions are possible within the scope of the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed, mechanically connected, electrically connected, or in communication, directly connected, or indirectly connected via an intervening medium, or in communication between two elements or in an interaction relationship between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present invention, unless expressly stated or limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, as well as the first and second features not being in direct contact but being in contact with each other through additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is less level than the second feature.
The above disclosure provides many different embodiments, or examples, for implementing different structures of the invention. The foregoing description of specific example components and arrangements has been presented to simplify the present disclosure. They are, of course, merely examples and are not intended to limit the invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not themselves indicate the relationship between the various embodiments and/or arrangements discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the application of other processes and/or the use of other materials.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201633407A (en) * | 2015-03-09 | 2016-09-16 | 聯華電子股份有限公司 | Manufacturing method of patterned structure of semiconductor device |
| CN208142177U (en) * | 2018-05-29 | 2018-11-23 | 长鑫存储技术有限公司 | Active array and random access memory |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100714305B1 (en) * | 2005-12-26 | 2007-05-02 | 삼성전자주식회사 | Formation method of self-aligned double pattern |
| JP4271243B2 (en) * | 2006-04-11 | 2009-06-03 | 株式会社東芝 | Method for forming integrated circuit pattern |
| US7807575B2 (en) * | 2006-11-29 | 2010-10-05 | Micron Technology, Inc. | Methods to reduce the critical dimension of semiconductor devices |
| TWI452419B (en) * | 2008-01-28 | 2014-09-11 | Az Electronic Mat Ip Japan Kk | Fine pattern mask, process for producing the same, and process for forming fine pattern by using the same |
| CN101640170A (en) * | 2008-07-29 | 2010-02-03 | 中芯国际集成电路制造(上海)有限公司 | Photoetching method capable of reducing width of exposure pattern |
| TWI517247B (en) * | 2012-04-06 | 2016-01-11 | 力晶科技股份有限公司 | Semiconductor circuit structure and its process |
| CN103794476B (en) * | 2012-10-30 | 2017-09-22 | 中芯国际集成电路制造(上海)有限公司 | The forming method of the triple figures of autoregistration |
| US9128384B2 (en) * | 2012-11-09 | 2015-09-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a pattern |
| CN103871956A (en) * | 2012-12-10 | 2014-06-18 | 中微半导体设备(上海)有限公司 | Silicon deep via etching method |
| KR102323251B1 (en) * | 2015-01-21 | 2021-11-09 | 삼성전자주식회사 | Semiconductor device and method for manufacturing semiconductor device |
| CN107968046B (en) * | 2016-10-20 | 2020-09-04 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN107731665B (en) * | 2017-11-13 | 2023-07-25 | 长鑫存储技术有限公司 | Integrated circuit fabrication for pitch multiplication |
-
2018
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201633407A (en) * | 2015-03-09 | 2016-09-16 | 聯華電子股份有限公司 | Manufacturing method of patterned structure of semiconductor device |
| CN208142177U (en) * | 2018-05-29 | 2018-11-23 | 长鑫存储技术有限公司 | Active array and random access memory |
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