CN110544667A - A deeply depleted image sensor pixel unit structure and fabrication method - Google Patents

Abstract

The invention discloses a deeply depleted image sensor pixel unit structure, comprising: a dielectric insulating layer embedded in a P ^- silicon substrate, a dielectric insulating layer disposed in the P ^- silicon substrate and located above the dielectric insulating layer P well, a photodiode located in the P ^- silicon substrate and located on one side of the P well, a P ⁺⁺ implanted substrate layer provided on the backside of the P ^- silicon substrate under the dielectric insulating layer ; wherein, the P well and the P ⁺⁺ implanted substrate layer are completely physically isolated by the dielectric insulating layer, so as to block the leakage path and avoid the generation of leakage, thereby improving the performance of the image sensor.

Description

A deeply depleted image sensor pixel unit structure and fabrication method

technical field

The present invention relates to the technical field of solid-state image sensors, and more particularly, to a pixel unit structure and fabrication method of a deeply depleted image sensor.

Background technique

An image sensor refers to a device that converts an optical signal into an electrical signal. Generally, large-scale commercial image sensor chips include charge-coupled device (CCD) and complementary metal-oxide semiconductor (CMOS) image sensor chips.

The absorption coefficient of silicon material to incident light decreases with the increase of wavelength. Conventional CMOS image sensor pixel units usually use filter layers for three primary colors of red, green, and blue. The wavelength of blue light is 450 nanometers, the wavelength of green light is 550 nanometers, and the wavelength of red light is 650 nanometers. Therefore, the absorption position of red light is the deepest, and the blue light is the lightest. The blue light is absorbed at the position closest to the silicon surface, and its absorption coefficient is the highest. The red light enters the silicon substrate the deepest, about 2.3 μm into the silicon substrate, and its absorption coefficient is the lowest. Absorption of infrared light requires an absorption thickness greater than 2.3 μm. At the same time, in the current application of security monitoring, machine vision and intelligent transportation systems, the wavelength of infrared supplementary light at night is concentrated in 850nm to 940nm, while the conventional back-illuminated CMOS image sensor pixel unit is not sensitive to this wavelength of light. Therefore, it is necessary to design a new back-illuminated pixel unit structure and formation method to improve the sensitivity of the near-infrared band and improve the night vision effect of the product.

Image sensor pixel cells using clamped photodiode (PPD) structures have been widely used in high-performance imaging due to their low readout noise, high conversion gain, and low dark current. For applications that require high quantum efficiency in the near-infrared and soft X-ray bands, the thickness of the silicon layer of the active sensor is usually tens or even hundreds of microns. is completely depleted, thereby eliminating the electric field-free regions inside conventional image sensors, so the photogenerated charges generated in the silicon substrate can be collected in time. The magnitude of the reverse bias depends on the resistivity and thickness of the semiconductor substrate and can far exceed any other voltage in the system, resulting in deeply depleted pixel structures that have been used in hybrid CMOS image sensors or CCD.

However, the above-mentioned structure has a problem that leakage current is easily formed. For an active pixel sensor, as shown in FIG. 1, in the P-well 22 next to the clamped photodiode 26, a control transistor for the pixel unit needs to be formed. The final P well lead is connected to the 0v substrate potential 21, and the substrate negative bias 20 is applied to the P ⁺⁺ implanted substrate 23 to increase the depletion depth under the clamped photodiode 26. This structure will cause a large current between the 0v substrate potential 21 of the P well 22 and the negative bias 20 of the P ⁺⁺ injection substrate 23, that is, from the P well 22 on the front side of the silicon wafer to the P ⁺ on the back side of the silicon wafer. ⁺ Contact. In order to eliminate this parasitic current, the conventional structure adds an N-type lightly doped implant 25, also called a DDE (DeepDepletion Extesion) structure, in the high-resistance P ^- substrate 24 under the P-well 22 of the pixel unit, to connect the P-well 22 and The leakage path between the P ⁺⁺ implanted substrates 23 forms a pinch off. However, the disadvantage of this DDE is that its potential is affected by the potential of the photodiode, and the process window for injecting energy and dose is very small, so it is easy to form a leakage path during the working process of the pixel, resulting in the deterioration of the image sensor performance.

Therefore, there is a need to devise a method to completely isolate the leakage path between the P-well extraction and the P ⁺⁺ implanted substrate.

SUMMARY OF THE INVENTION

The purpose of the present invention is to overcome the above-mentioned defects in the prior art, and to provide a deeply depleted image sensor pixel unit structure and fabrication method.

For achieving the above object, technical scheme of the present invention is as follows:

A deeply depleted image sensor pixel unit structure, comprising: a dielectric insulating layer embedded in a P ^- silicon substrate, a P well disposed in the P ^- silicon substrate and located above the dielectric insulating layer, A photodiode located in the P ^- silicon substrate and located on one side of the P well, and the P ⁺⁺ implanted on the backside of the P ^- silicon substrate under the dielectric insulating layer is implanted into the substrate layer; wherein, through The dielectric insulating layer completely physically isolates the P well and the P ⁺⁺ implanted substrate layer to block leakage paths.

Further, the dielectric insulating layer is a silicon dioxide layer.

Further, the dielectric insulating layer is a buried oxygen layer formed after oxygen ion implantation and high temperature annealing.

Further, the dielectric insulating layer is provided with a gap corresponding to the position of the photodiode, and the photodiode closes the gap.

Further, the lower end of the photodiode enters the P ^- silicon substrate under the dielectric insulating layer through the gap, and the photodiode closes the gap through its side.

Further, the photodiode is an N-type clamped photodiode.

Further, it also includes: a transfer tube, an N-type floating drain and a shallow trench isolation formed on the P ^- silicon substrate.

A method for fabricating a deeply depleted image sensor pixel unit structure, comprising the following steps:

providing a P ^- silicon substrate, and forming an implantation mask layer on the P ^- silicon substrate;

Carry out selective oxygen ion implantation on the P ^- silicon substrate through the implantation mask layer, and form an oxygen ion implantation layer with voids in the P ^- silicon substrate;

removing the implantation mask layer, and through high temperature annealing, the oxygen ions in the implantation layer react with silicon atoms in the p ^- silicon substrate to generate a silicon dioxide buried oxygen layer with voids;

forming a P-well and a shallow trench isolation in the P ^- silicon substrate, and having the P-well and shallow trench isolation located above the buried oxide layer outside the void;

implanting a photodiode such that the photodiode is located in the p ^- silicon substrate above the void location, and the photodiode closes the void;

Using a conventional CMOS process on the front side of the P ^- silicon substrate above the buried oxide layer, a transfer tube and an N-type floating drain are formed;

thinning the back surface of the P ^- silicon substrate under the buried oxide layer;

P ⁺⁺ implantation and annealing are performed on the backside of the thinned P ^- silicon substrate to form a P ⁺⁺ implanted substrate layer.

Further, the photodiode is an N-type clamped photodiode.

Further, by implanting the silicon substrate, it becomes the P ^- silicon substrate.

It can be seen from the above technical solutions that the present invention performs ion implantation and annealing in the local area of the P ^- silicon substrate, and forms a buried oxide layer under the P-well, so that the P-well and the P on the back of the P ^- silicon substrate are treated. ⁺⁺ is implanted into the substrate layer for physical isolation; at the same time, when P ⁺⁺ is implanted into the substrate layer and negatively biased, a reverse-biased PN junction is formed between the P ^- silicon substrate and the N-type clamped photodiode , so that there is no direct path between the P well connected to the 0V ground potential and the negatively biased P ⁺⁺ implanted substrate layer to avoid the generation of leakage.

Description of drawings

FIG. 1 is a schematic structural diagram of a pixel unit of a conventional deep depletion image sensor.

FIG. 2 is a schematic structural diagram of a pixel unit of a deeply depleted image sensor according to a preferred embodiment of the present invention.

3-10 are schematic diagrams of process steps of a method for fabricating a deeply depleted image sensor pixel unit structure according to a preferred embodiment of the present invention.

Detailed ways

The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

It should be noted that, in the following specific embodiments, when describing the embodiments of the present invention in detail, in order to clearly represent the structure of the present invention and facilitate the description, the structures in the accompanying drawings are not drawn according to the general scale, and the Partial enlargement, deformation and simplification of processing are shown, therefore, it should be avoided to interpret this as a limitation of the present invention.

In the following specific embodiments of the present invention, please refer to FIG. 2 , which is a schematic structural diagram of a pixel unit of a deeply depleted image sensor according to a preferred embodiment of the present invention. As shown in FIG. 2 , a deeply depleted image sensor pixel unit structure of the present invention is arranged on a high-resistance P ^- silicon substrate 1 . Specifically, it may include: a dielectric insulating layer 2 embedded in a high-resistance P ^- silicon substrate 1; a P-well 3 disposed in the high ^- resistance P ^- silicon substrate 1 and located above the dielectric insulating layer 2; The photodiode 4 in the silicon substrate 1 and located next to the P well 3; the P ⁺⁺ implanted substrate layer 8 on the backside of the high-resistance P ^- silicon substrate 1 disposed under the dielectric insulating layer 2 ^; The transfer tube (gate) 5 and the N-type floating drain 6 on the front surface of the silicon substrate 1, as well as the pixel unit structure of the image sensor such as the shallow trench isolation 7.

Wherein, the photodiode 4 can be a clamped photodiode 4 . The dielectric insulating layer 2 can be a silicon dioxide layer. In addition, the dielectric insulating layer 2 may be a silicon dioxide buried oxide layer 2 formed by performing oxygen ion implantation on the high-resistance P ^- silicon substrate 1 and annealing at a high temperature. The present invention is not limited to this.

The dielectric insulating layer 2 is provided with a reserved space (opening/gap) corresponding to the position of the clamped photodiode 4, and the clamped photodiode 4 can completely seal the space between the dielectric insulating layers 2 through its side or lower end.

The lower end of the clamped photodiode 4 can also pass through the gap and further enter the high-resistance P ^- silicon substrate 1 under the dielectric insulating layer 2 . At this time, the clamped photodiode 4 can completely close the gap by its side.

The clamped photodiode 4 may be an N-type clamped photodiode 4 .

By arranging the buried oxide layer 2 in the high-resistance P ^- silicon substrate 1, the P well 3 and the P ⁺⁺ implanted substrate layer 8 can be completely physically isolated, so that the P well 3 and the P ⁺⁺ implanted substrate can be blocked. A leakage path is formed between the bottom layers 8 .

As shown in FIG. 2 , below the P well 3 is a buried oxide layer 2 using a silicon dioxide insulating medium, and on the side of the P well 3 is an N-type clamping photodiode 4 . The buried oxide layer 2 achieves physical isolation between the P well 3 and the P ⁺⁺ implanted substrate layer 8 . At the same time, when P ⁺⁺ is injected into the substrate layer 8 and a negative bias is applied, a reverse-biased PN junction is formed between the high-resistance P ^- silicon substrate 1 and the N-type clamp photodiode 4, that is, connected to "0v" There is no direct path between the ground potential P well 3 and the negatively biased P ⁺⁺ implanted substrate layer 8 to form leakage current, thus completely blocking the leakage current path.

A method for fabricating a pixel unit structure of a deeply depleted image sensor of the present invention will be described in detail below through specific embodiments and accompanying drawings.

Please refer to FIGS. 3-10 . FIGS. 3-10 are schematic diagrams of process steps of a method for fabricating a deeply depleted image sensor pixel unit structure according to a preferred embodiment of the present invention. A method for fabricating a deeply depleted image sensor pixel unit structure of the present invention can be used to fabricate the above-mentioned deeply depleted image sensor pixel unit structure shown in, for example, FIG. 2 , and may specifically include the following steps:

First, as shown in FIG. 3 , a high-resistance P ^- silicon substrate 1 is provided, and an implantation mask layer 9 is formed on the high-resistance P ^- silicon substrate 1 .

A silicon substrate can be made a high-resistance P ^- silicon substrate 1 by implanting it.

The implantation mask layer 9 can be formed using a photoresist or a dielectric hard mask. A certain distance is preset between the patterns of the implantation mask layer 9 as implantation windows.

Then, the high-resistance P ^- silicon substrate 1 is selectively implanted with oxygen ions through the implantation mask layer 9 .

Next, as shown in FIG. 4 , the implantation mask layer 9 after the implantation is completed is removed, and it can be seen that there is a local oxygen ion implantation layer formed by the implantation mask layer 9 at a predetermined position in the high-resistance P ^- silicon substrate 1 , that is, the oxygen ion implantation layer 2 ′ having the voids 10 .

Next, as shown in FIG. 5 , through high-temperature annealing, oxygen ions in the implanted layer 2 ′ react with silicon atoms in the high-resistance P ^- silicon substrate 1 to form silicon dioxide, thereby forming a silicon dioxide buried layer with voids 10 Oxygen layer 2.

Again, as shown in FIG. 6 , through processes such as photolithography, dry etching and ion implantation, a P well 3 and a shallow trench isolation are formed in the high resistance P ^- silicon substrate 1 above the buried oxide layer 2 outside the void 10 7.

Next, as shown in FIG. 7 , the implantation of the N-type clamped photodiode 4 is performed, so that the clamped photodiode 4 is located in the high-resistance P ^- silicon substrate 1 above the position of the gap 10 . Wherein, the injection depth of the clamped photodiode 4 can be made equal to or greater than the position of the buried oxide layer 2, and the injection width of the clamped photodiode 4 can be made larger than or equal to the opening width of the gap 10 between the patterns of the buried oxide layer 2, The gaps 10 between the buried oxide layers 2 are closed.

Again, as shown in FIG. 8 , a conventional CMOS process can be used to form pixel unit structures such as a transfer transistor (gate) 5 and an N-type floating drain 6 on the front surface of the high-resistance P ^- silicon substrate 1 above the buried oxide layer 2 .

Next, as shown in FIG. 9 , the backside of the high-resistance P ^- silicon substrate 1 under the buried oxide layer 2 is thinned. The thickness of the thinned high-resistance P ^- silicon substrate 1 is between several micrometers and several hundreds of micrometers, and its thickness depends on the magnitude of the subsequent negative bias voltage and the performance requirements of the image sensor.

Finally, as shown in FIG. 10 , P ⁺⁺ implantation and annealing are performed on the backside of the thinned high-resistance P ^- silicon substrate 1 to form a P ⁺⁺ implanted substrate layer 8 .

To sum up, in the present invention, by performing ion implantation and annealing in the local area of the high-resistance P ^- silicon substrate, and forming a buried oxide layer under the P-well, the P ⁺ on the backside of the P-well and the high-resistance P ^- silicon substrate is treated ⁺ implanted into the substrate layer for physical isolation; at the same time, when the P ⁺⁺ implanted into the substrate layer was negatively biased, a reverse-biased PN was formed between the high-resistance P ^- silicon substrate and the N-type clamped photodiode junction, so that the lack of a direct path between the P well connected to the 0v ground potential and the negatively biased P ⁺⁺ implanted substrate layer avoids the generation of leakage, thus improving the performance of the image sensor.

The above are only the preferred embodiments of the present invention, and the embodiments are not intended to limit the protection scope of the present invention. Therefore, any equivalent structural changes made by using the contents of the description and drawings of the present invention shall be included in the protection of the present invention. within the range.

Claims (10)

1. A deeply depleted image sensor pixel unit structure, comprising: a dielectric insulating layer embedded in a P ^- silicon substrate, disposed in the P ^- silicon substrate and located in the dielectric insulating layer P-well above, a photodiode located in the P ^- silicon substrate and on one side of the P-well, a P ⁺⁺ implant on the backside of the P ^- silicon substrate under the dielectric insulating layer A substrate layer; wherein, the P well and the P ⁺⁺ implanted substrate layer are completely physically isolated by the dielectric insulating layer, so as to block the leakage path. 2 . The deeply depleted image sensor pixel unit structure according to claim 1 , wherein the dielectric insulating layer is a silicon dioxide layer. 3 . 3 . The deeply depleted image sensor pixel unit structure according to claim 1 , wherein the dielectric insulating layer is a buried oxide layer formed by oxygen ion implantation and high temperature annealing. 4 . 4 . The deeply depleted image sensor pixel unit structure according to claim 1 , wherein the dielectric insulating layer is provided with a gap corresponding to the position of the photodiode, and the photodiode closes the gap. 5 . 5 . The deeply depleted image sensor pixel unit structure according to claim 4 , wherein the lower end of the photodiode passes through the gap and enters the P ^- silicon substrate under the dielectric insulating layer. 6 . , the photodiode closes the gap by its side. 6 . The deeply depleted image sensor pixel unit structure of claim 1 , wherein the photodiode is an N-type clamped photodiode. 7 . 7 . The deeply depleted image sensor pixel unit structure according to claim 1 , further comprising: a transfer tube, an N-type floating drain and a shallow trench isolation formed on the P ^- silicon substrate. 8 . 8. A method for fabricating a deeply depleted image sensor pixel unit structure, comprising the following steps: providing a P ^- silicon substrate, and forming an implantation mask layer on the P ^- silicon substrate; Carry out selective oxygen ion implantation on the P ^- silicon substrate through the implantation mask layer, and form an oxygen ion implantation layer with voids in the P ^- silicon substrate; removing the implantation mask layer, and through high temperature annealing, the oxygen ions in the implantation layer react with silicon atoms in the p ^- silicon substrate to generate a silicon dioxide buried oxygen layer with voids; forming a P-well and a shallow trench isolation in the P ^- silicon substrate, and having the P-well and shallow trench isolation located above the buried oxide layer outside the void; implanting a photodiode such that the photodiode is located in the p ^- silicon substrate above the void location, and the photodiode closes the void; Using a conventional CMOS process on the front side of the P ^- silicon substrate above the buried oxide layer, a transfer tube and an N-type floating drain are formed; thinning the back surface of the P ^- silicon substrate under the buried oxide layer; P ⁺⁺ implantation and annealing are performed on the backside of the thinned P ^- silicon substrate to form a P ⁺⁺ implanted substrate layer. 9 . The method for fabricating a deeply depleted image sensor pixel unit structure according to claim 8 , wherein the photodiode is an N-type clamped photodiode. 10 . 10 . The method for fabricating a deeply depleted image sensor pixel unit structure according to claim 8 , wherein the P ^- silicon substrate is formed by implanting a silicon substrate. 11 .