CN110534562A - Static random access memory - Google Patents

Abstract

The invention discloses a static random access memory. The storage unit includes six fin field effect transistors; each fin field effect transistor includes a fin body, a gate structure, a source region and a drain region; the fin body and the gate structure The extension direction is vertical; the gate structure includes a gate dielectric layer and a gate conductive material layer, a negative capacitance material layer is formed on the surface of the gate conductive material layer extending to the outside of the fin body, and a contact hole leading out of the gate conductive material layer is formed On the top of the negative capacitance material layer, it is connected to the gate extraction electrode formed by the interconnection structure of the front metal layer through the contact hole on the top of the negative capacitance material layer; the negative capacitance material layer forms a negative electrode between the gate conductive material layer and the gate extraction electrode. The capacitance is connected in series on the dielectric layer capacitance composed of the semiconductor substrate, the gate dielectric layer and the gate conductive material layer. The invention can reduce the sub-threshold swing of the transistor of the static random access memory, thereby reducing the operating voltage of the memory, reducing energy consumption and calorific value.

Description

SRAM

technical field

The invention relates to a semiconductor integrated circuit, in particular to a static random access memory (SRAM).

Background technique

Static random access memory is mainly used as a high-speed cache between the central processing unit (CPU) and the main memory due to its fast speed and the ability to save internal storage data without refreshing the circuit. The shortcomings such as low precision make it mainly used in critical systems to improve efficiency. With the evolution of integrated circuit manufacturing process nodes and the maturity of fin field effect transistor (FinFET) manufacturing technology, the size of FinFET-based SRAM is getting smaller and smaller, but due to the physical limit of the device subthreshold swing (SS) at room temperature is about 60mV /dec, SS indicates the amount of change in gate voltage when the subthreshold current is changed by 10 times. The physical limit of SS at room temperature makes it difficult to reduce the operating voltage of SRAM, and the problem of high energy consumption needs to be solved urgently.

As shown in Figure 1, it is a circuit diagram of a storage unit of an existing SRAM, which is based on FinFET; as shown in Figure 2, it is a layout of an existing SRAM; The random access memory includes an array structure formed by a plurality of memory cells 101 arranged in rows and columns.

Each storage unit 101 includes a first transmission pipe PG101, a second transmission pipe PG102, a first pull-up pipe PL101, a second pull-up pipe PL102, a first pull-down pipe PD101 and a second pull-down pipe PD102; The transfer tube PG101, the second transfer tube PG102, the first pull-down tube PD101 and the second pull-down tube PD102 are all NMOS tubes, and the first pull-up tube PL101 and the second pull-up tube PL102 Both are PMOS tubes.

Both the NMOS transistor and the PMOS transistor use fin field effect transistors.

As shown in FIG. 2 , each fin field effect transistor includes a fin body 104 , a gate structure, a source region and a drain region; the fin body 104 is composed of a patterned semiconductor substrate.

The fin body 104 is perpendicular to the extending direction of the gate structure, as shown in FIG. 2 , the extending direction of the gate structure is the extending direction of the gate strip 105; along the extending direction of the gate structure Above, the gate structure covers the two sides of the fin body 104 or the gate structure covers the two sides and the top surface of the fin body 104, and the fin body covered by the gate structure Channels are formed on the side or top surface of the fin body 104; in the extending direction along the fin body 104, the source region and the drain region are formed on both sides of the gate structure, and the source region and the drain region regions are connected by channels.

The gate structure includes a gate dielectric layer and a gate conductive material layer, and the gate conductive material layer is connected to the gate lead-out electrode formed by the front metal layer interconnection structure through the corresponding contact hole 108 at the top.

As shown in FIG. 2, in each storage unit 101, the gate extraction electrode of the first transmission tube PG101 and the grid extraction electrode of the second transmission tube PG102 pass through the mark 107c in FIG. The contact hole corresponding to 107d is connected to the word line WL formed by the front metal layer (not shown), and the marks 106a and 106b are also marks of the corresponding contact holes, and the right slash pattern area corresponding to the mark 109 corresponds to the contact hole cut-off ( CT cut) structure, the contact hole cut 109 disconnects the connection between the corresponding contact holes 106a and 107c and disconnects the connection between the corresponding contact holes 106b and 107d. In the layout shown in FIG. 2 , the layout of the front metal layer is not drawn.

The source region of the first transmission pipe PG101 is connected to the first bit line BL composed of the front metal layer through the contact hole 106c, and the source region of the second transmission pipe PG102 is connected to the first bit line BL composed of the front metal layer through the contact hole 106d. A second bit line BLB, the second bit line BLB is an inverse bit line of the first bit line BL. It can be seen from FIG. 2 that corresponding contact hole cutouts 109 are provided on both sides of the strip structures corresponding to the contact holes 106c and 106d.

The drain region of the first transfer transistor PG101, the drain region of the first pull-up transistor PL101, the drain region of the first pull-down transistor PD101, the gate lead-out electrode of the second pull-up transistor PL102 and the The gate extraction electrodes of the second pull-down transistor PD102 are all connected to the first storage node 107a.

The drain region of the second transfer transistor PG102, the drain region of the second pull-up transistor PL102, the drain region of the second pull-down transistor PD102, the gate lead-out electrode of the first pull-up transistor PL101 and the second The gate electrodes of the pull-down transistor PD101 are all connected to the second storage node 107b, and the first storage node 107a and the second storage node 107b are mutually inverse and interlocked.

Both the source region of the first pull-up transistor PL101 and the source region of the second pull-up transistor PL102 are connected to the power supply voltage VCC.

Both the source region of the first pull-down transistor PD101 and the source region of the second pull-down transistor PD102 are grounded to VSS.

On the layout structure of each storage unit 101:

Both the fin body 104 of the first transmission tube PG101 and the fin body 104 of the first pull-down tube PD101 are composed of a first fin body 104a.

The fin body 104 of the first pull-up tube PL101 is composed of the second fin body 104b.

The fin body 104 of the second pull-up tube PL102 is composed of a third fin body 104c.

Both the fin body 104 of the second transmission tube PG102 and the fin body 104 of the second pull-down tube PD102 are composed of a fourth fin body 104d. In order to more clearly represent the first fin body, the second fin body, the third fin body and the fourth fin body, these four fin bodies are separately marked with 104a, 104b, 104c and 104d said.

The first fin body 104a, the second fin body 104b, the third fin body 104c and the fourth fin body 104d are parallel to each other and along a direction perpendicular to each of the fin bodies 104 arrangement.

On the layout structure of each storage unit 101:

The gate conductive material layer of the first transfer transistor PG101, the gate conductive material layer of the second pull-up transistor PL102, and the gate conductive material layer of the second pull-down transistor PD102 are all in the first grid strip 105a, and the gate conductive material layer of the second pull-up tube PL102 and the gate conductive material layer of the second pull-down tube PD102 are connected together, and the gate conductive material layer of the first transfer tube PG101 and the gate conductive material layer of the second pull-up transistor PL102 are disconnected.

The gate conductive material layer of the first pull-down transistor PD101, the gate conductive material layer of the first pull-up transistor PL101, and the gate conductive material layer of the second transfer transistor PG102 are all on the second gate bar 105b, and the gate conductive material layer of the first pull-up transistor PL101 and the gate conductive material layer of the first pull-down transistor PD101 are connected together, and the gate conductive material layer of the second transfer transistor PG102 The material layer is disconnected from the gate conductive material layer of the first pull-up transistor PL101.

The first grid strip 105a is parallel to the second grid strip 105b.

The first transfer transistor PG101 and the first pull-down transistor PD101 share a drain region, and the second transfer transistor PG102 and the second pull-down transistor PD102 share a drain region.

The drain region of the first pull-down transistor PD101, the drain region of the first pull-up transistor PL101 and the gate extraction electrode of the second pull-up transistor PL102 are connected together through a contact hole 106a to form the first pull-up transistor PL101. A storage node 107a.

The drain region of the second pull-down transistor PD102, the drain region of the second pull-up transistor PL102 and the gate electrode of the first pull-up transistor PL101 are connected together through a contact hole 106b to form the second storage node 107b.

The first storage node 107a and the second storage node 107b are located between the first gate strip 105a and the second gate strip 105b.

Both the first bit line BL and the second bit line BLB are parallel to the first gate strip 105a, the first bit line BL is located outside the first gate strip 105a, the The second bit line BLB is located outside the second gate strip 105b.

The structure of one memory unit 101 is described in detail in FIG. 2 . For the entire array structure, the structures of each memory unit 101 are the same, and the layout structure is also the same or is a mirror image structure of each other.

Contents of the invention

The technical problem to be solved by the present invention is to provide a static random access memory, which can reduce the subthreshold swing of transistors in the static random access memory, thereby reducing the operating voltage of the memory, reducing energy consumption and heat generation.

In order to solve the above technical problems, the static random access memory provided by the present invention includes an array structure formed by a plurality of memory cells arranged in rows and columns.

Each storage unit includes a first transfer tube, a second transfer tube, a first pull-up tube, a second pull-up tube, a first pull-down tube, and a second pull-down tube; the first transfer tube, the second pull-down tube The transmission tube, the first pull-down tube and the second pull-down tube are all NMOS tubes, and the first pull-up tube and the second pull-up tube are all PMOS tubes.

Both the NMOS transistor and the PMOS transistor use fin field effect transistors.

Each of the fin field effect transistors includes a fin body, a gate structure, a source region and a drain region; the fin body is composed of a patterned semiconductor substrate, and the extending direction of the fin body and the gate structure is perpendicular; Along the extending direction of the gate structure, the gate structure covers the two sides of the fin or the gate structure covers the two sides and the top surface of the fin, and is covered by the gate The side or top surface of the fin body covered by the structure forms a channel; in the extending direction along the fin body, the source region and the drain region are formed on both sides of the gate structure, the The source region and the drain region are connected through a channel.

The gate structure includes a gate dielectric layer and a gate conductive material layer, and a negative capacitance material layer is formed on the surface of the gate conductive material layer extending to the outside of the fin body, leading out the gate conductive material layer The contact hole is formed on the top of the negative capacitance material layer, and is connected to the gate lead-out electrode formed by the front metal layer interconnection structure through the contact hole on the top of the negative capacitance material layer; A negative capacitance is formed between the electrode conductive material layer and the gate lead-out electrode and is connected in series on the dielectric layer capacitance composed of the semiconductor substrate, the gate dielectric layer and the gate conductive material layer, so as to reduce the The subthreshold swing of a type field effect transistor.

A further improvement is that, in each of the memory cells, the gate extraction electrode of the first transfer transistor and the gate extraction electrode of the second transfer transistor are both connected to a word line composed of a front metal layer, so The source region of the first transmission pipe is connected to the first bit line formed by the front metal layer through the contact hole, and the source region of the second transmission pipe is connected to the second bit line formed by the front metal layer through the contact hole, so The second bit line is an inversion of the first bit line.

The drain region of the first transfer transistor, the drain region of the first pull-up transistor, the drain region of the first pull-down transistor, the gate extraction electrode of the second pull-up transistor, and the second pull-down transistor The gate extraction electrodes are all connected to the first storage node.

The drain region of the second transfer transistor, the drain region of the second pull-up transistor, the drain region of the second pull-down transistor, the gate extraction electrode of the first pull-up transistor, and the first pull-down transistor The gate extraction electrodes of all are connected to the second storage node, and the first storage node and the second storage node are mutually inverting and interlocked.

Both the source region of the first pull-up transistor and the source region of the second pull-up transistor are connected to a power supply voltage.

Both the source area of the first pull-down tube and the source area of the second pull-down tube are grounded.

A further improvement is, on the layout structure of each storage unit:

Both the fin body of the first transfer tube and the fin body of the first pull-down tube are composed of a first fin body.

The fin body of the first pull-up tube is composed of the second fin body.

The fin body of the second pull-up tube is composed of a third fin body.

Both the fin body of the second transfer tube and the fin body of the second pull-down tube are composed of a fourth fin body.

The first fin body, the second fin body, the third fin body and the fourth fin body are parallel to each other and arranged along a direction perpendicular to each of the fin bodies.

A further improvement is, on the layout structure of each storage unit:

The gate conductive material layer of the first transmission tube, the gate conductive material layer of the second pull-up tube, and the gate conductive material layer of the second pull-down tube all extend on the first grid strip, And the gate conductive material layer of the second pull-up tube and the gate conductive material layer of the second pull-down tube are connected together, the gate conductive material layer of the first transfer tube and the second pull-up tube The connection between the gate conductive material layer of the tube is disconnected.

The gate conductive material layer of the first pull-down transistor, the gate conductive material layer of the first pull-up transistor, and the gate conductive material layer of the second transfer transistor all extend on the second grid strip , and the gate conductive material layer of the first pull-up tube and the gate conductive material layer of the first pull-down tube are connected together, the gate conductive material layer of the second transfer tube and the first The gate conductive material layers of the pull-up transistors are disconnected.

The first grid strips are parallel to the second grid strips.

A further improvement is that the first transfer tube and the first pull-down tube share a drain area, and the second transfer tube and the second pull-down tube share a drain area.

The drain region of the first pull-down transistor, the drain region of the first pull-up transistor and the gate extraction electrode of the second pull-up transistor are connected together through a contact hole to form the first storage node.

The drain region of the second pull-down transistor, the drain region of the second pull-up transistor and the gate extraction electrode of the first pull-up transistor are connected together through a contact hole to form the second storage node.

The first storage node and the second storage node are located between the first gate stripe and the second gate stripe.

A further improvement is that both the first bit line and the second bit line are parallel to the first gate strip, the first bit line is located outside the first gate strip, and the The second bit line is located outside the second gate stripe.

A further improvement is that the material of the negative capacitance material layer includes a ferroelectric material.

A further improvement is that the ferroelectric material used in the negative capacitance material layer includes materials containing Zr, Ba or Sr.

A further improvement is that the ferroelectric material used in the negative capacitance material layer includes HfZrO2, BaTiO3, KH2PO4 or NBT.

A further improvement is that a first interface buffer layer is formed between the negative capacitance material layer and the gate conductive material layer, and a first interface buffer layer is formed between the negative capacitance material layer and the corresponding contact hole at the top. Two interface buffer layers.

A further improvement is that, in the layout structure, each of the negative capacitance material layers has a rectangular top view structure, and the length sides of the negative capacitance material layers are parallel to the extension direction of the corresponding gate conductive material layer.

The width of the negative capacitance material layer is greater than or equal to the width of the gate conductive material layer, and in the width direction of the gate conductive material layer, the negative capacitance material layer extends to the outside of the gate conductive material layer .

Alternatively, the width of the negative capacitance material layer is smaller than the width of the gate conductive material layer.

A further improvement is that the material of the gate dielectric layer includes silicon oxide, silicon oxynitride or high dielectric constant material.

A further improvement is that the high dielectric constant material includes hafnium dioxide.

A further improvement is that the material of the gate conductive material layer is polysilicon.

A further improvement is that the material of the gate conductive material layer is metal.

A further improvement is that the metal material of the gate conductive material layer includes Al or W.

A further improvement is that, in the fin field effect transistor corresponding to the NMOS transistor, both the source region and the drain region are doped with N+, and the fin body is doped with P type.

In the fin field effect transistor corresponding to the PMOS transistor, both the source region and the drain region are doped with P+, and the fin body is doped with N type.

The transistors of the static random access memory of the present invention all adopt fin field effect transistors, and the extension direction of the fin body and the gate structure is vertical, and the present invention forms a negative capacitance on the surface of the gate conductive material layer extending to the outside of the fin body The material layer, the contact hole leading out the gate conductive material layer is formed on the top of the negative capacitance material layer and thus a negative capacitance is connected in series on the basis of the dielectric layer capacitance of the gate structure. Since the negative capacitance has the function of voltage amplification, it can make The external gate voltage transfer to the channel surface voltage increases, enabling smaller changes in the external gate voltage to produce larger changes in the subthreshold current, thereby reducing the subthreshold swing and thus reducing the operating voltage of the memory , reduce energy consumption and heat generation.

In addition, the negative capacitance material layer of the present invention is disposed on the top of the gate conductive material layer and located in the region of the contact hole corresponding to the gate conductive material layer, so the negative capacitance material layer of the present invention does not need to be disposed in the gate structure of the gate structure. The gap between the dielectric layer and the gate conductive material layer has the characteristics of simple process structure and no adverse effect on the gate structure, which facilitates the realization of process integration.

Description of drawings

Below in conjunction with accompanying drawing and specific embodiment the present invention will be described in further detail:

Fig. 1 is the circuit diagram of the storage unit of existing SRAM;

FIG. 2 is a layout of an existing static random access memory;

3 is a circuit diagram of a storage unit of an SRAM according to an embodiment of the present invention;

4 is a schematic structural diagram of a fin field effect transistor used in an embodiment of the present invention;

FIG. 5 is a layout of the SRAM according to the embodiment of the present invention.

Detailed ways

As shown in Figure 3, it is a circuit diagram of the storage unit 1 of the static random access memory of the embodiment of the present invention; as shown in Figure 4, it is a schematic structural diagram of the fin field effect transistor adopted in the embodiment of the present invention; as shown in Figure 5 Shown is the layout of the static random access memory of the embodiment of the present invention; the static random access memory of the embodiment of the present invention includes an array structure formed by a plurality of memory cells 1 arranged in rows and columns.

Each storage unit 1 includes a first transmission tube PG1, a second transmission tube PG2, a first pull-up tube PL1, a second pull-up tube PL2, a first pull-down tube PD1, and a second pull-down tube PD2; The transmission tube PG1, the second transmission tube PG2, the first pull-down tube PD1 and the second pull-down tube PD2 are all NMOS tubes, and the first pull-up tube PL1 and the second pull-up tube PL2 Both are PMOS tubes.

Both the NMOS transistor and the PMOS transistor use fin field effect transistors.

As shown in FIG. 2 , each fin field effect transistor includes a fin body 4 , a gate structure, a source region 201 and a drain region 202 ; the fin body 4 is composed of a patterned semiconductor substrate.

The extending direction of the fin body 4 and the gate structure is vertical, as shown in FIG. The cross-sectional structure of the extending direction of the fin body 4; in the extending direction along the gate structure, the gate structure covers both sides of the fin body 4 or the gate structure covers the fin body 4 On both sides and the top surface, the side or top surface of the fin body 4 covered by the gate structure forms a channel; in the extending direction along the fin body 4, the source region 201 and the drain A region 202 is formed on both sides of the gate structure, and the source region 201 and the drain region 202 are connected through a channel.

The gate structure includes a gate dielectric layer 203 and a gate conductive material layer 204, and a negative capacitance material layer 205 is formed on the surface of the gate conductive material layer 204 extending to the outside of the fin body 4, as shown in FIG. 4 , in order to well show that the negative capacitance material layer 205 is located on the surface of the gate conductive material layer 204, the negative capacitance material layer 205 is also placed in FIG. 4; it can be seen from the layout structure shown in FIG. , the negative capacitance material layer 205 is not formed on all the surfaces of the gate conductive material layer 204, so please understand the negative capacitance material layer of the present invention in conjunction with the cross-sectional structure of FIG. 4 and the layout structure of FIG. 5 205 structural features.

The contact hole 8 leading out the gate conductive material layer 204 is formed on the top of the negative capacitance material layer 205, through which the contact hole 8 on the top of the negative capacitance material layer 205 is connected to the interconnect structure formed by the front metal layer 206. As for the gate extraction electrode, since in a semiconductor integrated circuit, the front metal layer usually includes multiple layers, the number 206 in FIG. 4 represents the front metal layer at the top of the contact hole 8 corresponding to the negative capacitance material layer 205 .

The negative capacitance material layer 205 forms a negative capacitance between the gate conductive material layer 204 and the gate lead-out electrode and is connected in series by the semiconductor substrate, the gate dielectric layer 203 and the gate conductive material layer 204. layer 204 to reduce the sub-threshold swing of the FinFET.

As shown in FIG. 5 , in each storage unit 1 , the gate extraction electrode of the first transmission tube PG1 and the grid extraction electrode of the second transmission tube PG2 respectively pass through the mark 7c in FIG. 5 The contact holes corresponding to 7d are all connected to the word line WL composed of the front metal layer (not shown); marks 6a and 6b are also the marks of the corresponding contact holes, and the right slash pattern area corresponding to mark 9 corresponds to the contact hole cut-off structure, the contact hole cut-off 9 disconnects the connection between the corresponding contact holes 6a and 7c and disconnects the connection between the corresponding contact holes 6b and 7d. In the layout shown in FIG. 5 , the layout of the front metal layer is not drawn.

The source region 201 of the first transmission pipe PG1 is connected to the first bit line BL composed of the front metal layer through the contact hole 6c, and the source region 201 of the second transmission pipe PG2 is connected to the first bit line BL composed of the front metal layer through the contact hole 6d. A second bit line BLB is formed, and the second bit line BLB is an inverse bit line of the first bit line BL. It can be seen from FIG. 5 that corresponding contact hole cutouts 9 are provided on both sides of the strip structures corresponding to the contact holes 6c and 6d.

The drain region 202 of the first transfer transistor PG1, the drain region 202 of the first pull-up transistor PL1, the drain region 202 of the first pull-down transistor PD1, and the gate extraction electrode of the second pull-up transistor PL2 and the gate extraction electrode of the second pull-down transistor PD2 are connected to the first storage node 7a.

The drain region 202 of the second transfer transistor PG2, the drain region 202 of the second pull-up transistor PL2, the drain region 202 of the second pull-down transistor PD2, the gate lead-out electrode of the first pull-up transistor PL1 and The gate electrodes of the first pull-down transistor PD1 are all connected to the second storage node 7b, and the first storage node 7a and the second storage node 7b are mutually inverse and interlocked.

The source region 201 of the first pull-up transistor PL1 and the source region 201 of the second pull-up transistor PL2 are both connected to the power supply voltage VCC.

Both the source region 201 of the first pull-down transistor PD1 and the source region 201 of the second pull-down transistor PD2 are grounded to VSS.

On the layout structure of each storage unit 1:

Both the fin body 4 of the first transmission pipe PG1 and the fin body 4 of the first pull-down pipe PD1 are composed of a first fin body 4a.

The fin body 4 of the first pull-up tube PL1 is composed of a second fin body 4b.

The fin body 4 of the second pull-up tube PL2 is composed of a third fin body 4c.

Both the fin body 4 of the second transmission pipe PG2 and the fin body 4 of the second pull-down pipe PD2 are composed of a fourth fin body 4d. In order to more clearly represent the first fin body, the second fin body, the third fin body and the fourth fin body, these four fin bodies are separately marked with 4a, 4b, 4c and 4d representation.

The first fin body 4a, the second fin body 4b, the third fin body 4c and the fourth fin body 4d are parallel to each other and along a direction perpendicular to each of the fin bodies 4 arrangement.

On the layout structure of each storage unit 1:

The gate conductive material layer 204 of the first transfer transistor PG1, the gate conductive material layer 204 of the second pull-up transistor PL2 and the gate conductive material layer 204 of the second pull-down transistor PD2 are all on the first gate The pole strip 5a extends, and the gate conductive material layer 204 of the second pull-up transistor PL2 and the gate conductive material layer 204 of the second pull-down transistor PD2 are connected together, and the gate conductive material layer 204 of the first transfer transistor PG1 The gate conductive material layer 204 is disconnected from the gate conductive material layer 204 of the second pull-up transistor PL2.

The gate conductive material layer 204 of the first pull-down transistor PD1, the gate conductive material layer 204 of the first pull-up transistor PL1 and the gate conductive material layer 204 of the second transfer transistor PG2 are all on the second The gate strip 5b extends upward, and the gate conductive material layer 204 of the first pull-up transistor PL1 and the gate conductive material layer 204 of the first pull-down transistor PD1 are connected together, and the second transmission tube The gate conductive material layer 204 of PG2 is disconnected from the gate conductive material layer 204 of the first pull-up transistor PL1.

The first grid strip 5a is parallel to the second grid strip 5b.

The first transmission transistor PG1 and the first pull-down transistor PD1 share a drain region 202 , and the second transmission transistor PG2 and the second pull-down transistor PD2 share a drain region 202 .

The drain region 202 of the first pull-down transistor PD1, the drain region 202 of the first pull-up transistor PL1 and the gate extraction electrode of the second pull-up transistor PL2 are connected together through a contact hole 6a to form the Describe the first storage node 7a.

The drain region 202 of the second pull-down transistor PD2, the drain region 202 of the second pull-up transistor PL2 and the gate extraction electrode of the first pull-up transistor PL1 are connected together through a contact hole 6b and form the the second storage node 7b.

The first storage node 7a and the second storage node 7b are located between the first gate strip 5a and the second gate strip 5b.

Both the first bit line BL and the second bit line BLB are parallel to the first gate strip 5a, the first bit line BL is located outside the first gate strip 5a, the The second bit line BLB is located outside the second gate strip 5b.

The structure of one memory cell 1 is described in detail in FIG. 5 . For the entire array structure, each memory cell 1 has the same structure, and the same layout structure or a mirror image structure.

The material of the negative capacitance material layer 205 includes ferroelectric material. The ferroelectric material used in the negative capacitance material layer 205 includes materials containing Zr, Ba or Sr. Preferably, the ferroelectric material used for the negative capacitance material layer 205 includes HfZrO2, BaTiO3, KH2PO4 or NBT. A first interface buffer layer is formed between the negative capacitance material layer 205 and the gate conductive material layer 204, and a second interface buffer layer is formed between the negative capacitance material layer 205 and the contact hole 8 corresponding to the top. Interface buffer layer.

In terms of layout structure, the plan view structure of each negative capacitance material layer 205 is a rectangle, and the length side of the negative capacitance material layer 205 is parallel to the extension direction of the corresponding gate conductive material layer 204 . The width of the negative capacitance material layer 205 is greater than or equal to the width of the gate conductive material layer 204, and in the width direction of the gate conductive material layer 204, the negative capacitance material layer 205 extends to the gate conductive material layer 204. The outer side of the material layer 204 . In other embodiments, it can also be: the width of the negative capacitance material layer 205 is smaller than the width of the gate conductive material layer 204 .

The material of the gate dielectric layer 203 includes silicon oxide, silicon oxynitride or high dielectric constant material. The high dielectric constant material includes hafnium dioxide.

The material of the gate conductive material layer 204 is polysilicon. In other embodiments, it can also be: the material of the gate conductive material layer 204 is metal. The metal material of the gate conductive material layer 204 includes Al or W.

Wherein, when the gate dielectric layer 203 is made of high dielectric constant material and the gate conductive material layer 204 is made of metal material, the gate structure of Zeus is HKMG. In the gate dielectric layer 203, an interface layer is usually formed between the high dielectric constant material layer and the surface of the semiconductor substrate, and the metal layer between the high dielectric constant material layer and the gate conductive material layer 204 A work function layer is usually provided between the materials, and a barrier layer can also be provided as required.

In the FinFET corresponding to the NMOS transistor, both the source region 201 and the drain region 202 are doped with N+, and the fin body 4 is doped with P type.

In the FinFET corresponding to the PMOS transistor, both the source region 201 and the drain region 202 are doped with P+, and the fin body 4 is doped with N type.

The transistors of the static random access memory in the embodiment of the present invention all adopt fin field effect transistors, and the extending direction of the fin body 4 and the gate structure is vertical, and the present invention extends to the surface of the gate conductive material layer 204 outside the fin body 4 A negative capacitance material layer 205 is formed, and the contact hole 8 leading out of the gate conductive material layer 204 is formed on the top of the negative capacitance material layer 205 and thus a negative capacitance is connected in series on the basis of the dielectric layer capacitance of the gate structure, because the negative capacitance has The effect of voltage amplification, so that the external gate voltage can be transferred to the channel surface voltage to increase, so that a small change in the external gate voltage can produce a larger change in the subthreshold current, thereby reducing the subthreshold swing, Finally, it can break through the limit limit of 60mV/dec in the sub-threshold swing of the transistor in the prior art, and thus can reduce the operating voltage of the memory, and reduce energy consumption and heat generation.

In addition, the negative capacitance material layer 205 of the embodiment of the present invention is disposed on the top of the gate conductive material layer 204 and is located in the area of the contact hole 8 corresponding to the gate conductive material layer 204, so the negative capacitance material layer 205 of the embodiment of the present invention does not It needs to be arranged between the gate dielectric layer 203 and the gate conductive material layer 204 in the gate structure, which has the characteristics of simple process structure and no adverse effect on the gate structure, and facilitates process integration.

The present invention has been described in detail through specific examples above, but these do not constitute a limitation to the present invention. Without departing from the principle of the present invention, those skilled in the art can also make many modifications and improvements, which should also be regarded as the protection scope of the present invention.

Claims (15)

1. A static random access memory, characterized in that: the static random access memory comprises an array structure formed by a plurality of memory cell rows and columns; Each storage unit includes a first transfer tube, a second transfer tube, a first pull-up tube, a second pull-up tube, a first pull-down tube, and a second pull-down tube; the first transfer tube, the second pull-down tube The transmission tube, the first pull-down tube and the second pull-down tube are all NMOS tubes, and the first pull-up tube and the second pull-up tube are all PMOS tubes; Both the NMOS tube and the PMOS tube use fin field effect transistors; Each of the fin field effect transistors includes a fin body, a gate structure, a source region and a drain region; the fin body is composed of a patterned semiconductor substrate, and the extending direction of the fin body and the gate structure is perpendicular; Along the extending direction of the gate structure, the gate structure covers the two sides of the fin or the gate structure covers the two sides and the top surface of the fin, and is covered by the gate The side or top surface of the fin body covered by the structure forms a channel; in the extending direction along the fin body, the source region and the drain region are formed on both sides of the gate structure, the The source region is connected to the drain region through a channel; The gate structure includes a gate dielectric layer and a gate conductive material layer, and a negative capacitance material layer is formed on the surface of the gate conductive material layer extending to the outside of the fin body, leading out the gate conductive material layer The contact hole is formed on the top of the negative capacitance material layer, and is connected to the gate lead-out electrode formed by the front metal layer interconnection structure through the contact hole on the top of the negative capacitance material layer; A negative capacitance is formed between the electrode conductive material layer and the gate lead-out electrode and is connected in series on the dielectric layer capacitance composed of the semiconductor substrate, the gate dielectric layer and the gate conductive material layer, so as to reduce the The subthreshold swing of a type field effect transistor. 2. The static random access memory according to claim 1, characterized in that: in each of the memory cells, the gate lead-out electrode of the first transfer transistor and the gate lead-out electrode of the second transfer transistor The electrodes are all connected to the word line composed of the front metal layer, the source region of the first transfer tube is connected to the first bit line composed of the front metal layer through the contact hole, and the source region of the second transfer tube is connected through the contact hole connected to a second bit line consisting of a front metal layer, the second bit line being an inverse phase line of the first bit line; The drain region of the first transfer transistor, the drain region of the first pull-up transistor, the drain region of the first pull-down transistor, the gate extraction electrode of the second pull-up transistor, and the second pull-down transistor The gate extraction electrodes of all are connected to the first storage node; The drain region of the second transfer transistor, the drain region of the second pull-up transistor, the drain region of the second pull-down transistor, the gate extraction electrode of the first pull-up transistor, and the first pull-down transistor The gate extraction electrodes of all are connected to the second storage node, and the first storage node and the second storage node are mutually inverse and interlocked; Both the source region of the first pull-up transistor and the source region of the second pull-up transistor are connected to a power supply voltage; Both the source area of the first pull-down tube and the source area of the second pull-down tube are grounded. 3. The static random access memory as claimed in claim 2, characterized in that, on the layout structure of each said storage unit: Both the fin body of the first transfer tube and the fin body of the first pull-down tube are composed of a first fin body; The fin body of the first pull-up tube is composed of a second fin body; The fin body of the second pull-up tube is composed of a third fin body; Both the fin body of the second transfer pipe and the fin body of the second pull-down pipe are composed of a fourth fin body; The first fin body, the second fin body, the third fin body and the fourth fin body are parallel to each other and arranged along a direction perpendicular to each of the fin bodies. 4. SRAM as claimed in claim 3, is characterized in that, on the domain structure of each described storage unit: The gate conductive material layer of the first transmission tube, the gate conductive material layer of the second pull-up tube, and the gate conductive material layer of the second pull-down tube all extend on the first grid strip, And the gate conductive material layer of the second pull-up tube and the gate conductive material layer of the second pull-down tube are connected together, the gate conductive material layer of the first transfer tube and the second pull-up tube Disconnection between the grid conductive material layers of the tube; The gate conductive material layer of the first pull-down transistor, the gate conductive material layer of the first pull-up transistor, and the gate conductive material layer of the second transfer transistor all extend on the second grid strip , and the gate conductive material layer of the first pull-up tube and the gate conductive material layer of the first pull-down tube are connected together, the gate conductive material layer of the second transfer tube and the first The gate conductive material layer of the pull-up tube is disconnected; The first grid strips are parallel to the second grid strips. 5. The static random access memory as claimed in claim 4, characterized in that: the first transmission pipe and the first pull-down pipe share a drain region, and the second transmission pipe and the second pull-down pipe shared drain area; The drain region of the first pull-down transistor, the drain region of the first pull-up transistor, and the gate electrode of the second pull-up transistor are connected together through a contact hole to form the first storage node; The drain region of the second pull-down transistor, the drain region of the second pull-up transistor, and the gate extraction electrode of the first pull-up transistor are connected together through a contact hole to form the second storage node; The first storage node and the second storage node are located between the first gate stripe and the second gate stripe. 6. The static random access memory as claimed in claim 5, characterized in that: the first bit line and the second bit line are parallel to the first gate strip, and the first bit line The second bit line is located outside the first gate strip, and the second bit line is located outside the second gate strip. 7. The SRAM according to claim 1, wherein the material of the negative capacitance material layer comprises ferroelectric material. 8. The SRAM according to claim 7, wherein the ferroelectric material used in the negative capacitance material layer includes materials containing Zr, Ba or Sr. 9. The SRAM according to claim 8, wherein the ferroelectric material used in the negative capacitance material layer includes HfZrO2, BaTiO3, KH2PO4 or NBT. 10. The static random access memory as claimed in claim 1, characterized in that: a first interface buffer layer is formed between the negative capacitance material layer and the gate conductive material layer, and a first interface buffer layer is formed between the negative capacitance material layer A second interface buffer layer is formed between the layer and the contact hole corresponding to the top. 11. The static random access memory as claimed in claim 1, characterized in that: on the layout structure, the top view surface structure of each of the negative capacitance material layers is rectangular, and the length sides of the negative capacitance material layers and the corresponding The extension direction of the gate conductive material layer is parallel; The width of the negative capacitance material layer is greater than or equal to the width of the gate conductive material layer, and in the width direction of the gate conductive material layer, the negative capacitance material layer extends to the outside of the gate conductive material layer ; Alternatively, the width of the negative capacitance material layer is smaller than the width of the gate conductive material layer. 12. The static random access memory according to claim 1, characterized in that: the material of the gate dielectric layer includes silicon oxide, silicon oxynitride or high dielectric constant material; the high dielectric constant material includes hafnium. 13. The static random access memory as claimed in claim 10, wherein the gate conductive material layer is made of polysilicon. 14. The static random access memory as claimed in claim 10, wherein the gate conductive material layer is made of metal. 15. The static random access memory according to claim 1, wherein in the fin field effect transistor corresponding to the NMOS transistor, both the source region and the drain region are doped with N+, and the The fin body is P-type doped; In the fin field effect transistor corresponding to the PMOS transistor, both the source region and the drain region are doped with P+, and the fin body is doped with N type.