CN110534149A - The single programmable memory of varying storage capacity - Google Patents

Abstract

The invention provides a one-time programmable memory with variable storage capacity, which includes: multiple storage units and multiple address bits; and a control circuit for configuring the corresponding relationship between the address bits and the storage units according to the programming yield. The one-time programmable memory with variable storage capacity of the present invention configures the corresponding relationship between address bits and storage units according to the programming yield rate through the control circuit, and configures more alternative storage when the programming yield rate is unknown or low. unit to achieve the purpose of multiple programming to improve chip yield. When the programming yield is high, configure fewer alternative storage units to avoid unnecessary waste, increase storage capacity, save chip area, and reduce manufacturing costs. Enhance chip applicability.

Description

One-time programmable memory with variable storage capacity

technical field

The invention relates to a one-time programmable memory with variable storage capacity.

Background technique

In the chip manufacturing process, due to the influence of various factors such as machine parameters and temperature distribution, there will be different degrees of parameter drift between chips, such as oscillator frequency, reference voltage or current value and the design value. This will lead to inconsistency problems in the application process of the chip, which will affect the product yield, such as the deviation of the camera effect caused by the camera module, the difference in the driving voltage of different LCD panels, etc. Therefore, it is necessary to correct the specific parameters of the chip, and Store the corrected value into the register, read and correct these parameters after the chip is powered on, so as to improve the consistency problem and improve the product yield. This function is usually implemented using OTP (One Time Programming) memory, that is, one-time programmable memory.

Because the programming process of OTP memory is usually destructive, such as dielectric breakdown type (including fuse type and antifuse type) OTP memory, the success rate of its programming also affects the chip yield.

Figure 1 is a commonly used dielectric breakdown type OTP memory structure. MOS transistor A is used as a storage unit, and a programming voltage VPP is applied to its gate for a certain period of time to make it break down and write "1" to the storage unit. The programmed storage unit is "0", and the read and write of the storage unit is controlled by selecting the switch M0.

In order to improve the success rate of programming, a spare storage unit is usually added to the same address. This method sacrifices the storage capacity of the OTP memory under the limited chip area, and the redundant storage unit will occupy a larger chip area and increase the cost.

Figure 2 is a circuit structure with a backup OTP memory, the circuit structure includes a plurality of OTP memories, when a storage unit in a certain OTP memory is not programmed successfully, the backup storage unit in the backup OTP memory will be selected by a control signal until the address is programmed successfully. The total storage capacity of this structure is the capacity of a single OTP memory, but it needs to occupy a larger chip area.

Figure 3 is another common practice, that is, in the same OTP memory, configure multiple storage units A for the same address. When a certain storage unit A fails to be programmed, a spare storage unit A will be selected until the address is successfully programmed. . When the OTP programming yield rate is low, you can choose to program different storage units A to achieve the purpose of multiple programming to improve the chip yield rate. However, when the OTP programming yield rate is high, there are more alternatives. Storage cells create unnecessary waste.

In addition, the programming and reading time of the OTP memory and the programming voltage are closely related to the process parameters. In the process of chip replacement, it is necessary to make a decision based on the storage address capacity, area, number of spare memory cells and chip yield of the OTP memory. Choose a compromise.

Contents of the invention

The object of the present invention is to provide a one-time programmable memory with variable storage capacity, which can flexibly configure storage capacity, ensure chip yield, save chip area, reduce manufacturing cost, and enhance chip applicability.

Based on the above considerations, the present invention provides a one-time programmable memory with variable storage capacity, including: a plurality of storage units and a plurality of address bits; a control circuit for configuring the correspondence between the address bits and the storage units according to the programming yield rate relation.

Preferably, each storage unit includes at least two burnable subunits.

Preferably, when the programming yield is higher than the preset threshold, the control circuit is configured such that one address bit corresponds to one memory cell.

Preferably, when the programming yield is unknown or lower than a preset threshold, the control circuit is configured such that one address bit corresponds to at least two memory cells.

Preferably, the one-time programmable memory is a dielectric breakdown one-time programmable memory.

Preferably, the dielectric breakdown type one-time programmable memory includes a fuse type one-time programmable memory and an anti-fuse type one-time programmable memory.

The one-time programmable memory with variable storage capacity of the present invention configures the corresponding relationship between address bits and storage units according to the programming yield rate through the control circuit, and configures more alternative storage when the programming yield rate is unknown or low. unit to achieve the purpose of multiple programming to improve chip yield. When the programming yield is high, configure fewer alternative storage units to avoid unnecessary waste, increase storage capacity, save chip area, and reduce manufacturing costs. Enhance chip applicability.

Description of drawings

Other features and advantages of the present invention will become clear or be more specifically explained through the accompanying drawings and the following specific embodiments used to illustrate some principles of the present invention together with the accompanying drawings.

Fig. 1 is the structural representation of existing dielectric breakdown type OTP memory;

Fig. 2 is the circuit structure schematic diagram of existing band backup OTP memory;

Fig. 3 is the structural representation of the existing OTP memory with spare storage unit;

FIG. 4 is a schematic structural diagram of an OTP memory with variable storage capacity according to an embodiment of the present invention.

Detailed ways

In the following detailed description of the preferred embodiment, reference is made to the accompanying drawings which form a part hereof. The accompanying drawings show, by way of example, specific embodiments in which the invention can be practiced. The illustrated embodiments are not intended to be exhaustive of all embodiments in accordance with the invention. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. Accordingly, the following detailed description is not limiting, and the scope of the invention is defined by the appended claims.

FIG. 4 shows an OTP memory with variable storage capacity according to an embodiment of the present invention, the OTP memory includes a plurality of storage units and a plurality of address bits. It is enough to ensure a high chip yield by only configuring fewer candidate memory cells

In the preferred embodiment shown in Figure 4, the OTP memory includes eight storage units A, B, C...H, each storage unit includes two programmable sub-units, for example, storage unit A includes two programmable sub-units The recording sub-units A0, A1; the storage unit B include two burnable sub-units B0, B1; . . . Those skilled in the art can understand that the OTP memory of the present invention may also include other numbers of storage units, and each storage unit may also include other numbers of programmable sub-units. Preferably, each storage unit includes at least two burnable subunits.

In the preferred embodiment shown in FIG. 4, the OTP memory includes two address bit combinations. Combination 1 includes eight address bits 000, 001, 010, 011, 100, 101, 110, 111 for realizing 8bits storage capacity. Combination 2 includes four new address bits 000', 001', 010', 011' formed by merging the eight address bits in combination 1 to achieve 4bits storage capacity, where address bit 000' corresponds to combination 1 000 and 100 in , the address bit 001' corresponds to 001 and 101 in combination 1... The correspondence between the address bits of combination 1 and combination 2 is not limited to this, and it is only used as an example and not a limitation. Those skilled in the art can understand that the OTP memory of the present invention may also include other number of address bit combinations, and each address bit combination may also include other number of address bits.

In addition, the OTP memory of the present invention also includes a control circuit for configuring the corresponding relationship between address bits and storage units according to the programming yield.

When the OTP programming yield is low, such as lower than the preset threshold, or when the initial tape-out programming yield is unknown, the control circuit sends a control signal to select address bit combination 2, and the storage capacity is 4 bits at this time. Therefore, the four address bits correspond to eight storage units respectively, that is, one address bit corresponds to two storage units. For example, address bit 000' corresponds to memory cells A and E, address bit 001' corresponds to memory cells B and F... Since each memory cell includes two programmable sub-units, each address bit can be performed up to four times burning. That is to say, when the programming yield is unknown or low, it is possible to configure more candidate memory cells for each address bit to achieve the purpose of increasing the chip yield by multiple programming.

When the OTP programming yield is high, for example, higher than the preset threshold, the control circuit sends a control signal to select the address bit combination 1, and the storage capacity is 8 bits at this time. Therefore, the eight address bits correspond to eight storage units respectively, that is, one address bit corresponds to one storage unit. For example, address bit 000 corresponds to storage unit A, and address bit 001 corresponds to storage unit B... Since each storage unit includes two programmable subunits, each address bit can be programmed twice at most. When programming When the yield rate is high, each address bit only needs to be equipped with fewer candidate storage units, which is enough to ensure a high chip yield rate, avoid unnecessary waste, increase storage capacity, save chip area, and reduce The manufacturing cost is reduced, and the applicability of the chip is enhanced.

It can be seen that the present invention realizes reasonable allocation and control of OTP address bits and storage units through the control circuit, and realizes an OTP memory structure with variable storage capacity. When the programming yield is unknown or low, it can provide more alternative storage units for multiple programming to ensure the chip yield. When the programming yield is high, it only needs to configure fewer alternative storage units It is enough to ensure the chip yield rate, and at the same time, the OTP storage capacity can be flexibly increased to provide more register calibration bits to adapt to different chip application environments.

Preferably, the one-time programmable memory is a dielectric breakdown one-time programmable memory.

Preferably, the dielectric breakdown type one-time programmable memory includes a fuse type one-time programmable memory and an anti-fuse type one-time programmable memory.

The one-time programmable memory with variable storage capacity of the present invention configures the corresponding relationship between address bits and storage units according to the programming yield rate through the control circuit, and configures more alternative storage when the programming yield rate is unknown or low. unit to achieve the purpose of multiple programming to improve chip yield. When the programming yield is high, configure fewer alternative storage units to avoid unnecessary waste, increase storage capacity, save chip area, and reduce manufacturing costs. Enhance chip applicability.

It will be apparent to those skilled in the art that the invention is not limited to the details of the above-described exemplary embodiments, but that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Accordingly, the embodiments should be regarded in all respects as exemplary and not restrictive. Furthermore, it is obvious that the word "comprising" does not exclude other elements and steps, and the word "a" does not exclude the plural. A plurality of elements recited in device claims may also be embodied by one element. The words first, second, etc. are used to denote names without implying any particular order.

Claims (6)

1. A one-time programmable memory with variable storage capacity, characterized in that, comprising: Multiple memory locations and multiple address bits; The control circuit is used to configure the corresponding relationship between the address bits and the memory cells according to the programming yield. 2. The one-time programmable memory with variable storage capacity as claimed in claim 1, wherein each storage unit comprises at least two programmable subunits. 3. The one-time programmable memory with variable storage capacity according to claim 1, wherein when the programming yield is higher than a preset threshold, the control circuit is configured such that one address bit corresponds to one memory cell. 4. The one-time programmable memory with variable storage capacity according to claim 1, wherein when the programming yield is unknown or lower than a preset threshold, the control circuit is configured such that one address bit corresponds to at least two memory cells . 5. The one-time programmable memory with variable storage capacity according to claim 1, wherein the one-time programmable memory is a dielectric breakdown type one-time programmable memory. 6. The one-time programmable memory with variable storage capacity as claimed in claim 5, wherein the dielectric breakdown type one-time programmable memory comprises a fuse type one-time programmable memory and an anti-fuse type one-time programmable memory subprogrammable memory.