CN110532030B - Method for optimizing register access in CPU - Google Patents
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- CN110532030B CN110532030B CN201910710720.XA CN201910710720A CN110532030B CN 110532030 B CN110532030 B CN 110532030B CN 201910710720 A CN201910710720 A CN 201910710720A CN 110532030 B CN110532030 B CN 110532030B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30043—LOAD or STORE instructions; Clear instruction
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
- G06F9/3009—Thread control instructions
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
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Abstract
The invention discloses a method for optimizing register access in a CPU, which comprises the following steps: establishing a mapping relation between a data register and a memory stack according to a preset mapping strategy; and simplifying stack access operation instructions according to the mapping relation between the data register and the memory stack, and performing data access operation according to the simplified operation instructions. After the mapping relation between the data register and the memory stack is established, it can be assumed that all temporary variables are on the stack, and the system can access the variables on the memory stack by directly accessing the register. By implementing the invention, a large number of stack access codes can be simplified while the data register is greatly increased, thereby effectively reducing the compiling complexity and difficulty and effectively improving the CPU performance.
Description
Technical Field
The invention relates to the technical field of compiling optimization, in particular to a method for optimizing register access in a CPU.
Background
Registers are a core component of the CPU, which is a high-speed memory unit used to temporarily store instructions, data, and addresses. The existence of the registers greatly quickens the calculation and memory access efficiency, so that theoretically, the larger the number of registers is, the better. The number of registers on the existing X86 architecture is more than ten, and the number of ARM is more than thirty, and the number of RISC-V is more than thirty. However, with the current state of the art, it is very difficult to further increase the number of registers, because too many registers increase instruction complexity, increase the compiling difficulty of the compiler, and thus decrease the system execution efficiency due to the increase of the code amount. Therefore, the prior art cannot effectively improve the system operation efficiency by increasing the number of registers.
Disclosure of Invention
The technical problem to be solved by the embodiment of the invention is to provide a method for optimizing register access in a CPU, which can avoid defects caused by adding registers when the number of the registers is greatly increased, so that the running efficiency of a system can be effectively improved by increasing the number of the registers.
In order to solve the above technical problems, an embodiment of the present invention provides a method for optimizing register access in a CPU, including:
establishing a mapping relation between a data register and a memory stack according to a preset mapping strategy;
and simplifying stack access operation instructions according to the mapping relation between the data register and the memory stack, and performing data access operation according to the simplified operation instructions.
Further, the method for optimizing register access in the CPU further comprises:
and setting a stack pointer according to the preset mapping strategy so that the system synchronously operates the memory stack and the data register when the stack pointer moves.
Further, the method for optimizing register access in the CPU further comprises:
and modifying the compiler according to the preset mapping strategy to adjust a register allocation scheme, a variable access mode and an assembly generation mode.
Further, the simplifying the stack access operation instruction according to the mapping relation between the data register and the memory stack, and performing the data access operation according to the simplified operation instruction, includes:
responding to stack access requirements of the variables, simplifying the stack access instructions of the variables according to the mapping relation between the data register and the memory stack, and performing data access operation on the variables according to the simplified operation instructions.
Further, the step of simplifying the stack access operation instruction according to the mapping relationship between the data register and the memory stack, and performing the data access operation according to the simplified operation instruction, further includes:
responding to the calling request of the subfunction, simplifying the stack access instruction of the subfunction according to the mapping relation between the data register and the memory stack, and performing data access operation on the variable according to the simplified operation instruction.
Further, the step of simplifying the stack access operation instruction according to the mapping relationship between the data register and the memory stack, and performing the data access operation according to the simplified operation instruction, further includes:
responding to the access request of the interrupt function, simplifying the stack access instruction of the interrupt function according to the mapping relation between the data register and the memory stack, and performing data access operation on the interrupt function according to the simplified operation instruction.
Further, the step of simplifying the stack access operation instruction according to the mapping relationship between the data register and the memory stack, and performing the data access operation according to the simplified operation instruction, further includes:
responding to the multithread switching request, simplifying the push-pull instruction of the thread switching according to the mapping relation between the data register and the memory stack, and performing the thread switching operation according to the simplified operation instruction.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a method for optimizing register access in a CPU, which comprises the following steps: establishing a mapping relation between a data register and a memory stack according to a preset mapping strategy; and simplifying stack access operation instructions according to the mapping relation between the data register and the memory stack, and performing data access operation according to the simplified operation instructions. After the mapping relation between the data register and the memory stack is established, it can be assumed that all temporary variables are on the stack, and the system can access the variables on the memory stack by directly accessing the register. By implementing the invention, a large number of stack access codes can be simplified while the data register is greatly increased, thereby effectively reducing the compiling complexity and difficulty and effectively improving the CPU performance.
Drawings
FIG. 1 is a flow chart of a method for optimizing register access in a CPU according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating an application of mapping a certain number of registers to a memory stack according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, an embodiment of the present invention provides a method for optimizing register access in a CPU, including:
step S1, establishing a mapping relation between a data register and a memory stack according to a preset mapping strategy;
and S2, simplifying stack access operation instructions according to the mapping relation between the data register and the memory stack, and performing data access operation according to the simplified operation instructions.
Compared with the prior art, after the mapping relation between the data register and the memory stack is established, the invention can assume that all temporary variables are on the stack, and the system can access the variables on the memory stack by directly accessing the register. By implementing the invention, a large number of stack access codes can be simplified while the data register is greatly increased, thereby effectively reducing the compiling complexity and difficulty and effectively improving the CPU performance.
Referring to fig. 2, the gist of the present invention is to map data registers with a memory stack. It will be appreciated that a data register refers to a register in the CPU that is used for data operations, and a memory stack refers to a piece of memory allocated to a program. The operating system allocates a piece of memory called a stack to an operating program (or thread), the bottom of which is the stack and the top of which is the stack (in small-end mode). The stack is mainly used for temporary storage of variables, and it grows downwards, that is, when a subroutine is called or more temporary variables are needed, an instruction generated by a compiler controls a stack pointer (SP register) to move downwards, and SP moves upwards when the subroutine is exited. The invention maps a certain number of registers to a memory stack, such as SP pointed to R0. In this illustration, there are 256 data registers at maximum, and in practical application, the number of registers may be increased or decreased according to specific requirements. These data registers are just like the stack caches, although there may be real data caches in between. When accessing the data register, the operations are equivalent to operating a memory stack, and the operations are automatically completed by hardware such as a CPU.
It will be appreciated that machine language is the most efficient language to execute and that the compiler that can be compiled into machine language is often a C/c++ compiler. In the C language, each subroutine has temporary variables such as dynamic variables in addition to functional variables. In the prior art, when the variables are few, the register representation can be directly used, and when the variables are more, some variables are temporarily stored on a stack, namely stack access. In fact, a large number of subroutine calls, complexity of functions, interrupts, multi-tasking, etc. all result in a large number of stack accesses. Since stack access requires a specific instruction, the occurrence of a large number of stack accesses causes an increase in the amount of code to be executed and time-consuming execution. After the mapping relation between the data register and the memory stack is established, the compiler can assume that all temporary variables are on the stack, and the variables on the stack can be accessed by directly accessing the register, so that a large number of stack access codes can be simplified, and the running performance of the system is effectively improved.
In the embodiment of the present invention, further, the method for optimizing register access in the CPU further includes:
and setting a stack pointer according to the preset mapping strategy so that the system synchronously operates the memory stack and the data register when the stack pointer moves.
In the embodiment of the present invention, further, according to the mapping relationship between the data register and the memory stack, the stack access operation instruction is reduced, and according to the reduced operation instruction, the method includes:
responding to stack access requirements of the variables, simplifying the stack access instructions of the variables according to the mapping relation between the data register and the memory stack, and performing data access operation on the variables according to the simplified operation instructions.
It will be appreciated that excessive variables, function calls, code blocking within functions may result in temporary variables being pushed or pulled. For the stack access operation, the compiler generates relevant instructions for processing, and in the prior art, the stack access instruction occupies a larger proportion.
For the push and pull of variables, the prior art is different from the present invention in that:
a) Stacking: when a common subfunction or code block is entered, the prior art will generate a push instruction, i.e., a variable to be saved is written from a register to the memory stack while the stack pointer is moved down. The present invention simply moves the stack pointer down. After the stack pointer has been moved down, R0 points to the new address, so it represents the new variable. If the stack pointer is shifted down by N, the original R0 is now denoted by RN. Stack pointer downshifting can result in the top registers, such as R255, being synchronized into memory, but this is hardware automated, with optimal performance, and the compiler does not need to take into account nor occupy CPU instruction cycles. The push operation of the present invention is therefore significantly better than the prior art.
b) And (5) pop-stacking: common subfunctions or code blocks exit, and the prior art adopts a pop instruction to restore the saved variables from the stack to the registers, and the stack pointer is also moved upwards. The present invention simply moves the stack pointer up. Stack pointer up-shifting requires synchronizing memory into the top registers, but this is a hardware automation operation. The pop operation of the present invention is also significantly better than the prior art.
In the embodiment of the present invention, further, according to the mapping relationship between the data register and the memory stack, the stack access operation instruction is simplified, and according to the simplified operation instruction, the method further includes:
responding to the calling request of the subfunction, simplifying the stack access instruction of the subfunction according to the mapping relation between the data register and the memory stack, and performing data access operation on the variable according to the simplified operation instruction.
When calling the sub-function, the parameter and the function return address are put on the stack. And calculating the occupation size of the return value stack. When the subfunction returns, the return value is written to the stack, and then the calling program is returned. Although the invention is similar to the prior art for the invocation and return of the subfunction, the performance of the invocation and return of the subfunction is still superior to the prior art due to the optimization of the egress stack.
In the embodiment of the present invention, further, according to the mapping relationship between the data register and the memory stack, the stack access operation instruction is simplified, and according to the simplified operation instruction, the method further includes:
responding to the access request of the interrupt function, simplifying the stack access instruction of the interrupt function according to the mapping relation between the data register and the memory stack, and performing data access operation on the interrupt function according to the simplified operation instruction.
It should be noted that, for the interrupt function entry, the prior art needs to push all data registers to the stack, and then set the stack pointer to be the interrupt stack top. The invention only needs to set the stack pointer, and the hardware automatically synchronizes the original data register into the stack memory of the current function in the setting process. The invention can also ensure that the interruption does not switch stacks, and ensure that the interruption function directly runs on the current stack, thereby having better performance.
For interrupt function exit, the prior art needs to restore all data registers, i.e., pop, and then return to the interrupt point. The invention only needs to restore the stack pointer, and the hardware automatically restores the original data register in the setting process. The present invention is significantly superior to the prior art when interrupting operation.
In the embodiment of the present invention, further, according to the mapping relationship between the data register and the memory stack, the stack access operation instruction is simplified, and according to the simplified operation instruction, the method further includes:
responding to the multithread switching request, simplifying the push-pull instruction of the thread switching according to the mapping relation between the data register and the memory stack, and performing the thread switching operation according to the simplified operation instruction.
In the operating system having multiple tasks, there is a frequent thread switch. Every time switching, all data registers of the original thread are saved, and all data registers of the new thread are restored. In the prior art, an explicit push instruction is still needed, but the related synchronization is automatically completed by hardware only by setting a push pointer. The present invention is significantly superior to the prior art in thread switch operations.
In the embodiment of the present invention, further, the method for optimizing register access in the CPU further includes:
and modifying the compiler according to the preset mapping strategy to adjust a register allocation scheme, a variable access mode and an assembly generation mode.
In a specific embodiment, embodiments of the present invention relate to modifications of the following aspects:
a) CPU: mainly stack pointer SP setting (taking small end as an example)
Sp move down instruction: the top N registers are synchronized into the memory stack (register- > memory) and then sp=sp-N.
Sp move up instruction: the memory stack is synchronized into the top N registers (memory- > registers), then sp=sp+n.
Sp set instruction: all registers are written into the original stack, SP new values are set, and the new stack is written into all registers.
b) Compiler modification: adjust register allocation schemes, variable access, assembly generation, etc.
c) Software modification: mainly modifying the bottom layer realization of interrupt, thread switch, etc.
It will be appreciated that the above-described modifications at multiple levels may be adapted by various professional developers (compiler developers, operating systems, or underlying software developers, etc.) according to mapping requirements.
In particular embodiments, the optimization may be done by, for example, in terms of the CPU:
a) The number N of actual data registers may be, but is not limited to, 256 in the present embodiment, and may be increased or decreased according to actual requirements.
b) The register uses a ring + index access mode, and R0 accessed in the instruction may be physical Rx. Physical R0 corresponds to R [ N-x ] in the instruction. By adopting the mode, data handling caused by SP movement can be reduced, so that the performance is improved.
c) One or more levels of cache are inserted between the registers and the memory to improve performance.
The following examples of some typical C language functions are attached to the translated related assembly language (like ARM assembly) to demonstrate the invention. In the following examples, there is indeed no explicit data-out-stack instruction, demonstrating the advantages of the present invention over the prior art.
First, regarding calling conventions:
a) When a function is called, sp is decremented by a value such that it points to the 0 th parameter to be entered, then the parameters are written in reverse order to the stack, finally pc (program counter) is stacked and transferred to the subfunction. If the number of bytes required by the parameter is less than the number of bytes required by the return value, sp minus the number of bytes required by the return value.
b) In the function, the function parameters can be used as local variables, i.e. the function can change the value of the real parameters of the function, the 0 th parameter is r1, and if the sp value changes, the sp value may become r n.
c) Each variable of the function is stored on the stack, and the corresponding value is subtracted from sp by using the number of the variables, so that the address of the variable is greater than or equal to sp, and accidents such as interruption and the like can be ensured not to rewrite the variables.
d) When the function returns, sp resumes, placing the first return value at r1, sp [1], then at r2, and finally, pc is popped off the stack, with pc pointing to the next instruction that calls the function.
1) The simplest function: loopDelay ()
2) Memory copy function: copy memory
3) Mathematical operation DoMath (a, b, c, d), return value (a+b): (c-d), followed by optimization code
Optimizing code:
while the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that changes and modifications may be made without departing from the principles of the invention, such changes and modifications are also intended to be within the scope of the invention.
Claims (3)
1. A method of optimizing register access in a CPU, comprising:
establishing a mapping relation between a data register and a memory stack according to a preset mapping strategy;
responding to stack access requirements of variables, simplifying stack access instructions of the variables according to the mapping relation between the data register and the memory stack, and performing data access operation on the variables according to simplified operation instructions;
responding to a calling request of the subfunction, simplifying a stack access instruction of the subfunction according to the mapping relation between the data register and the memory stack, and performing data access operation on the variable according to the simplified operation instruction;
responding to an access request of the interrupt function, simplifying a stack access instruction of the interrupt function according to the mapping relation between the data register and the memory stack, and performing data access operation on the interrupt function according to the simplified operation instruction;
responding to a multithread switching request, simplifying a push-pull instruction of thread switching according to the mapping relation between the data register and the memory stack, and performing thread switching operation according to the simplified operation instruction;
the method for simplifying each push instruction comprises the following steps: subtracting the part of the push instruction that indicates that the variable or function to be saved is written from the register to the memory stack and the part of the pop instruction that indicates that the saved variable or function is restored from the stack to the register.
2. The method of optimizing register access in a CPU of claim 1, further comprising:
and setting a stack pointer according to the preset mapping strategy so that the system synchronously operates the memory stack and the data register when the stack pointer moves.
3. The method of optimizing register access in a CPU of claim 1, further comprising:
and modifying the compiler according to the preset mapping strategy to adjust a register allocation scheme, a variable access mode and an assembly generation mode.
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| US7496734B1 (en) * | 2000-04-28 | 2009-02-24 | Stmicroelectronics, Inc. | System and method for handling register dependency in a stack-based pipelined processor |
| CN1504898A (en) * | 2002-11-29 | 2004-06-16 | 上海奇码数字信息有限公司 | Storing structure and addressing method for internal data and digital signal processor |
| CN1601462A (en) * | 2003-09-27 | 2005-03-30 | 英特尔公司 | Extended register space device of processor and method thereof |
| CN101286122A (en) * | 2008-05-22 | 2008-10-15 | 中国科学院计算技术研究所 | A RISC processor and its floating-point stack instruction translation device and method |
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