CN110526200B - Out-of-plane piezoresistive accelerometer chip with pure axial deformation sensitive beam and preparation method thereof - Google Patents

Abstract

The invention discloses an out-of-plane piezoresistive accelerometer chip with a pure axial deformation sensitive beam and a preparation method thereof. The chip includes two symmetrically arranged mass blocks, the outer end faces of the two mass blocks are respectively connected to an outer frame of the chip. The inner end face is connected by two sets of sensitive beams; the four sensitive beams form a Wheatstone full bridge circuit; the mass block is used to directly sense the acceleration signal outside the plane. When the chip is accelerated in the Z direction, the two mass blocks move synchronously, It also keeps synchronous motion with the sensitive beam to which it is fixed, so as to satisfy the pure axial deformation of the sensitive beam.

Description

An out-of-plane piezoresistive accelerometer chip with purely axial deformation-sensitive beam and the same Preparation

【Technical field】

The invention belongs to the field of micromechanical electronic sensor measurement, and in particular relates to an out-of-plane piezoresistive accelerometer chip with a purely axial deformation sensitive beam and a preparation method thereof.

【Background technique】

With the continuous development of micromachining technology, products based on MEMS technology are more and more widely used in daily life, and MEMS sensors are mainly due to their advantages of small size, light weight, low power consumption, high reliability, and easy integration. It has become the main force of micro sensors and is gradually replacing traditional mechanical sensors, and is widely used in consumer electronics, automotive industry, and even aerospace, machinery, chemical and pharmaceutical fields.

Compared with the strain gauge accelerometer, the working principle of the MEMS piezoresistive accelerometer is mainly different in the principle of resistance change: the shape of the metal wire or metal foil in the strain gauge changes when it is stressed, causing the resistance to change. When the silicon material is subjected to force, in addition to its shape change, the more important thing is that the material properties change, resulting in a large change in the resistance value.

The sensitivity and working bandwidth of the MEMS accelerometer are always its most important work indicators. The existing accelerometers have high lateral sensitivity due to structural design and process processing. The higher lateral sensitivity will affect the measurement accuracy of the sensor and reduce the reliability of the measurement results.

[Content of the invention]

The purpose of the present invention is to overcome the above-mentioned shortcomings of the prior art, and provide an out-of-plane piezoresistive accelerometer chip with a pure axial deformation sensitive beam and a preparation method thereof; the present invention can ensure the pure axial deformation of the sensitive beam, and simultaneously Through the structural design, the sensitivity of the sensor is improved, and the cross-sensitivity problem of the sensor is reduced.

To achieve the above object, the present invention adopts the following technical solutions to realize:

An out-of-plane piezoresistive accelerometer chip with a purely axial deformation-sensitive beam includes a mass block arranged inside the chip outer frame, the mass block including a first mass of the same structure and symmetrical with respect to the lateral centerline of the chip outer frame block and the second mass; the outer side of the first mass and the outer side of the second mass are fixedly connected to the outer frame of the chip through a support beam; the inner side of the first mass and the second mass are connected by a sensitive beam ;

The sensitive beam includes several first sensitive beams and several second sensitive beams, the first sensitive beams are arranged in the middle part of the two mass blocks, and the second sensitive beams are separately arranged on the side parts of the two mass blocks; The varistors on the beams are connected by metal leads to form a Wheatstone full bridge circuit.

Preferably, the support beam is arranged at the center line of the first mass block or the second mass block along the z direction, and the plane of the support beam is parallel to the plane of the chip outer frame.

Preferably, a serpentine beam is fixed on each support beam, the serpentine beam includes several serpentine units, one end of each serpentine unit is connected to the outer frame of the chip, and the other end is connected to the outer side of the first mass block. Or the outer side surface of the second mass block is fixedly connected; the serpentine unit is a plane circuitous structure.

Preferably, the serpentine beam includes two serpentine units, and the two serpentine units are symmetrically arranged with respect to the vertical center line of the chip outer frame.

Preferably, the serpentine unit includes a first plane and a second plane that are perpendicular to each other, the first plane is parallel to the short side of the outer frame of the chip, and the second plane is parallel to the long side of the outer frame of the chip; The two ends are respectively connected with a second plane.

Preferably, a protrusion and a groove are respectively provided on the inner sides of the first mass block and the second mass block, and the protrusions and grooves on each mass block are arranged adjacently; Placed in the groove of the second mass, the protrusion of the second mass is placed in the groove of the first mass; the protrusion of the first mass and the protrusion of the second mass pass through the four first Beam connection.

Preferably, two second sensitive beams are provided on the outer side of the protrusion of the first mass block, and two second sensitive beams are provided on the outer side of the protrusion of the second mass block; the second sensitive beams on both sides are opposite to the outside of the chip. The vertical centerline of the frame is symmetrical.

Preferably, the four first sensitive beams are symmetrical with respect to the vertical center line of the chip frame.

Preferably, the out-of-plane piezoresistive accelerometer chip is made of SOI silicon wafer.

A preparation method of the above-mentioned out-of-plane piezoresistive accelerometer chip with pure axial deformation sensitive beam, comprising the following steps:

1) Double-sided thermal oxidation is performed on the SOI silicon wafer, and a thermal oxide silicon dioxide layer is formed on the upper surface and the lower surface of the SOI silicon wafer, respectively, which are the thermal oxygen dioxide layer on the upper surface and the thermal oxygen dioxide layer on the lower surface. silicon layer;

2) Using a lightly doped version, the upper surface thermal oxide silicon dioxide layer in the lightly doped area on the upper surface of SOI is removed by photolithography and reactive ion etching, and after boron ions are doped in the lightly doped area, a light doped region;

3) Using a heavily doped version, remove the upper surface thermal oxide silicon dioxide layer in the heavily doped region by photolithography and reactive ion etching, and perform heavy doping in the heavily doped region to form an ohmic contact region;

4) The Ti/Al layer is deposited on the front of the SOI silicon wafer by physical vapor deposition, and photolithography is performed by metal pads and wire plates to form metal leads and pad structures;

5) a layer of silicon dioxide is deposited on the back of the lower surface thermal oxide silicon dioxide layer by vapor deposition, and the lower surface thermal oxide silicon dioxide layer and the silicon dioxide layer form a double mask layer;

6) Remove the double mask layer in the deep etched area on the back of the SOI silicon wafer by reactive ion etching, so that the substrate silicon in the deep etched area of the SOI silicon wafer is exposed; Etch off part of the lower part of the mass;

7) remove the double mask layer of the back etching area of the support beam and the serpentine beam by photolithography; continue to etch by the deep reactive ion etching method to form the base layer structure of the mass block and the lower part of the serpentine beam;

8) Perform a photoresist mask on the bottom glass plate by moving the gap layout, and perform wet etching by KOH to form an empty groove area on the bottom glass plate;

9) Etching the remaining double mask layer on the lower surface of the SOI silicon wafer by an ion etching method, so that the substrate silicon of the SOI silicon wafer is exposed; the substrate silicon region is encapsulated on the underlying glass plate by anodic bonding;

10) Etching and removing the thermal oxide silicon dioxide layer on the upper surface of the SOI silicon wafer by reactive ion etching, coating a layer of photoresist, and then etching until the buried oxygen layer stops by inductively coupled plasma etching to form a mass block The upper part of the ; the part of the device layer that forms the support beam and the serpentine beam;

11) Remove the buried oxygen layer in the upper area of the support beam by reactive ion etching, then etch away the buried oxygen layer in the upper area of the serpentine beam by reactive deep ion etching, and the upper part of the support beam and the serpentine beam are etched ;

12) Spray the photoresist on the front of the etched SOI silicon wafer for protection, remove the photoresist in the corresponding buried oxide layer area, and then use a buffer to etch the remaining buried oxygen layer on the front of the SOI silicon wafer, and clean the SOI silicon Dry the front side of the wafer naturally, and finally remove the photoresist on the front side of the SOI silicon wafer;

13) The SOI silicon wafer is processed by a low temperature annealing process, and the MEMS triaxial piezoresistive accelerometer chip with pure axial deformation is completed.

Compared with the prior art, the present invention has the following beneficial effects:

The invention discloses an out-of-plane piezoresistive accelerometer chip with a purely axial deformation-sensitive beam. The chip includes two symmetrically arranged mass blocks. The outer end faces of the two mass blocks are respectively connected with the outer frame of the chip, and the inner end face Connected by two sets of sensitive beams; the varistors on all sensitive beams are connected by metal leads to form a Wheatstone full bridge circuit; the sensitive beams are divided into two types, the first type is set in the middle position, and the second type is set at the side position , since the left and right mass blocks will move synchronously when subjected to the out-of-plane acceleration signal, the motion of the two types of sensitive beams at any time is the same, and because the sensitive beams are thin enough, the bending moment of the two mass blocks on the sensitive beams is as small as It can be ignored so that the sensitive beam always has the condition of pure axial deformation, so that the sensitive beam can be deformed along the axial direction of the sensitive beam without twisting in other directions, which can meet the requirements of sensor design performance and improve the measurement accuracy. and sensitivity; because the acceleration acts on the middle position of the chip, the first sensitive beam in the middle position is subjected to acceleration and produces tensile deformation, while the second sensitive beam at the edge is squeezed and squeezed inward. The deformation method is opposite. There are both tension-sensitive beams and compression-sensitive beams on the same structure, so that the varistors on the sensitive beams can form a Wheatstone full bridge and convert the sensed acceleration signals into corresponding Electrical signal output to improve the sensitivity of the sensor.

Further, the two support beams are arranged at the z-direction centerline of the mass block, which not only plays the role of connecting the mass block and the outer frame of the chip, but also makes the connection between the mass block and the outer frame of the chip when the mass block is accelerated. Even force.

Further, a circuitous serpentine beam structure is arranged on the support beam, which can lead out metal wires without increasing the rigidity of the support beam. The serpentine beam is a circuitous structure. When the chip is deformed by an acceleration perpendicular to the outer frame of the chip, because of the circuitous structure, The limiting force of the chip frame on the outside of the mass block is reduced, and the serpentine beam is arranged on the support beam, which ensures that the mass block and the chip frame can be firmly connected, thereby improving the sensitivity of the acceleration sensor and reducing the cross-sensitivity of the sensor at the same time. , to ensure the connection force between the mass block and the outer frame of the chip; the serpentine beam is provided with a plurality of serpentine units, which can ensure that the metal leads can be evenly distributed and drawn out.

Further, the two serpentine units are symmetrically arranged, so that the mass blocks and the sensitive beams on both sides of the vertical center line in the entire chip are uniformly stressed, and the motion of the mass blocks is synchronized, which meets the design performance requirements of the sensor.

Further, the inner sides of the two mass blocks are connected by a protrusion and groove matching structure, the two protrusions are connected by two first sensitive beams, and the outer ends of the inner sides of the two mass blocks are connected by two second sensitive beams. Connection, the first sensitive beam and the second sensitive beam are matched, the varistors on all sensitive beams are connected by metal leads to form a Wheatstone full bridge circuit, the fitting structure of protrusions and grooves, and the design of the position of the sensitive beams ( One group is in the middle and one group is outside), so that when the chip is subjected to an acceleration perpendicular to the outer frame of the chip, it is possible for the two types of sensitive beams to have opposite deformations.

Further, each type of sensitive beams is set to four, and they are symmetrical with respect to the vertical center line. The number of sensitive beams is set according to the resistance value of the sensitive beams. If the sensitive beams are too long, the natural frequency of the sensitive beams increases, but the sensitivity of the beams increases. However, if the sensitive beam is too short, the natural frequency will decrease; therefore, two second sensitive beams are set on each side here to improve the sensitivity while keeping the natural frequency unchanged; this method divides the sensitive beam into two, Even the one-to-many design not only improves the sensitivity, but also guarantees the natural frequency.

Further, the acceleration sensor chip is made of SOI silicon wafer, so that the size of each structure can be accurately and effectively controlled, and at the same time, the sensor chip has the advantages of low noise and high precision.

The invention also discloses a preparation method of an out-of-plane piezoresistive accelerometer chip with a pure axial deformation sensitive beam. The preparation method adopts the reactive ion etching method, plasma enhancement method in multiple steps according to the special structure of the chip. The chip is prepared by chemical vapor deposition method, deep reactive ion etching method and other methods; since the Z unit support beam is in the middle of the chip thickness direction (direction), it is very challenging for the processing of the MEMS process, the present invention adopts the back double mask Layer, deep reactive ion etching in two steps, etched grooves with different depths on the back, so that the lower half of the Z support beam and the lower half of the mass block, support beam and hinge beam are formed at the same time, and the front is etched first. The device layer is etched, the buried oxide layer is etched, and finally the base layer on the upper part of the support beam in the z-direction is etched to form the overall structure of the support beam.

【Description of drawings】

Fig. 1 is the overall structure schematic diagram of the present invention;

Fig. 2 is the detail enlarged view of A area of the present invention;

Fig. 3 is the enlarged view of B area detail of the present invention;

Fig. 4 is the working principle diagram of the present invention;

Fig. 5 is the partial force working diagram of the present invention;

6 is a Wheatstone full-bridge circuit diagram composed of the present invention;

Fig. 7 is the preparation flow structure schematic diagram of the present invention;

Among them, (a) picture shows step 1); (b) picture shows step 2); (c) picture shows step 3); (d) picture shows step 4); (e) picture shows step 5); (f) The picture shows step 6); (g) picture shows step 7); (h) picture shows step 8); (i) picture shows step 9); (j) picture shows step 10); (k) picture shows step 11) ; (1) figure is step 12);

Fig. 8 is the preparation process flow chart of the present invention;

Among them: 1-chip frame; 2-support beam; 3-mass block; 4-sensitive beam; 5-serpentine beam; 7-thermal silicon dioxide layer; 8-buried oxygen layer; 9-device layer; 10 -substrate silicon; 11-lightly doped region; 12-photoresist; 13-ohmic contact region; 14-metal lead; 15-pad structure; 16-silicon dioxide layer; 17-underlying glass plate; 18- Cr/Au layer; 19-empty groove area; 1-1-long side; 1-2-short side; 3-1-first mass; 3-2-second mass; 3-3-protrusion; 3-4-groove; 4-1-first sensitive beam; 4-2-second sensitive beam; 5-1-serpentine unit; 5-2-first plane; 5-3-second plane; 3 -3-1-first side; 3-3-2-second side; 3-3-3-third side; 3-3-4-common side; 3-4-1-first side wall;3 -4-2-The second side wall; 3-4-3-The third side wall; 7-1-The thermal oxy-silicon dioxide layer on the upper surface; 7-2-The thermal oxy-silicon dioxide layer on the lower surface.

【Detailed ways】

The present invention will be described in further detail below with reference to the accompanying drawings and specific steps.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific orientation or a specific orientation. construction and operation, and therefore should not be construed as limiting the invention; the terms "first", "second", "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance; furthermore, unless otherwise Clearly stipulated and defined, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection; it can be directly connected or indirectly connected through an intermediate medium, It can be a communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood in specific situations.

The invention discloses an out-of-plane piezoresistive accelerometer chip with a pure axial deformation sensitive beam and a preparation method thereof; the chip of the sensor is made of SOI (Silicon on Insulator) silicon wafer.

Referring to FIG. 1 , the chip includes two support beams 2 , two mass blocks 3 , a sensitive beam 4 , two serpentine beams 5 and a chip outer frame 1 ; the chip outer frame 1 is a rectangular frame-like structure, including two One long side 1-1 and two short sides 1-2, the two ends of each long side 1-1 are respectively connected with one short side 1-2, and finally a rectangular frame-like structure is formed, and the chip frame 1 is bonded by bonding The process is fixed on the bottom glass plate; in the coordinate system, O is the origin, the long side direction of the chip frame 1 is the X direction, and the short side direction of the chip frame 1 is the Y direction, then the entire chip is on the XY plane, The Z direction is perpendicular to the XY plane.

Referring to FIG. 2, the mass 3 includes a first mass 3-1 and a second mass 3-2; the first mass 3-1 and the second mass 3-2 are symmetrical with respect to the lateral centerline of the chip, and two The structure of the first mass block 3-1 is the same as that of the second mass block 3-2. Fixed connection, the other end is fixedly connected with the outer end of the first mass block 3-1 or the second mass block 3-2, the support beam 2 is a plane structure, and its plane is parallel to the XY plane, and the support beam 2 is arranged on the first mass At the Z-direction centerline of the block 3-1 or the second mass block 3-2; a serpentine beam 5 is fixedly arranged on each support beam 2, and the plane of the serpentine beam 5 is perpendicular to the plane of the support beam 2; One end of the beam 5 is connected to the outer edge of the first mass block 3-1 or the second mass block 3-2, and the other end is connected to the chip frame 1; the plane of the serpentine beam 5 is between the first mass block 3-1 and the Between the chip outer frame 1, or between the second mass block 3-2 and the chip outer frame 1, the serpentine beam 5 includes several serpentine units 5-1, and the serpentine units 5-1 are arranged in an array. Between the mass block and the chip frame 1, each serpentine unit 5-1 includes a first plane 5-2 and a second plane 5-3 that are perpendicular to each other, the first plane 5-2 is parallel to the short side 1-2, The second plane 5-3 is parallel to the long side 1-1, and the two ends of each first plane 5-2 are respectively connected with a second plane 5-3; the serpentine beam 5 is used to lead out wires without increasing the rigidity of the supporting beam , which can improve the sensitivity of the acceleration sensor and reduce the cross-sensitivity problem of the sensor.

Referring to FIG. 3 , the structure of the first mass block 3-1 or the second mass block 3-2 is the same, and the inner side of each mass block is provided with adjacent protrusions 3-3 and grooves 3-4, so The protrusion 3-3 is a rectangular structure, including a first side 3-3-1, a second side 3-3-2, a third side 3-3-3 and a common side 3-3-4 connected in sequence; the concave The groove 3-4 is a rectangular structure, and its shape is the same as that of the protrusion 3-3, but the length of each side is larger than the corresponding side of the protrusion 3-3, so that the protrusion 3-3 of the opposite mass block can prevent the In the groove, and there is a certain gap; the side wall of the groove 3-4 includes a common side 3-3-4, a first side wall 3-4-1, and a second side wall 3-4 connected in sequence -2 and the third side wall 3-4-3, the shared side 3-3-4 is the side wall shared by the protrusion 3-3 and the groove 3-4; one end of the first side 3-3-1 and the mass block (The first mass block 3-1 or the second mass block 3-2) is fixedly connected to the inner side, the other end is fixedly connected to the second side 3-3-2, and the other end of the second side 3-3-2 is connected to the second side 3-3-2. One end of the three sides 3-3-3 is fixedly connected, and the other end of the third side 3-3-3 is fixedly connected to the common side 3-3-4, wherein the first side 3-3-1 and the third side 3-3 -3 are both perpendicular to the inner side of the mass (the first mass 3-1 or the second mass 3-2), and both the second side 3-3-2 and the common side 3-3-4 are parallel to the mass ( The inner side surface of the first mass block 3-1 or the second mass block 3-2); one end of the common side surface 3-3-4 is fixedly connected with the third side surface 3-3-3, and the other end is connected with the first side wall 3- 4-1 Fixed connection, the other end of the first side wall 3-4-1 is fixedly connected to the second side wall 3-4-2, the other end of the second side wall 3-4-2 is fixed to the third side wall 3-4 -3 Fixed connection, the other end of the third side wall 3-4-3 is fixedly connected to the inner side of the mass block (the first mass block 3-1 or the second mass block 3-2); the first side wall 3-4 -1 and the third side wall 3-4-3 are both perpendicular to the inner side of the mass (the first mass 3-1 or the second mass 3-2), and the inner side of the second side wall 3-4-2 Parallel to the inner side of the mass (the first mass 3-1 or the second mass 3-2).

4 and 5, the first mass 3-1 and the second mass are symmetrically arranged in the chip frame 1, and the protrusion 3-3 of the first mass 3-1 is placed on the second mass 3-2 In the groove 3-4 of the second mass block 3-2, the protrusion 3-3 of the second mass block 3-2 is placed in the groove 3-4 of the first mass block 3-1; The common side surface 3-3-4 of 3 and the common side surface 3-3-4 of the protrusion 3-3 of the second mass block 3-2 are connected by four first sensitive beams 4-1; the two protrusions 3 The inner sides of the mass blocks on the outside of -3 are respectively connected by two second sensitive beams 4-2; four first sensitive beams 4-1 are a group, symmetrical with respect to the vertical center line of the chip frame 1, and four first sensitive beams 4-1 are a group. The second sensitive beams 4-2 are a group, symmetrical with respect to the vertical centerline of the chip frame 1; the distance between the two mass blocks is the length of the sensitive beams, which are used to directly sense the external acceleration signal; see FIG. 6 , the eight sensitive beams are distributed on the end of the inner side of the mass block, and the varistors on the sensitive beams form a Wheatstone full bridge circuit. When the resistance of four varistors on the eight sensitive beams decreases, the other four corresponding Raised, the sensed acceleration signal is converted into a corresponding electrical signal output. Due to the unique design of the end structure of the two mass blocks, it can be realized that when subjected to acceleration in the Z direction, the protrusions of the two mass blocks are downward relative to the plane at the same time, and the two protrusions share the side surfaces 3-3-4. The distance increases, so the two first sensitive beams 4-1 are subjected to tensile force; because the middle is indented, the distance between the outer sides of the two masses decreases, and the second sensitive beam 4-2 farther from the middle is compressed Therefore, on the same chip, there are both tension-sensitive beams and compression-sensitive beams, so that the sensed acceleration signals are converted into corresponding electrical signals for output.

The dimensions of this example are as follows:

The overall size of the sensor chip is: length × width × thickness = 6650 μm × 2200 μm × 510 μm;

The dimensions of the support beam 2 are: length×width×thickness=825μm×50μm×510μm;

Sensitive beam 4 size: length×width=70μm×5μm;

The size of the mass block 3 (the first mass block 3-1 or the second mass block 3-2) is: length×width×thickness=2730μm×1700μm×510μm;

The working principle of the sensor chip is as follows:

It can be obtained from Newton's second law F=ma, when the sensor chip is subjected to the out-of-plane acceleration a, the two mass blocks 3 in the sensor rotate slightly due to inertia, causing the deformation of the support beam 2, thereby causing the sensitive beam 4 According to the piezoresistive effect of silicon, the resistance value of the varistor on the sensitive beam 4 changes under the action of stress, and the relationship between its resistance change rate and the stress it is subjected to is as follows:

Among them: R is the initial resistance value of the varistor;

π is the piezoresistive coefficient of the varistor;

σ is the stress of the varistor;

ΔR is the resistance change of the varistor.

At the same time, the Wheatstone bridge composed of four varistors (that is, sensitive beams, of which the middle two are a group and the two sides are a group) will be out of balance due to different resistance changes, and the output will be out of balance with the external acceleration. a is proportional to the electrical signal, so as to realize the perception and measurement of acceleration. The relationship between the sensitivity S of the sensor and the out-of-plane acceleration a is as follows:

Where: U _out is the output voltage of the Wheatstone bridge;

E is the Young's modulus of silicon;

π is the piezoresistive coefficient;

U _apply is the supply voltage of the Wheatstone bridge;

ε is the strain of the piezoresistive microbeam;

π ₄₄ is the shear piezoresistive coefficient;

l is the length of the sensitive beam;

Δl--axial deformation of sensitive beam;

The technical indicators of the chip prepared in this embodiment are as follows:

Range: 0～100g;

Sensitivity: >1.5mV/g/3V;

Natural frequency: >11kHz;

Working temperature: -40℃～125℃.

Referring to Fig. 7 and Fig. 8, the letters in the block diagram in Fig. 8 represent the sequence in Fig. 7, and the preparation method of the chip of the present invention comprises the following steps:

1) Referring to (a) in FIG. 7 , select raw materials, and use N-type (100) crystal planes to polish SOI silicon wafers on both sides. The SOI silicon wafers include substrate silicon 10 and buried oxide layers 8 stacked sequentially from bottom to top. and device layer 9; the bottom glass plate 17 is made of BF33 glass; the SOI silicon wafer is cleaned, and double-sided thermal oxidation is performed at 900°C-1200°C to obtain a layer of thermal oxide silicon dioxide layer 7 on the upper and lower surfaces of the silicon wafer. , including the upper surface thermal oxide silicon dioxide layer 7-1 and the lower surface thermal oxide silicon dioxide layer 7-2, as the next lightly doped mask layer, while improving the uniformity of ion implantation.

2) Referring to (b) in FIG. 7, using a lightly doped version, the front side of the upper surface thermal oxide silicon dioxide layer 7-1 is patterned by the first photolithography, and the front side is removed using a reactive ion etching (RIE) process The thermal oxide silicon dioxide layer 7 in the lightly doped region 11 and the thermal oxide silicon dioxide layer 7 in the remaining regions serve as masks, and then lightly doped with boron ions to form the lightly doped region 11 in the device layer 9, so The lightly doped region 11 is the above-mentioned sensitive resistor, each sensitive resistor is fixed on a sensitive beam, and the sensitive resistors on all the sensitive beams are prepared through this step; then the redistributed well push diffusion annealing process is performed to ensure The impurity concentration in the entire SOI device layer 9 is uniformly distributed.

3) Referring to (c) in FIG. 7 , a layer of photoresist 12 is applied on the front side, in order to protect the lightly doped region 11 from being affected in the next heavily doped step; using the heavily doped version, The second photolithography and reactive ion etching (RIE) process realizes the patterning of the silicon dioxide layer and removes the upper surface thermal oxide silicon dioxide layer 7-1 and the photoresist 12 in the heavily doped area of the front side, and the remaining areas of the photoresist The resist 12 is used as a mask, and then heavily doped with boron ions to form a low-resistance ohmic contact region 13 in the device layer 9; a redistribution diffusion annealing process is performed, and then a redistribution diffusion annealing process is performed to make the sensitive resistance The impurity concentration of the ohmic contact region 13 is uniformly distributed to ensure stable contact between the metal lead 16 and the varistor on the sensitive beam in the next step.

4) Referring to (d) in Figure 7, a Ti/Al layer is fabricated on the entire front surface of the SOI silicon wafer by using physical vapor deposition (PVD) technology, and then a third lithography is performed using metal pads and wire plates. The metal layers in other regions outside the metal leads are removed by etching to form the metal leads 14 and the pad structure 15, and an alloying process is performed at a high temperature.

5) Referring to the figure (e) in FIG. 7, a layer of silicon dioxide layer 16 is formed on the backside of the SOI silicon wafer using a PECVD process, and the silicon dioxide layer 16 is arranged on the backside of the lower surface thermal oxide silicon dioxide layer 7-2, At the same time, the lower surface thermal oxide silicon dioxide layer 7-2 and the silicon dioxide layer 16 are combined as a double mask layer for the subsequent backside etching.

6) Referring to (f) in Figure 7, the backside is etched for the first time, and the fourth lithography is performed on the SOI silicon wafer lithography backside etching area, and the RIE process is used to remove the lower surface thermal oxygen in the backside deep etching area. The silicon dioxide layer 7-2 and the silicon dioxide layer 16, the thermal oxide silicon dioxide layer 7-2 and the silicon dioxide layer 16 on the lower surface of the remaining areas are used as masks; in the next etching step, in order to ensure the molding The supporting beam 2, hinge beam 3 and mass block 3 have good edge verticality and aspect ratio, and are etched using deep reactive ion etching technology (Deep Reactive Ion Etching, DRIE); through this step, the first mass is etched away Block 3-1 and part of the lower part of the second mass 3-2.

7) Referring to the figure (g) in Fig. 7, the back side is etched for the second time, and the fifth time is etched in the SOI silicon wafer lithography back side etching area, and the back side of the support beam 2 and the serpentine beam 5 in the measurement unit is removed. The thermal oxide silicon dioxide layer 7-2 and silicon dioxide layer 16 on the lower surface of the etched area are used as a mask layer, and the mask layer in the remaining area is used as a mask; the substrate silicon 10 is etched using the DRIE process to form support beams The lower part of 2, and the base layer structure of mass 3.

8) Referring to (h) in FIG. 7, using the motion gap layout, the sixth photolithography, photoresist masking is performed on the bottom glass plate 17, and KOH is used for wet etching to form an empty groove area 19 to ensure acceleration. The sensor can move normally in the working state; the empty groove area 19 is used to match the support beam, sensitive beam and mass block area in the acceleration chip; Cr/Au layer is sputtered on the empty groove area 19 in the bottom glass plate 17 18, to prevent electrostatic adsorption.

9) Referring to (i) in FIG. 7, the lower surface thermal silicon dioxide layer 7-2 and silicon dioxide layer 16 on the backside of the SOI silicon wafer as a mask are etched by the RIE process to expose the backside of the SOI silicon wafer The substrate silicon 10 in the chip is then encapsulated on the underlying glass plate 17 by anodic bonding.

10) Referring to (j) in FIG. 7, the seventh photolithography, using the first etching plate on the front, photoetches the frontal etching area, and uses a reactive ion etching (RIE) process to remove the upper surface in the frontal etching area. The surface thermal oxide silicon dioxide layer 7-1 is then coated with a layer of photoresist to protect the metal leads 14 and the pad structure 15, and is etched to the buried surface by using the Inductively Coupled Plasma (ICP) etching technology The oxygen layer 8 stops, forming the upper half of the sensitive beam 4 and all the masses, forming the supporting beam 2, and the device layer part of the serpentine beam 5.

11) Referring to (k) in Figure 7, the eighth photolithography, using the second etching plate on the front, photoetches the area of the front support beam 2, and uses a reactive ion etching (RIE) process to remove the support beam 2 area. The buried oxide layer 10 does not remove the photoresist, and plays the role of protecting the metal lead 14 and the pad structure 15 . In the next etching step, in order to ensure that the formed serpentine beam 7 has good edge verticality and aspect ratio, deep reactive ion etching (DRIE) is used to etch, and the The buried oxide layer 8 in the upper region of the serpentine beam 5; so far, the etching of the upper part of the support beam 2 and the serpentine beam 5 is completed.

12) Referring to the (1) figure in Figure 7, the front surface of the SOI silicon wafer that has been etched is sprayed with photoresist for protection, and then the tenth photoetching is used to remove the corresponding buried oxide layer 8 by the third etching plate on the front. Then, the buried oxygen layer 8 is etched from the front side by using buffer HF acid, rinsed with deionized water and acetone, and then dried naturally, and finally the photoresist on the front side is removed.

13) In order to further release and relieve the residual stress (including: mechanical stress, internal film stress, thermal stress, etc.) of the integrated sensor chip during processing, a low-temperature annealing process is used for processing.

The preparation of the out-of-plane piezoresistive accelerometer chip with pure axial deformation-sensitive beam ends.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the scope of the present invention. within the scope of protection.

Claims (8)

1. An out-of-plane piezoresistive accelerometer chip with a pure axial deformation-sensitive beam, characterized in that it comprises a mass block (3) arranged inside the chip outer frame (1), and the mass block (3) includes the same structure The first mass block (3-1) and the second mass block (3-2) are symmetrical with respect to the lateral centerline of the chip frame (1); the outer side of the first mass block (3-1) and the second mass The outer sides of the mass blocks (3-2) are respectively fixedly connected to the chip outer frame (1) through a support beam (2); the inner sides of the first mass block (3-1) and the second mass block (3-2) connected by sensitive beams (4); The sensitive beam (4) includes several first sensitive beams (4-1) and several second sensitive beams (4-2), and the first sensitive beams (4-1) are arranged in the middle part of the two mass blocks , the second sensitive beams (4-2) are separately arranged on the side portions of the two mass blocks; the varistors on the sensitive beams (4) are connected by metal leads to form a Wheatstone full bridge circuit; A protrusion (3-3) and a groove (3-4) are respectively provided on the inner sides of the first mass block (3-1) and the second mass block (3-2). The protrusion (3-3) and the groove (3-4) of the first mass block (3-1) are arranged adjacent to each other; In the groove (3-4), the protrusion (3-3) of the second mass (3-2) is placed in the groove (3-4) of the first mass (3-1); the first mass The protrusion (3-3) of (3-1) and the protrusion (3-3) of the second mass (3-2) are connected by four first sensitive beams (4-1); Two second sensitive beams (4-2) are arranged on the outer side of the protrusion (3-3) of the first mass block (3-1), and the protrusion (3-3) of the second mass block (3-2) Two second sensitive beams (4-2) are arranged on the outer side of the chip; the second sensitive beams (4-2) on both sides are symmetrical with respect to the vertical center line of the chip outer frame (1). 2. An out-of-plane piezoresistive accelerometer chip with purely axial deformation-sensitive beams according to claim 1, characterized in that, the support beams (2) are arranged on the first mass block (3-1) Or at the Z-direction centerline of the second mass block (3-2); one end of the support beam (2) is fixedly connected to the chip frame (1), and the other end is connected to the first mass block (3-1) or the second mass The outer ends of the blocks (3-2) are fixedly connected, and the support beam (2) is a plane structure; the plane of the support beam (2) is parallel to the plane of the chip outer frame (1); The whole chip is on the XY plane, and the Z direction is perpendicular to the XY plane. 3. An out-of-plane piezoresistive accelerometer chip with a purely axial deformation-sensitive beam according to claim 2, wherein a serpentine beam (5) is fixedly arranged on each support beam (2), The serpentine beam (5) includes several serpentine units (5-1), one end of each serpentine unit (5-1) is connected to the chip frame (1), and the other end is connected to the first mass (3) -1) The outer side surface or the outer side surface of the second mass (3-2) is fixedly connected; the serpentine unit (5-1) is a plane circuitous structure. 4. An out-of-plane piezoresistive accelerometer chip with a purely axial deformation-sensitive beam according to claim 3, wherein the serpentine beam (5) comprises two serpentine units (5-1 ), the two serpentine units (5-1) are symmetrically arranged with respect to the vertical center line of the chip outer frame (1). 5. The out-of-plane piezoresistive accelerometer chip with purely axial deformation-sensitive beams according to claim 3, wherein the serpentine unit (5-1) comprises mutually perpendicular first planes ( 5-2) and the second plane (5-3), the first plane (5-2) is parallel to the short side (1-2) of the chip frame (1), and the second plane (5-3) is parallel to the chip The long side (1-1) of the outer frame (1); the two ends of each first plane (5-2) are respectively connected with a second plane (5-3). 6. An out-of-plane piezoresistive accelerometer chip with purely axial deformation sensitive beams according to claim 1, wherein the four first sensitive beams (4-1) are relative to the chip outer frame (1). ) is symmetrical to the vertical centerline. 7 . The out-of-plane piezoresistive accelerometer chip with purely axial deformation-sensitive beam according to claim 1 , wherein the out-of-plane piezoresistive accelerometer chip is made of SOI silicon wafer. 8 . 8. The method for preparing an out-of-plane piezoresistive accelerometer chip with a purely axial deformation-sensitive beam according to claim 3, wherein the method comprises the following steps: 1) Double-sided thermal oxidation is performed on the SOI silicon wafer, and a thermal oxide silicon dioxide layer (7) is formed on the upper surface and the lower surface of the SOI silicon wafer respectively, which are respectively the upper surface thermal oxide silicon dioxide layer (7-1). ) and the lower surface thermal oxide silicon dioxide layer (7-2); 2) Using a lightly doped version, the upper surface thermal oxide silicon dioxide layer (7-1) in the lightly doped region on the upper surface of the SOI silicon wafer is removed by photolithography and reactive ion etching, and doped in the lightly doped region. After the doped boron ions, a lightly doped region (11) is formed; 3) Using a heavily doped version, the upper surface thermal oxide silicon dioxide layer (7-1) in the heavily doped region is removed by photolithography and reactive ion etching, and the heavily doped region is heavily doped to form ohmic contact area (13); 4) depositing a Ti/Al layer on the front of the SOI silicon wafer by a physical vapor deposition method, and performing photolithography through a metal pad and a wire plate to form a metal lead (14) and a pad structure (15); 5) deposit a layer of silicon dioxide (16) by vapor deposition on the back of the lower surface thermal oxide silicon dioxide layer (7-2), the lower surface thermal oxide silicon dioxide layer (7-2) and the silicon dioxide layer (16) forming a double mask layer; 6) Removing the double mask layer in the deep etching area on the back of the SOI silicon wafer by reactive ion etching, so that the substrate silicon (10) in the deep etching area of the SOI silicon wafer is exposed; etching the substrate by deep reactive ion etching Silicon (10), etched away a part of the lower part of the mass (3); 7) Remove the double mask layer of the back etching area of the support beam (2) and the serpentine beam (5) by photolithography; continue to etch by the deep reactive ion etching method to form the base layer structure of the mass block (3), the lower part of the serpentine beam (5); 8) performing a photoresist mask on the bottom glass plate (17) by moving the gap layout, and performing wet etching by KOH to form an empty groove region (19) on the bottom glass plate (17); 9) Etch the remaining double mask layer on the lower surface of the SOI silicon wafer by an ion etching method, so that the substrate silicon (10) of the SOI silicon wafer is exposed; the substrate silicon (10) area is encapsulated in the anodic bonding on the bottom glass plate (17); 10) Etching and removing the thermal oxide silicon dioxide layer (7-1) on the upper surface of the SOI silicon wafer by reactive ion etching, coating a layer of photoresist, and then etching to the buried oxygen layer by inductively coupled plasma etching (8) stop, form the upper part of the mass (3); form the device layer part of the support beam (2) and the serpentine beam (5); 11) removing the buried oxide layer (8) in the upper region of the support beam (2) by reactive ion etching, and then etching the buried oxide layer (8) in the upper region of the serpentine beam (5) by reactive deep ion etching, The upper parts of the support beam (2) and the serpentine beam (5) are etched; 12) Spray the photoresist on the front side of the SOI silicon wafer that has been etched for protection, remove the photoresist in the area of the corresponding buried oxygen layer (8), and then use the buffer to etch the remaining buried oxygen layer on the front surface of the SOI silicon wafer ( 8), clean the front of the SOI silicon wafer and dry it naturally, and finally remove the photoresist on the front of the SOI silicon wafer; 13) The SOI silicon wafer is processed by a low temperature annealing process, and the MEMS triaxial piezoresistive accelerometer chip with pure axial deformation is completed.

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