CN110518818A - CRM decompression-flyback pfc converter of fixed-frequency control - Google Patents

Abstract

The invention provides a CRM step-down-flyback PFC converter adopting constant frequency control, comprising a main power circuit, an input voltage digital feedforward circuit, an output voltage differential circuit, a feedback circuit, a state judgment circuit, a drive signal generation circuit, Comparing and multiplying circuits. The present invention introduces an input voltage digital feedforward circuit, an input voltage comparison circuit and a gating circuit to realize a double-fixed-frequency control mode, so that the switching frequencies of the switching tubes of the converter in the Buck stage and the Flyback stage are kept at different constant values respectively.

Description

CRM Buck-Flyback PFC Converter with Fixed Frequency Control

technical field

The invention relates to an AC/DC converter technology, in particular to a constant frequency controlled CRM step-down-flyback PFC converter.

Background technique

Due to problems such as input current dead zone and switching tube floating ground, it is difficult for the traditional BuckPFC converter to meet the design technical requirements in many applications. In order to solve these problems, someone proposed a buck-flyback PFC converter, which combines the Buck topology with the Flyback topology. When the input voltage is greater than the output voltage, the Buck topology works. When the input voltage is lower than the output voltage, the Flyback Topology works. However, the traditional CRM buck-flyback PFC converter adopts constant on-time control. When the two topologies of the converter work, the on-time is equal, so that the switching frequency of the switching tube in the second half of the power frequency cycle of this control mode The variation range is large and the power factor is low in the low-voltage range, which makes it difficult to meet the performance requirements.

The traditional CRM buck-flyback PFC converter has the same switch conduction time in each switching cycle. The advantages are simple control, high power factor in the high-voltage range, and no reverse recovery problem for diodes; the disadvantages are that the switching frequency of the switch tube has a large range of switching frequency within half a power cycle, low power factor in the low-voltage range, complex EMI design, and low efficiency.

Contents of the invention

The object of the present invention is to provide a CRM buck-flyback PFC converter with constant frequency control.

The technical solution for realizing the object of the present invention is: a CRM step-down-flyback PFC converter controlled by a fixed frequency, including a main power circuit and a control circuit, and the main power circuit includes an input power supply v _in , an EMI filter, a rectifier Diodes D ₁ -D ₆ , main circuit primary side inductance L _p , main circuit secondary transformer inductance L _s , zero-crossing detection inductance L _ZCD , switching tube Q _b and switching tube Q _b/b , freewheeling diode D _o , output Capacitor C _o , load R _L ; input voltage source v _in is connected to the input port of the EMI filter, the output port of the EMI filter and the rectifier bridge composed of rectifier diodes D ₁ -D ₄ and the rectifier bridge composed of D ₃ -D ₆ The input port is connected, the anodes of the rectifier diodes D ₃ and D ₄ are the reference potential zero point, the cathodes of the rectifier diodes D ₅ and D ₆ are connected to the primary inductance L _p of the main circuit, and the other end of the primary inductance L _p of the main circuit is connected to the switching tube Q _f One end of the rectifier diode D ₁ and D ₂ is connected to the negative pole of the secondary inductance L _s of the main circuit and connected to the negative pole of the freewheeling diode D _o , and the secondary inductance L _s of the main circuit is connected to the positive pole of the output capacitor C _o and the load RL , the negative pole of the output capacitor C _o and the load RL are connected to one end of Q _b of the switch tube together with the freewheeling diode D _o , the zero-crossing detection inductance L _ZCD is coupled with the main circuit inductance Lp and L _s , and the zero-crossing detection inductance L _ZCD One end of the current sampling resistor R s is connected to the reference potential zero point and the other end is connected to the current limiting resistor R _ZCD , one end of the current sampling resistor R _s is grounded and the other end is connected to the switch tube Q _f and the switch tube Q _b .

Further, the control circuit includes a main control chip, a sampling circuit, a digital-to-analog conversion circuit, an output voltage differential circuit, a feedback circuit, a state judgment circuit, a drive signal generation circuit, a comparison circuit and a multiplication circuit; the positive input terminal of the output voltage differential circuit It is connected with the positive pole V _o + of the output voltage of the main circuit, the negative input terminal of the output voltage differential circuit is connected with the positive pole V _o - of the output voltage of the main circuit, the output terminal of the output voltage differential circuit is connected with the first input terminal of the sampling circuit and the feedback The input terminal K of the circuit is connected, the second input terminal of the sampling circuit is connected with the rectified voltage v _g of the main circuit, the first output terminal of the sampling circuit is connected with the ADC2 port of the main control chip, and the second output terminal of the sampling circuit is connected with the main circuit The ADC1 port of the control chip is connected, the first output port of the main control chip is connected with the input port of the digital-to-analog conversion circuit, the output port of the digital-to-analog conversion circuit is connected with the input terminal _vx of the multiplier, and the output port of the feedback circuit is connected with the multiplier The input terminal v _y of the multiplier is connected, the output terminal of the multiplier is connected with the positive input terminal of the comparison circuit, the negative input terminal of the comparison circuit is connected with the main circuit v _Rs , and the output terminal of the comparison circuit is connected with the input terminal of the driving signal generating circuit , the input end of the driving signal generation circuit is connected to the zero-crossing detection winding L _ZCD of the main circuit through the current limiting resistor R _ZCD , the output end of the driving signal generation circuit is connected to the input end of the state judgment circuit, and the end of the driving signal generation circuit is connected to the main power circuit The switching tube Q _b of the drive signal generating circuit is connected to the switching tube Q _f of the main power circuit.

Further, the sampling circuit converts the input voltage v _g and the output voltage V _o of the converter into voltages v _{g_dsp} and V _{o_dsp} that can be collected by the control chip; the main control chip includes a phase-locking program, input voltage peak sampling Program, output voltage sampling program and control program, v _{g_dsp} is connected to the ADC1 interface of the control chip, and the value after sampling is given to the phase-locking program and input voltage peak sampling program, V _{o_dsp} is connected to the ADC2 interface of the control chip, after sampling The value of the output voltage sampling program is given to the output voltage sampling program, the output of the phase-locking program, the input voltage peak sampling program and the output voltage sampling program are given to the main control program, and the main control program calculates the value of the contour of the inductor current; the digital-to-analog conversion circuit The input end is connected with the control chip through the SPI protocol, which converts the value of the contour of the inductor current received into a voltage output.

Further, the state judging circuit includes a first comparator _Comp1 , resistors _R5 , R6, a reference voltage source V _boundary , two AND gates, a NOT gate and a drive circuit; the non-inverting input of the first comparator Comp1 terminal is connected to the rectified voltage v _g of the diode rectification circuit of the main power circuit (1) through voltage dividing resistors R ₅ and R ₆ , the inverting input terminal of the first comparator Comp1 is connected to the reference voltage source V _boundary , and the first comparator The output terminal of the device Comp1 is connected with an input terminal of the first AND gate AND Gate1 and the input terminal of the NOT gate, the output terminal of the NOT gate is connected with an input terminal of the second AND gate AND Gate2, and the output terminals of the two AND gates are connected with The input end of the driving circuit is connected, and the output end of the driving circuit is respectively connected to two switch tubes Q _b and Q _f of the main power circuit.

Further, the driving signal generating circuit can adopt L6561 or L6562 integrated IC circuit, the amplifiers used in the output voltage differential sampling circuit and the output voltage feedback circuit use TL074, TL072, LM358, LM324 and other operational amplifiers, and the multiplier adopts integrated Composed of IC circuits or discrete devices, the AND gates used in the state judgment circuit use SN74HC08N, CD4011BE or 74HC32N logic chips, and the drive circuits can use IR2110, TLP2590 and other types of drive chips or totem pole drive circuits, and the control chip can be selected Chips such as TMS320F28335 or TMS320F28377.

Compared with the prior art, the present invention has the following advantages: (1) when using constant switching frequency control, the switching frequency of the two topological switching tubes in half a power frequency cycle remains constant; (2) compared with constant switching frequency control Because the traditional constant on-time is controlled in the low-voltage range, the PF is significantly improved; (3) The effective value of the inductor current is greatly reduced under the new control mode, so that the efficiency of the entire converter is greatly improved; (4) The constant The output voltage ripple under the switching frequency control is much smaller than that under the traditional constant on-time control.

The present invention will be further described below in conjunction with the accompanying drawings.

Description of drawings

Figure 1 is a schematic diagram of the main circuit of a CRM buck-flyback PFC converter.

Figure 2 is a waveform diagram of the inductor current and switch tube current of a CRM buck-flyback PFC converter within a switching cycle.

Figure 3 is a waveform diagram of the input current under conventional control.

Figure 4 is a diagram of switching frequency variation under traditional control.

Fig. 5 is a schematic diagram of PF variation curve under traditional control.

Fig. 6 is a schematic diagram of PF variation curve under constant switching frequency control at different turn ratios.

Fig. 7 is a schematic diagram of switching frequency change curves under two kinds of control.

Fig. 8 is a schematic diagram of PF variation curves under two kinds of controls.

Fig. 9 is a schematic diagram of input current harmonic curves under two kinds of controls.

Fig. 10 is a schematic diagram of the RMS curves of the primary and secondary currents of the inductor under two kinds of control.

Fig. 11 is a schematic diagram of the change curve of the output voltage ripple under two kinds of control.

Fig. 12 is a combined schematic diagram of the main power circuit and the control circuit of the CRM buck-flyback PFC converter controlled by fixed frequency.

The main symbol names in the above figure: v _in —power supply voltage, i _in —input current, RB—rectifier bridge, v _g —output voltage after rectification, i _L —inductor current, L—inductance, Q _b —Q _{b/ b} —switch tube, D _fw —D _sk —diode, C _o —output filter capacitor, R _L —load, V _o —output voltage, R _{s_b/b} —R _{s_b/b —sampling} resistor, V _ref —output voltage feedback Controlled reference voltage, v _EA — error voltage signal output of output voltage feedback control, t — time, ω — input voltage angular frequency, V _m — input voltage peak value, v _{gs_b} — driving voltage of switching tube Q _b , v _{gs_b/ b} —driving voltage of switch tube Q _b/b , T _s —converter switching period, f _s —converter switching frequency, PF—power factor, I _{L_pk} —inductor current peak value, I _{in_rms} —input current effective value, t _on —converter turn-on time, t _off —converter turn-off time, i _in —input current, P _in —input power, ΔV _o —output voltage ripple.

Detailed ways

Figure 1 is the main circuit of the Buck-FlybackPFC converter.

The following assumptions are made: (1) All devices are ideal; (2) The output voltage ripple is small compared to its DC value; (3) The switching frequency is much higher than the input voltage frequency.

Figure 2 shows the switching tube current and inductor current waveforms in one switching cycle when the inductor current is critically continuous, where Figure 2(a) is the waveform diagram when the Buck topology is working, and Figure 2(b) is the waveform diagram when the Flyback topology is working . When the input voltage v _g is less than the output voltage V _o , the Flyback topology works, Q _b is off, when Q _f is on, D _o is off, the voltage across the inductor L _p is v _g , and its current i _Lp starts from zero and starts at v The slope of _g /L _p rises linearly, and the output filter capacitor C _o supplies power to the load; when Q _f is turned off, according to the ampere-turn conservation i _Ls continues to flow through D _o , and the voltage at both ends of L _s is -V _o , i _Ls falls with the slope of V _o /L _s , and i _Ls can drop to zero at the beginning of a new cycle. When the input voltage v _g is greater than the output voltage V _o , the Buck topology works, Q _f is off, when Q _b is on, D _fw is off, the voltage across the inductor L _s is v _g -V _o , and its current i _{Ls changes} from zero It begins to rise linearly with the slope of (v _g -V _o )/L _s , and v _g supplies power to the output filter capacitor C _o and the load; when Q _b is turned off, i _Ls continues to flow through D _o , and at this time the voltage at both ends of L _s The voltage is -V _o , i _Ls falls with the slope of V _o /L, and i _Ls can drop to zero at the beginning of a new cycle.

Without loss of generality, the expression of v _in defining the input AC voltage is

v _in = V _m sin ωt (1)

Where V _m and ω are the amplitude and angular frequency of the input AC voltage, respectively.

Then the voltage after the input voltage is rectified by the rectifier bridge becomes

v _g ＝V _m |sinωt| (2)

In half a power frequency cycle, the converter is divided into two working stages: Buck topology work and Flyback topology work. When the rectified input voltage v _g is greater than the output voltage V _o , the Buck topology works. If it is assumed that the on-time of the switch in the Buck topology is t _{on_buck} , when the switch is turned on, the input voltage v _g supplies power to the inductor, output capacitor and load, then the peak value of the secondary inductor current i _{Ls_pk_buck} in a switching cycle in the Buck mode can be obtained The expression is as follows:

Among them, V _o is the output voltage, and L _s is the inductance value of the secondary side.

When the switching tube turns off the freewheeling of the inductor, the expression of the off-time t _{off_buck} can be obtained according to the principle of volt-second balance:

According to formula (4), the expression of the switching frequency in the Buck stage can be obtained:

According to Equation (3) and Equation (5), it can be obtained that the average value of the current flowing through the inductor in one switching cycle when the Buck topology is working is

When the input voltage v _g is less than the output voltage V _o , the Flyback topology works. If it is assumed that the turn-on time of the Flyback topology switch is t _{on_flyback} , when the switch is turned on, the input voltage v _g supplies power to the primary inductor, and the peak value i _{Lp_pk_flyback} of the primary inductor current within one switching cycle can be expressed as follows

Where _Lp is the inductance value of the primary side.

When the switching tube is turned off, the secondary inductance L _s freewheels, and the inductance supplies power to the capacitor and the load. According to the principle of ampere-turn conservation and volt-second balance, the expressions of the peak value i _{Ls_pk} of the secondary inductance and the off-time t _{off_flyback} can be obtained:

i _{Ls_pk} (ωt) = ni _{Lp_pk} (ωt) (8)

in

According to formula (9), the expression of the switching frequency of the Flyback stage can be obtained:

According to formula (7) and formula (10), it can be obtained that the average value of the input current flowing through the Flyback topology in one switching cycle is

Since the Flyback topology works in the dead zone where the Buck circuit cannot work, the converter does not have a dead zone in the entire power frequency cycle. From the above derivation, the input current i _in can be obtained as:

in

According to formula (6) and formula (11), the expression of switching frequency in half power frequency cycle can be obtained:

When the on-time is the same and constant within the two operating phases, that is

t _on =t _{on_buck} =t _{on_flyback} (14)

According to the formula (13), the waveform of the input current within half a power frequency period can be drawn under different input voltages, as shown in Figure 3; according to the formula (14), the half power frequency cycle can be drawn under different input voltages. The change waveform of the switching frequency of the switching tube in the frequency cycle is shown in Figure 4. It can be seen from Figure 3 that although the Flyback converter compensates for the dead zone of the input current of the Buck converter in the low-voltage range, the waveform of the input current is far from sinusoidal at this time, and there are many harmonics. It can be seen from Figure 4 that the switching frequency of the switching tubes of the constant on-time control method Buck topology and Flyback topology has a large range of variation within half the power frequency cycle, which is not conducive to the design of EMI.

Assuming that the efficiency of the converter is 100%, that is, the input power is equal to the output power, according to the power balance, it can be obtained

According to formula (16), the expression of traditional control constant on-time can be obtained:

According to the above formula, the expression of PF is obtained as

According to formula (18), the PF curve under traditional control can be made, as shown in Figure 5. It can be seen from the figure that the PF value increases with the increase of the input voltage. In the low voltage range, the PF value is low, and when the input voltage is 90V, the PF value is only 0.888.

From the above inferences, it can be seen that under traditional control, the switching frequency range of switching tubes, whether it is Buck topology or Flyback topology, is relatively large, which is not conducive to the design of EMI. The idea of the constant switching frequency control strategy is to make the switching frequency of the switching tubes of the Buck topology and the Flyback topology constant and equal within half the power frequency cycle, that is,

According to formula (18), the expressions of the conduction time of the Buck topology and the Flyback topology switch tube in half the power frequency cycle can be obtained respectively:

According to Equation (7), Equation (12), Equation (21) and Equation (22), the expression of input current in half power frequency cycle can be obtained:

2.2 Optimal turns ratio selection

Assuming that the output power of the converter is P _o and the efficiency of the converter is 100%, according to the principle of power balance:

According to formula (24) can get the expression of K.

According to formula (22), the expression of PF under double fixed frequency can be written

According to formula (24), the power factor curves of the CRM Buck-Flyback PFC converter controlled by constant switching frequency under different turn ratios can be drawn, as shown in Figure 6. It can be seen from the figure that when the turn ratio n=2, the PF curve of the converter is the highest, and the converter can obtain the optimal power factor.

From the above analysis, it can be known that to keep the switching frequency of the converter constant during the switching period, it is only necessary to make the on-time t _{on_buck} and t _{on_flyback} of the converter work in Buck mode and Flyback mode according to formula (19) and formula (20) changes, but formula (19) and formula (20) are functions about V _o , V _m , L and _Po , and there are many independent variables of the function. If an analog circuit is used to build a control circuit, then the feedforward control circuit will be very complicated. This design adopts digital feed-forward circuit control. The parameters such as input voltage peak value V _m and output voltage V _o are sampled into the control chip through the sampling circuit. Through the calculation function of the control chip, the peak envelope curve of the inductor current is calculated. Through The digital-to-analog conversion circuit outputs to the drive generating circuit. The control circuit is shown in Figure 12.

The above-mentioned driving signal generation circuit can adopt integrated IC circuits of models such as L6561 or L6562, and the amplifiers used in the output voltage differential sampling circuit (4) and the output voltage feedback circuit (6) are selected from models such as TL074, TL072, LM358, and LM324. The multiplier (10) is made up of integrated IC circuits or discrete devices, the AND gates used in the state judgment circuit (7) and the drive signal generation circuit (8) are logic chips such as SN74HC08N, CD4011BE or 74HC32N, and the drive circuit can be selected from IR2110 , TLP2590 and other types of driver chips or totem pole driver circuits, the control chip can choose TMS320F28335 or TMS320F28377 and other chips.

It can be seen from formula (18) that under different input voltage levels, the switching frequency of the two topological switching tubes remains constant within half a power frequency cycle when using constant switching frequency control. Compared with traditional control, the switching frequency range of the two switching tubes is much reduced, which simplifies the design of EMI. Figure 7 shows the switching frequency waveforms of different control modes in the power frequency cycle under 110VAC and 220VAC.

According to formula (24) and formula (17), the PF value change curves of traditional control and new control can be drawn respectively, as shown in Figure 8. It can be seen from the figure that compared with the traditional constant on-time control in the low voltage range, the PF of the constant switching frequency control is significantly improved; in the high voltage range, the PF of the constant switching frequency control has a certain decrease, but compared with the The minimum PF of constant on-time is "0.88", and the PF under constant switching frequency control can be kept above 0.91, so the PF of constant switching frequency is significantly improved compared with the traditional control PF.

In order to analyze the harmonics of the input current, Fourier analysis can be performed on formula (21). The Fourier decomposition form of the input current is:

in

Where T _line is the power frequency cycle.

Substituting formula (21) into formula (26), the harmonics contained in the input current under constant switching frequency control can be obtained through calculation. Among them, both the cosine component and the even-order sine component are 0.

From equation (21) and equation (26), the 3rd, 5th, and 7th harmonic current amplitudes I ₃ , I ₅ , and I ₇ of the constant switching frequency control and the traditional constant on-time control can be obtained against the fundamental current amplitude I per unit value of ₁ As shown in Figure 9.

According to IEC61000-3-2, Class D standard requirements, the ratio of input current 3rd, 5th, 7th, 9th harmonics to input power should satisfy formula (27)

It can be seen from Figure 9 that under any input voltage, the 3rd, 5th, and 7th harmonics are all lower than the limit value of IEC61000-3-2, ClassD standard.

From Equation (3), Equation (4), Equation (7) and Equation (9), the square of the effective value of the primary side inductance current and the auxiliary transformer inductance current in Buck mode and Flyback mode in a switching cycle can be obtained as

Calculate the root mean square of the above formula in half the power frequency cycle to get the effective value of the primary side and auxiliary transformer inductor current

Substituting Equation (16), Equation (19) and Equation (20) into the above equation, the effective value change curve of the inductor current under the traditional control mode and the constant switching frequency control can be obtained, as shown in Figure 10. It can be seen from the figure that the RMS value of the inductor current drops significantly under the new control mode, which greatly improves the efficiency of the entire converter.

According to the calculation formula of instantaneous input power per unit value

Substituting formula (12) into the above formula, the instantaneous input power per unit value p ^* _{in_cot} under traditional control can be obtained; substituting formula (21) into the above formula can obtain the instantaneous input power per unit value p ^* _{in_dcf} under constant switching frequency control .

when When , the energy storage capacitor C _o is charged; when , C _o discharges. Assuming that starting from ωt=0, the constant on-time control and variable on-time control The time axis coordinates corresponding to the intersection points of the waveform of 1 and 1 are t ₁ and t ₂ respectively, then the maximum energy per unit value stored in the energy storage capacitor C _o in half a power frequency cycle (the reference value is output energy) are

According to the calculation formula of capacitor energy storage, and can also be expressed as

Among them, ΔV _{o_1} and ΔV _{o_2} are the output voltage ripple values under constant on-time and constant switching frequency control respectively.

Figure 8 can be drawn from formula (36) and formula (37). It can be seen from the figure that the output voltage ripple under constant switching frequency control is much smaller than that under the traditional constant on-time control. When the input When the voltage is 264VAC, the constant switching frequency control output voltage ripple is only 46.5% of the traditional control.

Claims (5)

1. a CRM step-down-flyback PFC converter of constant frequency control, is characterized in that, comprises main power circuit (1) and control circuit, and described main power circuit (1) comprises input power supply v _in , EMI filter device, rectifier diode D ₁ -D ₆ , primary circuit inductance L _p , main circuit secondary transformer inductance L _s , zero-crossing detection inductance L _ZCD , switching tube Q _b and switching tube Q _b/b , freewheeling diode D _o , output capacitance C _o , load R _L ; The input voltage source v _in is connected to the input port of the EMI filter, The output port of the EMI filter is connected to the rectifier bridge composed of rectifier diodes D ₁ -D ₄ and the input port of the rectifier bridge composed of D ₃ -D ₆ , The anodes of the rectifier diodes D ₃ and D ₄ are the zero point of the reference potential, The cathodes of the rectifier diodes D ₅ and D ₆ are connected to the primary side inductance L _p of the main circuit, The other end of the primary side inductance L _p of the main circuit is connected to one end of the switch tube Q _f , The cathodes of the rectifier diodes D ₁ and D ₂ are connected to the secondary inductance L _s of the main circuit and connected to the cathode of the freewheeling diode D _o , The secondary inductance L _s of the main circuit is connected to the positive pole of the output capacitor C _o and the load RL, The negative electrode of the output capacitor C _o and the load RL are connected to one end of Q _b of the switch tube together with the freewheeling diode D _o , The zero-crossing detection inductance L _ZCD is coupled with the main circuit inductance Lp and _Ls , One end of the zero-crossing detection inductance L _ZCD is connected to the zero point of the reference potential and the other end is connected to the current limiting resistor R _ZCD , One end of the current sampling resistor R _s is grounded and the other end is connected to the switching tube Q _f and the switching tube Q _b . 2. The converter according to claim 1, characterized in that the control circuit comprises a main control chip (2), a sampling circuit (3), a digital-to-analog conversion circuit (5), an output voltage differential circuit (4), a feedback circuit (6), state judgment circuit (7), drive signal generation circuit (8), comparison circuit (9) and multiplication circuit (10); The positive input terminal of the output voltage differential circuit (4) is connected to the positive output voltage V _o + of the main circuit (1), The negative input terminal of the output voltage differential circuit (4) is connected to the positive output voltage V _o - of the main circuit (1), The output terminal of the output voltage differential circuit (4) is connected to the first input terminal of the sampling circuit (3) and the input terminal of the feedback circuit (6), The second input terminal of the sampling circuit (3) is connected with the rectified voltage v _g of the main circuit, The first output end of the sampling circuit (3) is connected with the ADC2 port of the main control chip (2), The second output terminal of the sampling circuit (3) is connected with the ADC1 port of the main control chip (2), The first output port of the main control chip (2) is connected with the input port of the digital-to-analog conversion circuit (5), The output port of the digital-to-analog conversion circuit (5) is connected with the input terminal v _x of the multiplier, The output port of the feedback circuit (6) is connected with the input terminal v _y of the multiplier, The output terminal of the multiplier is connected with the positive input terminal of the comparator circuit (9), The negative input terminal of the comparison circuit (9) is connected with the main circuit v _Rs , The output terminal of the comparator circuit (9) is connected with the input terminal of the drive signal generating circuit (8), The input terminal of the driving signal generating circuit (8) is connected with the zero-crossing detection winding L _ZCD of the main circuit through the current limiting resistor R _ZCD , The output end of the driving signal generation circuit (8) is connected with the input end of the state judgment circuit (7), The end of the driving signal generating circuit (8) is connected with the switching tube Q _b of the main power circuit (1), The end of the driving signal generating circuit (8) is connected with the switching tube _Qf of the main power circuit (1). 3. The converter according to claim 2, characterized in that, The sampling circuit (3) converts the input voltage v _g and the output voltage V _o of the converter into voltages v _{g_dsp} and V _{o_dsp} that can be collected by the control chip; The main control chip (4) includes a phase-locking program, an input voltage peak sampling program, an output voltage sampling program and a control program, v _{g_dsp} is connected with the ADC1 interface of the control chip, and the value after sampling is given to the phase-locking program and input The voltage peak sampling program, V _{o_dsp} is connected to the ADC2 interface of the control chip, and the sampled value is given to the output voltage sampling program, and the output of the phase-locking program, the input voltage peak sampling program and the output voltage sampling program are given to the main control program. The control program calculates the value of the contour of the inductor current; The input end of the digital-to-analog conversion circuit (5) is connected with the control chip through the SPI protocol, and it converts the received contour value of the inductor current into a voltage output. 4. The transformer according to claim 2, characterized in that, the state judging circuit (7) comprises a first comparator Comp1, resistors R ₅ , R ₆ , a reference voltage source V _boundary , two AND gates, a NOT gates and a drive circuit; The non-inverting input terminal of the first comparator Comp1 is connected to the rectified voltage v _g of the diode rectification circuit of the main power circuit ( ₁ ) through the voltage dividing resistors _R5 and R6, The inverting input terminal of the first comparator Comp1 is connected to the reference voltage source V _boundary , The output end of the first comparator Comp1 is connected with an input end of the first AND gate AND Gate1 and an input end of the NOT gate, The output end of the NOT gate is connected with an input end of the second AND gate AND Gate2, The output terminals of the two AND gates are connected to the input terminals of the driving circuit, and the output terminals of the driving circuit are respectively connected to the two switching tubes Q _b and Q _f of the main power circuit (1). 5. The transformer according to claim 2, characterized in that, the driving signal generating circuit can adopt integrated IC circuits of models such as L6561 or L6562, the output voltage differential sampling circuit (4) and the output voltage feedback circuit (6) used in The amplifier selects TL074, TL072, LM358, LM324 and other types of operational amplifiers, the multiplier (10) adopts integrated IC circuits or discrete devices to form, and the AND gate used in the state judgment circuit (7) selects logic chips of models such as SN74HC08N, CD4011BE or 74HC32N , the drive circuit can use IR2110, TLP2590 and other types of drive chips or a totem pole drive circuit, and the control chip can use TMS320F28335 or TMS320F28377 and other chips.