CN110517644A - Display device capable of suppressing electromagnetic interference and display drive circuit - Google Patents

Abstract

The present invention relates to a kind of capable of suppressing electromagnetic interference display device and display driver circuits.Display device includes that substrate, active array, display driver and thin film transistor (TFT) (Thin-Film Transistor, TFT) adjust circuit.Active array is set on substrate, and including multiple data lines, a plurality of gate line and multiple pixels, wherein for data line in a crisscross manner in gate line, pixel is coupled to the staggered place of data line and gate line.Display driver is set on substrate, is generated to sequence data clock signal after responding adjusting to driving data line and/or the signal of gate line.Thin film transistor (TFT) adjusts circuit and is set on substrate and couples display driver.It includes one or more thin film transistor (TFT)s that thin film transistor (TFT), which adjusts circuit, it is to respond default gate bias decaying sequence data clock signal (Serial Data Clock, SDCLK amplitude), to sequence data clock signal after display driver offer adjusting.

Description

Display device capable of suppressing electromagnetic interference and display driving circuit

technical field

The present invention relates to the field of display devices, and in particular to a display device capable of suppressing Electromagnetic Interference (EMI) and a display driving circuit.

Background technique

Electromagnetic Interference (EMI) refers to the influence of electromagnetic energy of electronic signals on surrounding components, devices, equipment, and biological tissues. Severe electromagnetic interference may lead to failure of electronic devices and even endanger the health of users. At present, the world pays more and more attention to the electromagnetic interference phenomenon of electronic products, and requires electronic products to meet certain anti-electromagnetic interference standards before they go on the market.

Taking the display device as an example, the display device must pass the electromagnetic interference test before it can be sold on the market. However, as the resolution requirement of the display device is higher and higher, the transmission rate of the display driver to transmit the data signal and the scanning signal must also be increased accordingly, resulting in more and more serious electromagnetic interference phenomenon of the display device. In view of this, it is necessary to propose an improved display technology to reduce the electromagnetic interference of the display device.

Contents of the invention

In order to solve the above technical problems, the object of the present invention is to provide a display device and a display drive circuit, which can effectively reduce the electromagnetic interference of the display device by properly attenuating the serial data clock signal (Serial DataClock, SDCLK) provided to the display driver, Make the display device pass the electromagnetic interference test.

Specifically, the present invention discloses a display device, which includes:

Substrate;

The active array is arranged on the substrate, the active array includes a plurality of data lines, a plurality of gate lines and a plurality of pixels, the data lines are criss-crossed with the gate lines, and the pixels are coupled to the data line and the intersection of the gate lines;

a display driver, arranged on the substrate, the display driver is used to respond to the adjusted serial data clock signal, and generate signals for driving the data lines and/or the gate lines; and

The thin film transistor adjustment circuit is arranged on the substrate and coupled to the display driver, the thin film transistor adjustment circuit includes at least one thin film transistor, and is used to respond to the amplitude of the preset gate bias attenuation sequence data clock signal to control the display The driver provides the conditioned sequential data clock signal.

The display device, wherein the thin film transistor adjustment circuit includes a plurality of thin film transistors arranged in parallel, each of the thin film transistors is connected between the serial data clock signal and the adjusted serial data clock signal, and is controlled by the preset gate bias.

In the display device, the thin film transistor adjustment circuit includes a plurality of thin film transistors arranged in series to form a thin film transistor string, and the thin film transistors are connected in series between the serial data clock signal and the adjusted serial data clock signal, and are subjected to controlled by the preset gate bias.

The display device, wherein the thin film transistor adjustment circuit is realized by a single thin film transistor, the thin film transistor is connected between the serial data clock signal and the adjusted serial data clock signal, and is controlled by the preset gate bias.

The display device, which also includes:

The printed circuit board is coupled to the thin film transistor adjustment circuit, and the printed circuit board is used to provide the serial data clock signal to the thin film transistor adjustment circuit.

The display device, which also includes:

The electronic ink layer is stacked on the active array.

The present invention also discloses a display driving circuit for driving an active array of a display device, which includes:

a display driver, arranged on the substrate, the display driver is used to respond to the adjusted serial data clock signal, and generate a signal for driving the active array; and

The thin film transistor adjustment circuit is arranged on the substrate and coupled to the display driver, the thin film transistor adjustment circuit includes at least one thin film transistor, and is used to respond to the amplitude of the preset gate bias attenuation sequence data clock signal to control the display The driver provides the conditioned sequential data clock signal.

The display driving circuit, wherein the thin film transistor adjustment circuit includes a plurality of thin film transistors arranged in parallel, each of the thin film transistors is connected between the serial data clock signal and the adjusted serial data clock signal, and is controlled by the preset Set the gate bias.

The display driving circuit, wherein the thin film transistor adjustment circuit includes a plurality of thin film transistors arranged in series to form a thin film transistor string, the thin film transistors are connected in series between the serial data clock signal and the adjusted serial data clock signal, and controlled by the preset gate bias.

The display driving circuit, wherein the thin film transistor adjustment circuit is realized by a single thin film transistor, the thin film transistor is connected between the serial data clock signal and the adjusted serial data clock signal, and is controlled by the preset gate extreme bias.

Description of drawings

FIG. 1 is a block diagram of a display device according to an embodiment of the present invention;

2 is a circuit diagram of a thin film transistor regulating circuit according to an embodiment of the present invention;

3 is a circuit diagram of a thin film transistor regulating circuit according to another embodiment of the present invention;

4 is a circuit diagram of a thin film transistor regulating circuit according to another embodiment of the present invention;

FIG. 5 is a cross-sectional view of a display device according to an embodiment of the invention.

Symbol Description:

100, 500: display device; 102: substrate;

104: active array; 106: display driver;

108, 200, 300, 400: thin film transistor regulation circuit; 110: data line;

112: gate line; 114: pixel;

116: printed circuit board; JS: serial data clock signal;

JS': adjusted serial data clock signal; 202, 302, 402: thin film transistors;

PVB: preset gate bias voltage; 502: electronic ink layer;

506: electronic ink unit.

Detailed ways

In order to make the above-mentioned features and effects of the present invention more clear and understandable, the following specific examples are given together with the accompanying drawings for detailed description as follows.

FIG. 1 is a block diagram of a display device 100 according to an embodiment of the invention. The display device 100 may be any type of display, which mainly includes a substrate 102 , an active array 104 , a display driver 106 and a thin-film transistor (Thin-Film Transistor, TFT) regulating circuit 108 . The display device 100 may also include a printed circuit board 116 .

The active array 104 is disposed on the substrate 102 and includes a plurality of data lines 110 , a plurality of gate lines 112 and a plurality of pixels 114 . The data lines 110 are criss-crossed with the gate lines 112 , and the pixels 114 are coupled to the intersections of the data lines 110 and the gate lines 112 to form a pixel array disposed in the display area of the substrate 102 .

The display driver 106 is disposed on the substrate 102, and is used for generating a signal for driving the data line 110 and/or the gate line 112 in response to the adjusted serial data clock signal JS'. The display driver 106 can be a data driver, a gate driver, or a combination of both. Although FIG. 1 shows that the display driver 106 is coupled to the data line 110 as a data driver, it should be noted that the display driver 106 can also be coupled to the gate line 112 as a gate driver, or can be coupled to the data line 110 and the gate line at the same time. 112 as the common drive for both. Compared with the active array 104 , the display driver 106 is disposed in a shielded non-display area on the substrate 102 .

The adjusted serial data clock signal JS' is the result of attenuation of the serial data clock signal (Serial Data Clock, SDCLK) JS. The adjusted sequential data clock signal JS' can be generated by the thin film transistor adjusting circuit 108 . As shown in FIG. 1 , the thin film transistor adjustment circuit 108 is disposed on the substrate 102 and coupled to the display driver 106 , for example, disposed on the non-display area of the substrate 102 . The thin film transistor regulating circuit 108 may include one or more thin film transistors controlled by a predetermined gate bias voltage. The thin film transistor adjustment circuit 108 can attenuate the amplitude of the serial data clock signal JS in response to the preset gate bias voltage, so as to provide the adjusted serial data clock signal JS' to the display driver 106 . The thin film transistors in the thin film transistor adjustment circuit 108 can be fabricated in the same manufacturing process as the active array 104 , for example. The circuit details of the TFT adjustment circuit 108 will be described in conjunction with FIGS. 2 , 3 , and 4 .

The adjusted sequence data clock signal JS'/sequence data clock signal JS determines the working clock of the display driver 106 . The display driver 106 can generate a data signal for driving the data line 110 and/or a gate signal for driving the gate line 112 according to the adjusted sequential data clock signal JS'.

Through the above configuration, the electromagnetic interference effect in the display device 100 can be effectively suppressed. Furthermore, research has found that the serial data clock signal JS from a display signal source (not shown in the figure) is often a high-frequency signal (for example, a frequency of about 50MHz), if it is directly provided to the display driver 106 as a working Clock, serial data The clock signal JS will become one of the main sources of electromagnetic interference. Since the electromagnetic interference is highly positively correlated with the amplitude and frequency of the electronic signal, by appropriately attenuating the amplitude of the sequence data clock signal JS, the attenuated result (ie, the adjusted sequence data clock signal JS') is provided Using the display driver 106 can effectively reduce the electromagnetic interference of the display device 100 .

According to an aspect of the present invention, the display driver 106 and the TFT adjusting circuit 108 can be regarded as a display driving circuit disposed on the substrate 102 of the display device 100 . In one embodiment, the display driver 106 may be a chip, and the TFT adjusting circuit 108 may be coupled to the chip pins of the display driver 106 originally used to receive the serial data clock signal JS.

The printed circuit board 116 is coupled to the TFT regulating circuit 108 . The printed circuit board 116 can provide the serial data clock signal JS to the TFT adjusting circuit 108 . The printed circuit board may be a flexible printed circuit (FPC) board, which serves as a signal transmission interface between the electronic components on the substrate 102 and an external display signal source.

According to an embodiment of the present invention, the thin film transistor adjustment circuit 108 may be implemented by one or more thin film transistors. The gates of the one or more thin film transistors can respond to a preset gate bias to exhibit an on-resistance (RON), thereby properly attenuating the received sequence data clock signal JS to an adjusted sequence data clock signal JS'.

Different embodiments of the thin film transistor adjustment circuit will be described below in conjunction with FIGS. 2 , 3 , and 4 . However, it should be noted that these embodiments are not exhaustive or restrictive, and in some applications, appropriate modification and/or combination of these embodiments may be allowed.

FIG. 2 is a circuit diagram of a TFT adjusting circuit 200 according to an embodiment of the invention. In this embodiment, the TFT regulating circuit 200 includes a single TFT 202 . The thin film transistor 202 is connected between the serial data clock signal JS and the adjusted serial data clock signal JS', and is controlled by a preset gate bias voltage PVB. For example, one terminal (such as drain/source) of the thin film transistor 202 can be coupled to the printed circuit board 116 to receive the serial data clock signal JS, and the other terminal (such as source/drain) is coupled to the display The driver 106 provides the adjusted serial data clock signal JS′ thereto.

The magnitude of the preset gate bias PVB can be programmed to allow the thin film transistor 202 to exhibit an on-resistance. Therefore, compared with the sequence data clock signal JS, the amplitude of the adjusted sequence data clock signal JS' will be attenuated. The degree of attenuation of the amplitude of the adjusted serial data clock signal JS' may depend on the chip decision voltage of the display driver 106 . For example, the attenuation degree of the amplitude of the adjusted serial data clock signal JS' may be required to enable the attenuated level of the adjusted serial data clock signal JS' to be recognized by the display driver 106, and the level change feature is consistent with The sequence data clock signal JS before adjustment remains consistent. In other words, the TFT adjustment circuit 200 does not change the display operation characteristics of the display driver 106 .

FIG. 3 is a circuit diagram of a TFT regulating circuit 300 according to another embodiment of the present invention. In this embodiment, the thin film transistor adjustment circuit 300 includes a plurality of thin film transistors 302 arranged in parallel, and each thin film transistor 302 can be connected between the sequence data clock signal JS and the adjusted sequence data clock signal JS′, and is affected by Controlled by the preset gate bias voltage PVB.

For example, one end (such as drain/source) of each thin film transistor 302 can be coupled to the printed circuit board 116 to receive the serial data clock signal JS, and the other end (such as source/drain) is coupled to to the display driver 106 to provide the adjusted serial data clock signal JS′ to the display driver 106 . The preset gate bias voltage PVB is applied to the control terminals (eg, gates) of the thin film transistors 302 to control the equivalent on-resistance of the thin film transistor regulating circuit 300 .

FIG. 4 is a circuit diagram of a TFT regulating circuit 400 according to yet another embodiment of the present invention. In this embodiment, the TFT adjusting circuit 400 includes a plurality of TFTs 402 arranged in series to form a TFT string 404 . The thin film transistor string 404 is connected between the serial data clock signal JS and the adjusted serial data clock signal JS', and is controlled by a preset gate bias voltage PVB.

For example, the first and the last two thin film transistors 402 in the thin film transistor string 404 can be respectively coupled to the printed circuit board 116 and the display driver 106, so as to receive the sequence data clock signal JS from the printed circuit board 116 and send the display driver 106 outputs the adjusted sequence data clock signal JS′. The preset gate bias voltage PVB can be applied to the control terminals (eg, gates) of the thin film transistors 402 to control the equivalent on-resistance of the thin film transistor strings 404 .

FIG. 5 is a cross-sectional view of a display device 500 according to an embodiment of the present invention. The configuration of the display device 500 is the same as that of the display device 100 in FIG. 1 , but further includes an electronic ink layer 502 as an electronic paper display. The electronic ink layer 502 can be stacked on the active array 104 . The electronic ink layer 502 includes a plurality of electronic ink cells 506 . Each E-ink unit 506 can have a bistable/multi-stable property, so that the image can be kept after being written. For example, the electronic ink unit 506 can be realized by a liquid with charged particles. By applying an electric field to the electronic ink cell 506, the charged particles can be moved in the liquid. The charged particles can have different colors, such as black and white. Therefore, by driving the electrodes in the active array 104 to control the charged particles with the color to be displayed to float up, the electronic ink layer 502 can display the desired image.

According to the embodiments of the present invention, a display device and a display driving circuit capable of suppressing electromagnetic interference can be provided. Research has found that the sequential data clock signal traditionally used in display devices is one of the main sources of electromagnetic interference. Therefore, by properly attenuating the sequence data clock signal provided to the display driver, the electromagnetic interference can be effectively reduced, so that the display device can pass the electromagnetic interference test. In addition, in the embodiment of the present invention, the attenuation of the serial data clock signal is realized through the thin film transistor device. The thin film transistor can be disposed on the substrate of the display device and used as a variable resistor to weaken the strength of the sequential data clock signal. In this way, when the display device fails the EMI test, the developer does not need to redesign the circuit board, but only needs to adjust the preset gate bias voltage provided to the TFT to improve the EMI problem. And because the signal strength of the sequence data clock signal is appropriately attenuated, the power consumption during the operation of the display device can also be reduced.

Claims (10)

1. A display device, characterized in that, comprising: Substrate; The active array is arranged on the substrate, the active array includes a plurality of data lines, a plurality of gate lines and a plurality of pixels, the data lines are criss-crossed with the gate lines, and the pixels are coupled to the data line and the intersection of the gate lines; a display driver, arranged on the substrate, the display driver is used to respond to the adjusted serial data clock signal, and generate signals for driving the data lines and/or the gate lines; and The thin film transistor adjustment circuit is arranged on the substrate and coupled to the display driver, the thin film transistor adjustment circuit includes at least one thin film transistor, and is used to respond to the amplitude of the preset gate bias attenuation sequence data clock signal to control the display The driver provides the conditioned sequential data clock signal. 2. The display device according to claim 1, wherein the thin film transistor adjustment circuit comprises a plurality of thin film transistors arranged in parallel, and each of the thin film transistors is connected to the serial data clock signal and the adjusted serial data clock signal. between signals and is controlled by the preset gate bias voltage. 3. The display device according to claim 1, wherein the thin film transistor adjustment circuit comprises a plurality of thin film transistors arranged in series to form a thin film transistor string, the thin film transistors are connected in series to the serial data clock signal and the adjustment The subsequent data clock signals are controlled by the preset gate bias voltage. 4. The display device according to claim 1, wherein the thin film transistor adjustment circuit is realized by a single thin film transistor, and the thin film transistor is connected between the serial data clock signal and the adjusted serial data clock signal and is controlled by the preset gate bias voltage. 5. The display device according to claim 1, further comprising: The printed circuit board is coupled to the thin film transistor adjustment circuit, and the printed circuit board is used to provide the serial data clock signal to the thin film transistor adjustment circuit. 6. The display device according to claim 1, further comprising: The electronic ink layer is stacked on the active array. 7. A display driving circuit for driving an active array of a display device, characterized in that it comprises: a display driver, arranged on the substrate, the display driver is used to respond to the adjusted serial data clock signal, and generate a signal for driving the active array; and The thin film transistor adjustment circuit is arranged on the substrate and coupled to the display driver, the thin film transistor adjustment circuit includes at least one thin film transistor, and is used to respond to the amplitude of the preset gate bias attenuation sequence data clock signal to control the display The driver provides the conditioned sequential data clock signal. 8. The display driving circuit according to claim 7, wherein the thin film transistor adjustment circuit comprises a plurality of thin film transistors arranged in parallel, and each of the thin film transistors is connected to the sequence data clock signal and the adjusted sequence data clock signal. between pulse signals and is controlled by the preset gate bias voltage. 9. The display driving circuit according to claim 7, characterized in that, the thin film transistor adjustment circuit comprises a plurality of thin film transistors arranged in series to form a thin film transistor string, the thin film transistors are connected in series to the serial data clock signal and the The adjusted sequential data clock signal is controlled by the preset gate bias voltage. 10. The display driving circuit according to claim 7, wherein the thin film transistor adjustment circuit is realized by a single thin film transistor, and the thin film transistor is connected to the sequence data clock signal and the adjusted sequence data clock signal between and controlled by the preset gate bias voltage.