CN110515861A - Storage device and method for processing flash command - Google Patents

Abstract

A kind of method that the application provides solid storage device and is written to data, wherein this method comprises the following steps: in response to having received flash command, obtaining current time to generate the timestamp for being associated with the flash command；Access cache descriptor；Obtain the time stamp data in buffer descriptor；By non-easily the making property memory of the data write-in of cache unit indicated by buffer descriptor of the timestamp of buffer descriptor earlier than the timestamp of the flash command.

Description

Storage device and method for processing flash command

technical field

The present application relates to a storage device, and in particular, to a storage device using a cache to process a flush (Flush) command.

Background technique

Figure 1 shows a block diagram of a solid-state storage device. The solid state storage device 102 is coupled to the host for providing storage capabilities for the host. The host and the solid-state storage device 102 can be coupled in various ways, including but not limited to, for example, SATA (Serial Advanced Technology Attachment, Serial Advanced Technology Attachment), SCSI (Small Computer System Interface, Small Computer System Interface) , SAS (Serial Attached SCSI, Serial Attached SCSI), IDE (Integrated Drive Electronics, Integrated Drive Electronics), USB (Universal Serial Bus, Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIe, high-speed peripheral component interconnection), NVMe (NVM Express, high-speed non-volatile storage), Ethernet, Fibre Channel, wireless communication networks, etc. connect the host and the solid-state storage device 102 . The host may be an information processing device, such as a personal computer, tablet computer, server, portable computer, network switch, router, cellular phone, personal digital assistant, etc., capable of communicating with the storage device in the manner described above. The solid-state storage device 102 includes an interface 103 , a control unit 104 , one or more NVM chips 105 , and a DRAM (Dynamic Random Access Memory, dynamic random access memory) 110 .

NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM, ferroelectric memory), MRAM (Magnetic Random Access Memory, magnetoresistive memory), RRAM (Resistive Random Access Memory, resistive memory), etc. are common NVMs.

The interface 103 may be adapted to exchange data with the host via, for example, SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, Fibre Channel, and the like.

The control unit 104 is used to control the data transmission between the interface 103, the NVM chip 105 and the DRAM 110, and is also used to store and manage the mapping of host logical addresses to flash physical addresses, erase leveling, bad block management, and the like. The control unit 104 can be implemented in various ways of software, hardware, firmware or a combination thereof. For example, the control unit 104 can be an FPGA (Field-programmable gate array, field programmable gate array), an ASIC (Application Specific Integrated Circuit, application specific integrated circuit) circuit) or a combination thereof. The control unit 104 may also include a processor or controller in which software is executed to manipulate the hardware of the control unit 104 to process IO (Input/Output) commands. Control unit 104 may also be coupled to DRAM 110 and may access data of DRAM 110 . The FTL table and/or cached IO command data may be stored in DRAM.

The control unit 104 includes a flash interface controller (or referred to as a media interface controller, a flash channel controller), which is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in a manner that follows the interface protocol of the NVM chip 105 , to operate the NVM chip 105 and receive the command execution result output from the NVM chip 105 . Known NVM chip interface protocols include "Toggle", "ONFI" and the like.

In existing solid-state storage devices, FTL (Flash Translation Layer, flash memory translation layer) is used to maintain mapping information from logical addresses to physical addresses. The logical address constitutes the storage space of the solid-state storage device perceived by upper-layer software such as the operating system. The physical address is the address of the physical storage unit used to access the solid state storage device. In the related art, the address mapping can also be implemented using an intermediate address form. For example, a logical address is mapped to an intermediate address, and the intermediate address is further mapped to a physical address.

A table structure that stores mapping information from logical addresses to physical addresses is called an FTL table. FTL tables are important metadata in solid-state storage devices. Usually, the data item of the FTL table records the address mapping relationship in the unit of data page in the solid-state storage device.

The Flush command is also defined in the NVMe protocol. With the Flush command, the storage device is instructed to save the data (and its metadata) to be written by all commands received prior to the Flush command to the non-volatile storage medium.

Solid-state storage devices use caching to improve performance. For the write command, after the data indicated by the write command is written into the cache, it indicates that the write command is processed. Due to the existence of the cache, when the Flush command is processed, the data in the cache needs to be written to the non-volatile storage medium, which takes a long time. There is a need to reduce or avoid the performance jitter experienced by the host during the process of writing data in the cache to the non-volatile storage medium due to the Flush command.

SUMMARY OF THE INVENTION

The solid-state storage device and the method for writing data to the solid-state storage device of the present application solve the problem of performance jitter caused by the Flush command when the solid-state storage device writes data.

According to a first aspect of the present application, the present application provides a method for writing data to a solid-state storage device, comprising the steps of: in response to receiving a flash command, obtaining a current time to generate a data associated with the flash command Timestamp; access the cache descriptor; obtain the timestamp data in the cache descriptor; write the data of the cache unit indicated by the cache descriptor whose timestamp of the cache descriptor is earlier than the timestamp of the flush command is not easy enable memory.

A method for writing data to a solid-state storage device according to the first aspect of the present application, wherein data of all cache units indicated by cache descriptors with timestamps earlier than that of the flush command are written to In the case of non-volatile memory, it indicates that the flash command processing is completed.

A method for writing data to a solid-state storage device according to a first aspect of the present application, wherein the cache descriptor includes an index of an allocated cache unit, a timestamp indicating a writing time of the allocated cache unit, and The address of the data in the allocated cache unit.

A method of writing data to a solid-state storage device according to a first aspect of the present application, wherein, the address of the data is a logical address or a physical address of a non-volatile memory.

A method for writing data to a solid-state storage device according to a first aspect of the present application, wherein when a write command is received, a cache unit and a cache descriptor of a dynamic random access memory are allocated for the write command.

A method for writing data to a solid-state storage device according to the first aspect of the present application, wherein after receiving a flush command, a flag is set to indicate that there is a flush command to be processed; after the flush command is processed, all set tags.

According to a second aspect of the present application, the present application further provides a method for writing data to a solid-state storage device, wherein the method includes the following steps: in response to data being written to a cache unit of the dynamic random access memory, polling the cache descriptor; Cache descriptor, which writes the data in the cache unit to the non-volatile memory.

A method of writing data to a solid-state storage device according to a second aspect of the present application, wherein the cache unit is released in response to data in the cache unit being written to the non-volatile memory.

According to a third aspect of the present application, the present application further provides a method for writing data to a solid-state storage device, including the following steps: in response to receiving a write command, identifying whether the write command hits a cache unit; The write command hits the cache unit, and it is determined whether the hit cache unit is affected by the flush command; if the hit cache unit is affected by the flush command, the write command is temporarily cached to wait for the flush command After the processing is completed, the write command is processed or a new cache unit that is not affected by the flush command is allocated for the write command.

A method for writing data to a solid-state storage device according to a third aspect of the present application, wherein if the write command does not hit a cache unit, a free cache unit is allocated for the write command, and a corresponding write command is assigned to a cache unit. Data is stored in cache units.

A method for writing data to a solid-state storage device according to a third aspect of the present application, wherein whether the write command hits is identified by whether the logical address to be accessed by the write command is consistent with the logical address recorded in the cache descriptor cache unit.

A method for writing data to a solid-state storage device according to a third aspect of the present application, wherein if the hit cache unit is not affected by the flush command, the write command to be written is stored in the hit cache unit, and indicates that write command processing is complete.

A method for writing data to a solid-state storage device according to a third aspect of the present application, wherein there is currently no refresh command to be executed or although there is currently a refresh command to be executed, the refresh command to be executed is When the timestamp of the hit cache unit is less than the timestamp of the hit cache unit, it is determined that the hit cache unit is not affected by the flush command.

A method for writing data to a solid-state storage device according to a third aspect of the present application, wherein there is currently a flush command to be executed and the timestamp of the flush command to be executed is not less than the time stamp of the hit cache unit. When the time stamp is used, it is determined that the hit cache unit is affected by the flush command.

A method for writing data to a solid-state storage device according to a third aspect of the present application, wherein during the temporary buffering of the write command, the command continues to be received and processed.

A method for writing data to a solid-state storage device according to a third aspect of the present application, wherein allocating a new cache unit that is not affected by the flush command for the write command is any An unoccupied cache unit or an unoccupied cache unit for which there is currently a flush command to be executed, but the timestamp of the to-be-executed flush command is smaller than the timestamp of the cache unit.

A method for writing data to a solid-state storage device according to a third aspect of the present application, wherein after allocating a new cache unit that is not affected by the flush command for the write command, the new non-flush command is also Affected cache units allocate cache descriptors.

A method for writing data to a solid-state storage device according to a third aspect of the present application, wherein the cache descriptor includes an index of an allocated cache unit, a timestamp indicating a writing time of the allocated cache unit, and The address of the data in the allocated cache unit.

According to the method for writing data to a solid-state storage device according to the third aspect of the present application, after the data corresponding to the write command is stored in the cache unit, it is indicated that the write command is completed.

According to a fourth aspect of the present application, the present application further provides a solid-state storage device including a dynamic random access memory, a controller and a non-volatile memory, wherein the controller executes the method described in one of the above.

According to a fourth aspect of the present application, the present application also provides a program comprising program code which, when loaded into the CPU and executed in the CPU, causes the CPU to perform one of the methods described above.

Description of drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only These are some embodiments described in this application. For those of ordinary skill in the art, other drawings can also be obtained according to these drawings.

1 is a schematic structural diagram of a solid-state storage device in the prior art;

FIG. 2 is a schematic structural diagram of a solid-state storage device according to an embodiment of the present application;

3 is a cache descriptor according to an embodiment of the present application;

4A-4C are schematic diagrams of processing a Flush command according to an embodiment of the present application;

5A-5D are schematic diagrams of processing a Flush command according to yet another embodiment of the present application;

6 is a flowchart of processing a Flush command using a cache according to an embodiment of the present application;

FIG. 7 is a flowchart of processing a Flush command by using a cache according to yet another embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present invention.

FIG. 2 shows a block diagram of a solid-state storage device according to an embodiment of the present application. The control part of the solid-state storage device includes a host interface 210 , a CPU 220 , an address translation unit 230 , and a media interface 240 for accessing the NVM chip 105 . The control components are also coupled to external memory (eg, DRAM) 260 .

Cache descriptors are stored in the memory of the control unit. One or more of the cache descriptors record the address of the corresponding cache unit 265 in DRAM 260 and the storage device address of the data occupying the cache unit (eg, the logical address or physical address of the storage device accessible by the host).

The host interface 210 is used to exchange commands and data with the host. For example, the host communicates with the storage device through the NVMe/PCIe protocol, and the host interface 210 processes the PCIe protocol data packet, extracts the NVMe protocol command, and returns the processing result of the NVMe protocol command to the host.

The CPU 220 is coupled to the host interface 210 for receiving IO commands sent by the host to the storage device, and utilizing one or more cache units 265 to service the received IO commands. If the host uses the logical address to access the storage device, the CPU 220 also accesses the address translation unit 230 to convert the logical address into a physical address. The CPU 220 also sends the received IO command (the form of the IO command may change during processing, and is collectively referred to as an IO command here for brevity) to the media interface 240, and the media interface 240 accesses one or more NVMs according to the IO command. chip.

FIG. 3 shows a cache descriptor according to an embodiment of the present application.

Each cache descriptor is used to describe a cache unit corresponding to it. The cache descriptor records the index of the corresponding cache unit (the cache unit index in FIG. 3 ), the timestamp and the logical address (LBA). The cache unit index indicates the location of the cache unit in DRAM 260 . The time stamp records the time the cache unit was allocated, and the logical address (LBA) records the logical address accessed by the IO command to which the cache unit was allocated. Understandably, when the host uses the physical address to access the storage device, the logical address field of the cache unit descriptor is replaced with the recorded physical address.

4A-4C show schematic diagrams of processing a Flush command according to an embodiment of the present application.

Figure 4A shows the IO commands received in the command queue in chronological order. The write command (IOW1) is received at the earliest time T1, then the write command (IO W2) is received at the time of T2, then the Flush command is received, and then the write command (IO W3) and Write command (IO W4). In FIG. 4A, arrows indicate the direction in which time passes. The time when the Flush command is received is between time T3 and time T4.

Figure 4B shows the state of the cache unit before processing the Flush command. According to the storage device of the embodiment of the present application, after receiving the Flush command, it does not stop receiving and processing other IO commands. Therefore, although the Flush command is received before the write command (IO W3), the processing of the write command (IO W3) and the write command (IO W4) has already started, and the write command (IOW3) is allocated a buffer unit (indicated by ID3), And the data to be written by the write command (IO W3) has been stored in the cache unit, the cache unit (indicated by ID4) is allocated for the write command (IO W4), but the data to be written by the write command (IO W4) has not been is written to the cache unit.

Figure 4C shows the state of the cache unit after processing the Flush command. In response to receiving the Flush command, the data to be written of all IO commands received prior to receiving the Flush command (refer to FIG. 4A, the write command (IO W1) and the write command (IO W2)) are written to the non-volatile Storage medium (eg, NVM chip 105, see also Figure 2). The host can then be indicated that the Flush command has been processed. At this time, whether the data to be written by the write command (IO W3) and the write command (IO W4) is written to the non-volatile storage medium is not constrained by the semantics of the Flush command.

5A-5D show schematic diagrams of processing a Flush command according to yet another embodiment of the present application.

Figure 5A is the same as Figure 4A, showing the IO commands received in the command queue in chronological order. Receive the write command (IO W1) at the earliest time T1, then receive the write command (IO W2) at the time of T2, then receive the Flush command, and then receive the write command (IO W3) at the time of T3 and T4. with the write command (IO W4). In FIG. 5A, arrows indicate the direction in which time passes. The time when the Flush command is received is between time T3 and time T4.

Figure 5B shows the state of the cache unit before processing the Flush command. According to the storage device of the embodiment of the present application, after receiving the Flush command, it does not stop receiving and processing other IO commands. Therefore, although the Flush command is received before the write command (IO W3), the processing of the write command (IO W3) and the write command (IO W4) has already started, and the write command (IOW3) is allocated a buffer unit (indicated by ID3), And the data to be written by the write command (IO W3) has not been stored in the cache unit. And before the Flush command starts processing, the write command (IO W4) has not been allocated a buffer unit.

Figure 5C shows the state of the cache unit at a certain point in the process of processing the Flush command. In response to receiving the Flush command, the data to be written of all IO commands (refer to FIG. 5A, the write command (IO W1) and the write command (IO W2)) received prior to the Flush command are written to the non-volatile Loss of storage medium (eg, NVM chip 105, see also Figure 2). At the moment shown in FIG. 5C, the data to be written by the write command (IO W1) has been written to the non-volatile storage medium, while the data to be written by the write command (IO W2) has not been written to the non-volatile storage medium . The data to be written by the write command (IO W3) has not yet been written to the cache unit. And the write command (IO W4) has not yet been allocated a cache unit.

Figure 5D shows the state of the cache unit after processing the Flush command. The data to be written of all IO commands (see Figure 5A, write commands (IO W1) and write commands (IO W2)) received prior to receiving the Flush command have been written to the non-volatile storage medium (eg, NVM Chip 105, see also Figure 2). As the write command (IO W1) is processed, the buffer unit occupied by it is released, and the buffer unit can be allocated to other write commands. The buffer unit occupied by the write command (IO W2) has not been released.

The host can then be indicated that the Flush command has been processed. At this time, whether the data to be written by the write command (IO W3) and the write command (IO W4) is written to the non-volatile storage medium is not constrained by the semantics of the Flush command. As an example, referring to FIG. 5D, the data to be written by the write command (IO W3) has not yet been written to the cache unit. And the cache unit (ID 4) is allocated for the write command (IOW4).

FIG. 6 is a flowchart of processing a Flush command by using a cache according to an embodiment of the present application.

The processing flow shown according to the embodiment of FIG. 6 is controlled by, for example, the CPU 220 of FIG.

In response to the IO command obtained from the host interface (610), the type of the IO command is identified to distinguish whether the IO command is a write command (620) or a Flush command (670). For write commands, allocate buffers for write commands, eg, allocate buffer locations and buffer descriptors that have not yet been used. The address of the allocated buffer unit, the timestamp indicating the current time, and the data to be written by the write command are obtained from the host, and the data to be written is stored in the allocated buffer unit (630). So far, although the data corresponding to the write command has not been written into the NVM chip, it can indicate to the host that the write command is processed (640).

Another task running in the CPU is to move the data written to the cache unit to the NVM chip (650). For example, in response to data being written to the cache unit, the process of moving the data of the cache unit to the NVM chip is started. As yet another example, each cache descriptor is polled to move the data of the cache unit to which the data is written to the NVM chip in turn. Optionally, in response to the data in the cache unit being moved to the NVM chip, the cache unit is freed so that the timestamp in the cache unit is updated (or cleared) and the cache unit can be allocated to other write commands.

For an IO command obtained from a host interface, such as a Flush command, obtain the current time to generate a timestamp associated with the Flush command (680). By accessing each cache descriptor, it is identified whether the data of the cache unit indicated by each cache descriptor with a timestamp earlier than that of the Flush command has been moved to the NVM chip (660). If the data of the cache units indicated by the cache descriptors whose timestamps are earlier than the timestamps of the Flush command are all moved to the NVM chip, the host is indicated to complete the processing of the Flush command (690).

If the data of the cache units indicated by the cache descriptors whose timestamps are earlier than the timestamp of the Flush command have not all been moved to the NVM chip, for the Flush command, the data of the cache units whose timestamps are earlier than the timestamp of the Flush command are not all moved to the NVM chip. After the data of the cache unit indicated by each cache descriptor has been moved to the NVM chip (660), the host is then instructed to complete the processing of the Flush command (690). Understandably, while waiting for the data of the cache units indicated by the cache descriptors whose timestamps are earlier than the timestamp of the Flush command to be moved to the NVM chip, the process shown in FIG. IO commands and process them.

As an example, if a Flush command is received, a flag is set to indicate that a Flush command is pending. And after each IO command is obtained from the host interface, if a flag indicating that there is a Flush command to be processed is found, each cache descriptor is accessed to identify the timestamp indicated by each cache descriptor with a timestamp earlier than that of the Flush command. Whether the data of the cache unit has been moved to the NVM chip. If it is recognized that the Flush command has been processed, the set flag is also cleared.

Referring to FIG. 6, as an example, the task of moving data written into the cache unit to the NVM chip is continuously performed, rather than in response to identifying the cache descriptors with timestamps earlier than the Flush command. The data of the cell is not all moved to the NVM chip to be executed. However, the processing of the Flush command relies on moving the data in the cache unit associated with the Flush command's cache unit to the NVM chip. Optionally, in response to the Flush command to be processed, the task of moving data of the cache units associated with the Flush command to the NVM chip is preferentially processed, so as to move the data written in these cache units to the NVM chip as early as possible.

FIG. 7 is a flowchart of processing a Flush command by using a cache according to yet another embodiment of the present application.

On the basis of the flow chart shown in FIG. 6 , the situation in which the IO write command hits the cache unit is further processed according to the flow chart of the embodiment of FIG. 7 .

In response to receiving the write command (720), whether the write command hits a cache location is identified by whether the logical address to be accessed by the write command is consistent with the logical address recorded by the cache descriptor (730).

If the write command misses the cache unit, allocate a free cache unit for the write command, record a timestamp indicating the current time in the cache entry corresponding to the cache unit, and store the data corresponding to the write command in the cache unit (740). And indicate to the host that write command processing is complete (770).

If the write command hits the cache unit, it is further identified whether the hit cache unit is a cache unit affected by the Flush command and its data needs to be written into the NVM chip (750). If the hit cache unit is not affected by the Flush command (there is currently no Flush command to be executed, or there is currently a Flush command to be executed, but the timestamp of the Flush command to be executed is less than the timestamp of the hit cache unit), the command will be written The data to be written is stored in the hit cache unit (760) and indicates to the host that the write command processing is complete (770). If the hit cache unit is affected by the Flush command (there is currently a Flush command to be executed, and the timestamp of the Flush command to be executed is not less than the timestamp of the hit cache unit) (750), the write command is temporarily cached (780) to The write command is processed after the Flush command is processed. During the temporary buffering of the write command, other IO commands are also obtained from the host interface for processing, so as to avoid the performance jitter of the storage device caused by the execution of the Flush command.

Optionally, if the hit cache unit is affected by the Flush command, allocate a new cache unit and a cache descriptor for the write command, record the address of the allocated cache unit, a timestamp indicating the current time, and a cache descriptor in the cache descriptor. The host acquires the data to be written by the write command, stores the data to be written in the allocated buffer unit, and then indicates to the host that the write command is processed.

The embodiments of the present application also provide a program including program codes, when loaded into a host and executed on the host, the program causes a processor of the host to execute one of the methods provided above according to the embodiments of the present application.

It will be understood that each block of the block diagrams and flowchart illustrations, and combinations of blocks in the block diagrams and flowchart illustrations, respectively, can be implemented by various means including computer program instructions. These computer program instructions may be loaded on a general purpose computer, special purpose computer or other programmable data control device to produce a machine such that the instructions executed on the computer or other programmable data control device create a flow diagram for implementing one or more blocks device with the function specified in .

These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data control device to function in a particular manner, such that the instructions stored in the computer readable memory can be used to manufacture including for implementing a Articles of manufacture of computer readable instructions for the functions specified in the flowchart block or blocks. Computer program instructions can also be loaded onto a computer or other programmable data control device to cause a series of operations to be performed on the computer or other programmable data control device, resulting in a computer-implemented process, which in turn is performed on the computer or other programmable data control device. The instructions executing on the control device provide operations for implementing the functions specified in one or more of the flowchart blocks.

Accordingly, blocks of the block diagrams and flowchart illustrations support combinations of means for performing the specified functions, combinations of operations for performing the specified functions and combinations of program instruction means for performing the specified functions. It will also be understood that each block of the block diagrams and flowchart illustrations, and combinations of blocks in the block diagrams and flowchart illustrations, can be implemented by special purpose hardware-based computer systems that perform the specified functions or operations, or by combinations of special purpose hardware and computer instructions.

Although the examples with reference to the present invention are described for purposes of explanation only and not limitation of the application, changes, additions and/or deletions to the embodiments may be made without departing from the scope of the application.

Many modifications and other embodiments of the applications set forth herein will come to mind to those skilled in the art to which these embodiments pertain having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that this application is not to be limited to the specific embodiments disclosed, but that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims (10)

1. a kind of method to solid storage device write-in data, which comprises the steps of:

In response to having received flash command, current time is obtained to generate the timestamp for being associated with the flash command；

Access cache descriptor；

Obtain the time stamp data in buffer descriptor；

By cache unit indicated by buffer descriptor of the timestamp of buffer descriptor earlier than the timestamp of the flash command Non- easily the making property memory of data write-in.

2. as described in claim 1 to the method for solid storage device write-in data, which is characterized in that in timestamp earlier than institute Non- easily making property memory is all written in the data for stating cache unit indicated by all buffer descriptors of the timestamp of flash command When, indicate that the flash command processing is completed.

3. as claimed in claim 1 or 2 to the method for solid storage device write-in data, which is characterized in that the caching is retouched The index in symbol including distributed cache unit is stated, the timestamp of distributed cache unit write time is indicated and divides The address of data in the cache unit matched.

4. the method to solid storage device write-in data as described in one of claim 1-3, which is characterized in that when received When being write order, the cache unit and buffer descriptor of dynamic RAM are distributed for write order.

5. the method to solid storage device write-in data as described in one of claim 1-4, which is characterized in that

After receiving flash command, setting flag is to have indicated that flash command is to be processed；

After the completion of flash command processing, set label is removed.

6. a kind of method to solid storage device write-in data, which comprises the steps of:

In response to having received write order, identify whether the write order has hit cache unit；

If the write order has hit cache unit, judge the hit cache unit whether the influence by flash command；

If the cache unit being hit is influenced by flash command, write order described in temporal cache is with to the flash command The write order or the cache unit that by flash command is not influenced new for write order distribution are reprocessed after the completion of reason.

7. as claimed in claim 6 to the method for solid storage device write-in data, which is characterized in that if the write order is not Cache unit is hit, then the cache unit idle for write order distribution, and the corresponding data of write order are stored in caching In unit.

8. the method to solid storage device write-in data as claimed in claims 6 or 7, which is characterized in that if be hit Cache unit is not influenced by flash command, then is stored in write order is to be written in the cache unit being hit, and indicate Write order processing is completed.

9. as claimed in claim 8 to the method for solid storage device write-in data, which is characterized in that currently without wait hold Although capable flash command currently has pending flash command, the timestamp of the pending flash command is less than When the timestamp for the cache unit being hit, judge that the cache unit being hit is not influenced by flash command.

10. a kind of solid storage device, including dynamic RAM, controller and nonvolatile memory, wherein controller Execute method described in one of -9 according to claim 1.