CN110510572B - A capacitive pressure sensor and method of making the same - Google Patents

Abstract

The invention discloses a capacitance type pressure sensor and a manufacturing method thereof, which mainly solve the problem of small linear range of the existing pressure sensor and comprise a monocrystalline silicon substrate (1), an insulating layer (2), an isolating layer (3) and a polycrystalline silicon film (4) from bottom to top, wherein the insulating layer (2) consists of N laminated circular steps with the radiuses gradually reduced from top to bottom, N is more than or equal to 2, the thickness of each layer of circular step is the same, the radiuses of the circular steps are different, a through hole (5) for corroding the isolating layer (3) is etched on the polycrystalline silicon film (4), a cavity (6) is formed by corroding the isolating layer (3), metal electrodes (8) are deposited on the polycrystalline silicon film (4) and the monocrystalline silicon substrate (1), and passivation layers (7) cover other surfaces of the isolating layer, the through hole and the polycrystalline silicon film except for the metal electrodes (8). The invention has large linear range, simple process and high yield, and can be used for measuring large-range pressure in automobile systems and industrial fields.

Description

A capacitive pressure sensor and method of making the same

technical field

The invention belongs to the technical field of electronic devices, and in particular relates to a capacitive pressure sensor, which can be used for measuring a wide range of pressure in automotive systems and industrial fields.

technical background

The MEMS pressure sensor is the core component of the pressure monitoring system. Its function is to convert the external pressure into a capacitance signal to be recognized and processed by the system. MEMS pressure sensors have the characteristics of high sensitivity, low power consumption, small size and easy integration, and have important and extensive applications in the fields of intelligent electronics, biomedical, aerospace and automotive systems. Therefore, many scientific research institutions and colleges and universities have invested a lot of money and manpower to study MEMS pressure sensors.

The working modes of MEMS pressure sensors are mainly piezoresistive, capacitive and resonant, and capacitive pressure sensors are the most widely used due to their good linearity and temperature characteristics. Among them, the contact capacitive pressure sensor TMCPS is currently the most studied. A capacitive pressure sensor, in which there is an insulating layer between the upper and lower plates of the capacitor, the upper and lower plates of the capacitor can be contacted when the sensor is working, so it has the advantage of overload protection. In recent years, capacitive pressure sensors have shown a development trend of smaller and smaller size, more and more application fields, and emerging of new materials and new structures. With the increasing market demand for capacitive pressure sensors, the performance requirements for capacitive pressure sensors are also getting higher and higher. Improving the performance of pressure sensors by improving the quality of materials cannot meet the current application needs. Therefore, the device structure optimization is adopted. Designing to improve the performance of pressure sensors has become a research hotspot at home and abroad.

At present, many researchers have invested in the research and development of high-performance contact pressure sensors. In 2001, Jiao Yuzhong and others proposed a capacitive pressure sensor with a double-film structure, which expanded the linear range of the sensor, but reduced the sensitivity. , 2001. In 2016, Wang Wenjing et al. proposed a capacitive pressure sensor with a comb-tooth electrode structure, which effectively expanded the linear range and improved the sensitivity, see patent CN106153241A. However, in this invention, the performance of the sensor is improved by introducing a comb-tooth electrode structure, and the process preparation is difficult. In 2017, Myong-Chol Kang et al. proposed improving the shape of the bottom electrode in a capacitive pressure sensor, which expanded the linear range of the sensor, but resulted in reduced sensitivity. See A simple analysis to improve linearity of touch mode capacitive pressure sensor by modifying shape of fixed electrode [J]. Sensors and Actuators A: Physical, 263: 300-304, 2017. Therefore, it has been reported that the pressure linear range and sensitivity of the contact capacitive pressure sensor are difficult to improve at the same time, and the pressure linear range is usually small, which cannot meet the monitoring needs of a large range of pressure in many fields such as automotive systems and aerospace.

SUMMARY OF THE INVENTION

The purpose of the present invention is to overcome the above-mentioned deficiencies of the prior art, and to provide a capacitive pressure sensor with a simple manufacturing process and a large linear range and a manufacturing method thereof, so as to significantly increase the pressure linear range without losing sensitivity, and improve the capacitive pressure sensor. The overall performance of the pressure sensor.

In order to achieve the above object, the capacitive pressure sensor of the present invention, the structure includes a single crystal silicon substrate (1), an insulating layer (2), an isolation layer (3) and a polysilicon film (4) from bottom to top, the polysilicon film (4) A through hole (5) for etching the isolation layer (3) is etched thereon, the isolation layer (3) is etched to form a cavity (6), and the polysilicon film (4) and the single crystal silicon substrate (1) A metal electrode (8) is deposited thereon, and a passivation layer (7) is covered on the surface of the isolation layer (3), the through hole (5) and the polysilicon thin film (4) except for the metal electrode (8) area, characterized in that in:

The insulating layer (2) is composed of N stacked circular steps with gradually decreasing radii from top to bottom. The total thickness T is 250 nm to 800 nm, and the thickness of each circular step is t=T/N, where N is Integer, and _N≥2 , the radius ri of each circular step is determined by solving the following equation:

15T/R ⁶ ×(Rr _i ) ⁵ ×r _i =(i-1)T/N,

where i is an integer, and 1≤i≤N, and R is the radius of the cavity (6).

Further, it is characterized in that the thickness h of the polysilicon film (4) is 2-10 μm, the radius _rs is 150-600 μm, and the overlapping length of the polysilicon film (4) and the cavity (6) in the horizontal direction is greater than 5 μm .

Further, it is characterized in that the height g of the cavity (6) is 4-10 μm, and the radius R is 100 μm-500 μm.

Further, it is characterized in that the height of the isolation layer (3) is the same as the height of the cavity (6).

Further, it is characterized in that the insulating layer (2) is made of SiO ₂ ; the isolation layer (3) is made of SiN; the passivation layer (7) is made of SiO ₂ , SiN, Al ₂ O ₃ , HfO ₂ , Sc Any of ₂ O ₃ .

In order to achieve the above purpose, the method for making a capacitive pressure sensor provided by the present invention includes the following processes:

A) On the single crystal silicon substrate, the single crystal silicon in the N-layer insulating layer region is etched by the ion etching process:

A1) Make a mask on the single crystal silicon substrate, and use the mask to etch the first insulating layer region with a radius of r ₁ and a thickness of t on the single crystal silicon substrate;

A2) making a secondary mask on the single crystal silicon substrate, and using the mask to etch the second insulating layer region with a radius of r ₂ and a thickness of t on the single crystal silicon substrate;

And so on, until the Nth insulating layer area with radius r _N and thickness t is etched, N is determined according to the actual use requirements of the device, and its value is an integer greater than or equal to 2;

B) In the area of the N-layer insulating layer etched on the single-crystal silicon substrate, the insulating layer dielectric is deposited by the plasma enhanced chemical vapor deposition process, and is flattened to obtain an insulating layer with a total thickness T of 250 nm to 800 nm. The insulating layer is composed of N stacked circular steps with gradually decreasing radius from top to bottom, the thickness of each circular step is t=T/N, N is an integer, and N≥2;

C) depositing an isolation layer with a thickness g of 4-10 μm on the single crystal silicon substrate and the insulating layer;

D) making a mask on the isolation layer for the first time, and using the mask to etch and remove the isolation layer medium of the metal electrode region on the single crystal silicon substrate;

E) depositing a polysilicon film with a thickness h of 2-10 μm on the isolation layer;

F) making a mask for the second time on the polysilicon film, and using the mask to etch through holes;

G) Through the through hole on the polysilicon film, the isolation layer is etched by the wet etching process to form a cavity with a radius R of 100 μm to 500 μm and a height g of 4 to 10 μm, and satisfies 15T/R ⁶ ×(Rr _i ) ⁵ × ri =( _i -1)T/N, where ri is the radius of the _i -th insulating layer region, i is an integer, and 1≤i≤N;

H) making a mask on the polysilicon film for the third time, and using the mask to etch to obtain a polysilicon film with a radius _rs of 150-600 μm;

1) covering passivation layer on polysilicon film, through hole, isolation layer and monocrystalline silicon substrate;

J) make a mask for the fourth time on the passivation layer, and use the mask to etch and remove the passivation layer medium of the metal electrode region on the passivation layer;

K) Making a mask on the passivation layer for the fifth time, using the mask to deposit the metal electrodes on the monocrystalline silicon substrate and the polycrystalline silicon thin film by the electron beam evaporation process, to complete the fabrication of the whole device.

Compared with the traditional contact capacitive pressure sensor, the present invention has the following advantages:

1. Large linear range.

The invention adopts N layers of insulating layer, and by setting the thickness of the insulating layer to change nonlinearly with the radial direction, the nonlinear deformation caused by the force of the elastic film can be compensated, thereby ensuring the linear change of the output capacitance, improving the linearity and expanding the linearity of the sensor. scope.

2. The process is simple and the yield is high.

The invention improves the linear range of the sensor by manufacturing the N-layer insulating layer through the etching and deposition process, the process is simple, the process complexity problem caused by the use of the comb-tooth structure, the cantilever beam structure and the like is avoided, and the manufacturing difficulty of the sensor is reduced. , improve the device yield.

The simulation results show that the linear range of the capacitive pressure sensor of the present invention is obviously better than that of the traditional contact capacitive pressure sensor.

Description of drawings

Fig. 1 is the top-view structure schematic diagram of the capacitive pressure sensor of the present invention;

Fig. 2 is the cross-sectional structure schematic diagram to the transverse direction AB of Fig. 1;

Fig. 3 is the process flow chart of the capacitive pressure sensor of the present invention;

Fig. 4 is the simulation comparison diagram of the output capacitance of the present invention and the traditional contact type contact pressure sensor with pressure change;

FIG. 5 is a simulation comparison diagram of the sensitivity of the present invention and a conventional pressure sensor changing with pressure.

Detailed ways

The embodiments and effects of the present invention will be described in further detail below with reference to the accompanying drawings.

Referring to FIG. 1 and FIG. 2 , the capacitive pressure sensor of the present invention is a multi-layer structure based on a single crystal silicon substrate, and the structure includes from bottom to top: a single crystal silicon substrate 1, an insulating layer 2, an isolation layer 3 and a polysilicon film 4.

The height g of the isolation layer 3 is 4 to 10 μm, and SiN can be used, and a cavity 6 is arranged in the middle; The overlapping length in the horizontal direction is greater than 5 μm;

The polysilicon film 4 has a thickness h of 2 to 10 μm, a radius _rs of 150 to 600 μm, a through hole 5 in the middle, and a metal electrode 8 deposited on the polysilicon film 4 and the single crystal silicon substrate 1 .

The isolation layer 3 , the through hole 5 and the other surfaces of the polysilicon film 4 except the metal electrode 8 are covered with a passivation layer 7 , the passivation layer 7 has a thickness of 0.06 μm to 0.12 μm, and SiO ₂ One of , SiN, Al ₂ O ₃ , HfO ₂ , Sc ₂ O ₃ ;

The insulating layer 2 is composed of N stacked circular steps whose radius gradually decreases from top to bottom. is an integer, and _N≥2 , the radius ri of each circular step is determined by solving the following equation:

15T/R ⁶ ×(Rr _i ) ⁵ ×r _i =(i-1)T/N,

Wherein, i is an integer and 1≤i≤N, R is the radius of the cavity 6, and the insulating layer 2 is SiO ₂ .

3, the method for making a capacitive pressure sensor of the present invention provides the following three embodiments:

Embodiment 1: A capacitive pressure sensor with the insulating layer of SiO ₂ , the isolation layer of SiN, the passivation layer of SiN, and the number of insulating layers N=2 is fabricated.

Step 1, etch the single crystal silicon in the region of the two insulating layers on the single crystal silicon substrate, as shown in FIG. 3a.

1a) Make a mask on a single crystal silicon substrate, using reactive ion etching technology, that is, under the process conditions of CF4 flow rate of _15sccm , pressure of 10mT, and power of 80W, the etching thickness t is 125nm, and the radius r ₁ is the area of the first insulating layer of 100 μm;

1b) Make a secondary mask on the single crystal silicon substrate, use the same reactive ion etching process conditions as 1a), and etch the second insulating layer region with a thickness t of 125 nm and a radius r ₂ of 39 μm.

In step 2, an insulating layer dielectric SiO ₂ is deposited in the region of the N-layer insulating layer etched on the single crystal silicon substrate, and planarized to obtain an insulating layer, as shown in FIG. 3 b .

Plasma-enhanced chemical vapor deposition technology was used, that is, under the process conditions of N ₂ O flow rate of 800 sccm, SiH ₄ flow rate of 200 sccm, temperature of 250 °C, RF power of 25 W, and pressure of 1100 mT, on a single crystal silicon substrate An insulating layer dielectric SiO ₂ is deposited in the etched insulating layer region and planarized to obtain an insulating layer.

In step 3, a SiN isolation layer is deposited on the single crystal silicon substrate and the insulating layer, as shown in Figure 3c.

Plasma-enhanced chemical vapor deposition technology was adopted, that is, under the process conditions of _NH3 flow rate of 2.5sccm, _N2 flow rate of 950sccm, _SiH4 flow rate of 250sccm, temperature of 300°C, RF power of 25W, and pressure of 950mTorr, the An isolation layer with a thickness g of 4 μm is deposited on the single crystal silicon substrate.

Step 4, removing the isolation layer dielectric in the metal electrode region on the single crystal silicon substrate, as shown in Figure 3d.

A mask was made on the isolation layer for the first time, and the reactive ion etching technology was used, that is, under the process conditions of CF4 flow rate of _55sccm , _O2 flow rate of 8sccm, pressure of 18mT, and power of 280W, the single crystal silicon was etched and removed. Spacer dielectric for metal electrode regions on substrates.

Step 5, depositing a polycrystalline silicon film on the single crystal silicon substrate and the isolation layer, as shown in Figure 3e.

The chemical vapor deposition technique was adopted, that is, under the condition that the reaction chamber temperature was 1200 °C, the SiCl4 flow rate was ₅ mol% in _H2 , and the film growth rate was 2.2 μm/min on the monocrystalline silicon substrate and the isolation layer A polysilicon film with a thickness h of 2 μm is deposited;

Step 6, etching through holes on the polysilicon film, as shown in Figure 3f.

A mask was made on the polysilicon film for the second time, and through holes were etched on the polysilicon film by reactive ion etching process with CF4 flow rate of _15sccm , pressure of 10mT, and power of 100W.

In step 7, the isolation layer is etched through the through hole on the polysilicon film to form a cavity, as shown in Figure 3g.

The isolation layer was etched under wet etching conditions with a concentration of H ₃ PO ₄ solution of 90% and a temperature of 180° C. to form a cavity with a radius R of 100 μm in the middle of the isolation layer.

Step 8, etching the polysilicon film medium to obtain a polysilicon film with a radius _rs of 150 μm, as shown in Figure 3h.

A mask was made on the polysilicon film for the third time, using reactive ion etching technology, that is, under the process conditions of CF4 flow rate of _15sccm , pressure of 10mT, and power of 100W, a polysilicon film with a radius _rs of 150μm was obtained.

In step 9, a SiN passivation layer is deposited on the polysilicon film, the isolation layer and the single crystal silicon substrate, as shown in Figure 3i.

Plasma-enhanced chemical vapor deposition technology was adopted, that is, under the process conditions of _NH3 flow rate of 2.5sccm, _N2 flow rate of 950sccm, _SiH4 flow rate of 250sccm, temperature of 350°C, RF power of 30W, and pressure of 1000mT, the A SiN passivation layer with a thickness of 0.06 μm is deposited on the single crystal silicon substrate, the isolation layer and the polycrystalline silicon film.

Step 10, remove the passivation layer dielectric in the metal electrode region on the single crystal silicon substrate and the polycrystalline silicon film, as shown in Figure 3j.

The fourth time mask was made on the polysilicon film and single crystal silicon substrate, using reactive ion etching technology, that is, under the process conditions of CF4 flow rate of _20sccm , _O2 flow rate of 2sccm, pressure of 20mT, and bias voltage of 100V The lower etching removes the passivation layer of the metal electrode region on the single crystal silicon substrate and the polycrystalline silicon film.

In step 11, metal electrodes are deposited on the monocrystalline silicon substrate and the polycrystalline silicon thin film, as shown in Figure 3k.

的工艺条件下，在单晶硅衬底和多晶硅薄膜上依次淀积Al、Au金属，制作厚度为0.08μm/1.2μm金属电极，再在气体为N₂，温度为700℃，时间为30s的工艺条件下快速退火，完成整个器件的制作。The fifth time mask was made on the polycrystalline silicon film and single crystal silicon substrate, and the electron beam evaporation technology was used, that is, the vacuum degree was less than 1.8×10 ^-3 Pa, the power was 220W, and the evaporation rate was less than

Under the same process conditions, Al and Au metals were sequentially deposited on the single crystal silicon substrate and polycrystalline silicon film to make metal electrodes with a thickness of 0.08μm/1.2μm, and then the gas was N ₂ , the temperature was 700 ℃, and the time was 30s. Rapid annealing under process conditions completes the fabrication of the entire device.

Embodiment 2: A capacitive pressure sensor with the insulating layer made of SiO ₂ , the isolation layer made of SiN, the passivation layer made of Al ₂ O ₃ , and the number of insulating layers N=4 was fabricated.

In step 1, the single crystal silicon in the region of the four insulating layers is etched on the single crystal silicon substrate, as shown in Figure 3a.

1.1) Make a mask on the single crystal silicon substrate, and use reactive ion etching technology to etch the first layer of insulating layer region, the thickness t of the first layer of insulating layer region is 0.1 μm, and the radius r ₁ is 250 μm;

1.2) A secondary mask is made on the monocrystalline silicon substrate, and reactive ion etching technology is used to etch the second insulating layer region, the thickness t of the second insulating layer region is 0.1 μm, and the radius r ₂ is 123 μm;

1.3) Make three masks on the single crystal silicon substrate, and use reactive ion etching technology to etch the third insulating layer region, the thickness t of the third insulating layer region is 0.1 μm, and the radius r ₃ is 97 μm;

1.4) Four masks were made on the monocrystalline silicon substrate, and the fourth layer of insulating layer region was etched using reactive ion etching technology, the thickness t of the fourth layer of insulating layer region was 0.1 μm, and the radius r ₄ was 76 μm;

The process conditions of the reactive ion etching are as follows: the flow rate of CF4 is _20sccm , the pressure is 20mT, and the power is 100W.

In step 2, an insulating layer is obtained, as shown in Figure 3b.

The insulating layer dielectric SiO ₂ is deposited in the insulating layer region etched on the single crystal silicon substrate by using the plasma enhanced chemical vapor deposition technology, and is planarized to obtain the insulating layer.

The process conditions of the plasma-enhanced chemical vapor deposition technique for depositing the medium are: N ₂ O flow rate of 850 sccm, SiH ₄ flow rate of 250 sccm, temperature of 250° C., RF power of 35 W, and pressure of 1200 mT.

Step 3, depositing a SiN isolation layer, as shown in Figure 3c.

Plasma-enhanced chemical vapor deposition technology was used to deposit an isolation layer with a thickness g of 5.5 μm on a single crystal silicon substrate. The process conditions of the plasma-enhanced chemical vapor deposition technology were as follows: the gases were NH ₃ , N ₂ and SiH _4. The gas flow rates were 2.5 sccm, 950 sccm and 250 sccm, and the temperature, RF power and pressure were 300 °C, 25 W and 950 mTorr, respectively.

Step 4, remove the isolation layer dielectric in the metal electrode region on the single crystal silicon substrate, as shown in Figure 3d.

A mask was made on the isolation layer for the first time, and the isolation layer dielectric in the metal electrode region _on the single crystal silicon substrate was etched and removed by reactive ion etching technology. _The O flow was 8sccm, the pressure was 18mT, and the power was 280W.

Step 5, depositing a polycrystalline silicon film on the single crystal silicon substrate and the isolation layer, as shown in Figure 3e.

A polysilicon film with a thickness h of 5 μm was deposited on the single crystal silicon substrate and the isolation layer by chemical vapor deposition technology. The process conditions for depositing the polysilicon film were as follows: the temperature of the reaction chamber was 1200 °C, and the flow rate of SiCl ₄ was at H ₂ The molar percentage in the film was 5%, and the film growth rate was 2.5 μm/min.

Step 6, etching through holes on the polysilicon film, as shown in Figure 3f.

A mask is made on the polysilicon film for the second time, and through holes are etched on the polysilicon film by reactive ion etching technology. The process conditions of reactive ion etching are: CF4 flow rate is _15sccm , pressure is 10mT, power is 100W .

In the seventh step, a cavity is formed in the middle of the isolation layer, as shown in Figure 3g.

The isolation layer is etched by wet etching technology to form a cavity with a radius R of 250 μm in the middle of the isolation layer. The process conditions of the wet etching technology are: H ₃ PO ₄ solution concentration of 91.5% and temperature: 190°C.

In the eighth step, a polysilicon film is obtained, as shown in Figure 3h.

A mask was made on the polysilicon film for the third time, and a polysilicon film with a radius _rs of 300 μm was obtained by reactive ion etching technology _. 100W.

In the ninth step, a passivation layer is deposited on the polycrystalline silicon film, the isolation layer and the single crystal silicon substrate, as shown in Figure 3i.

Using plasma enhanced chemical vapor deposition technology, a passivation layer Al ₂ O ₃ with a thickness of 0.1 μm was deposited on the single crystal silicon substrate, the isolation layer and the polysilicon film. The process conditions of the plasma enhanced chemical vapor deposition were as follows: : TMA and H ₂ O were used as reaction sources, the carrier gas was N ₂ , the carrier gas flow rate was 200sccm, the substrate temperature was 300°C, and the pressure was 700Pa.

Step ten, removing the passivation layer of the metal electrode region on the single crystal silicon substrate and the polycrystalline silicon film, as shown in Figure 3j.

A mask is made for the fourth time on the polycrystalline silicon film and the single crystal silicon substrate, and the passivation layer of the metal electrode region on the single crystal silicon substrate and the polycrystalline silicon film is etched and removed by reactive ion etching technology. The reactive ion etching process The conditions were: CF ₄ flow rate of 20 sccm, O ₂ flow rate of 2 sccm, pressure of 20 mT, and bias voltage of 100 V.

In step eleven, metal electrodes are deposited on the monocrystalline silicon substrate and the polycrystalline silicon thin film, as shown in Figure 3k.

快速退火采用的工艺条件为：气体为N₂，温度为700℃，时间为30s，完成整个器件的制作。A mask was fabricated for the fifth time on the polycrystalline silicon film and single crystal silicon substrate, and Al and Au metals were sequentially deposited on the single crystal silicon substrate and polycrystalline silicon film by electron beam evaporation technology, and metal electrodes with a thickness of 0.08μm/1.2μm were fabricated , and then perform rapid annealing in N ₂ atmosphere. The process conditions used for metal deposition are: vacuum degree is less than 1.8×10 ^-3 Pa, power is 230W, evaporation rate is less than

The process conditions used in the rapid annealing are as follows: the gas is N ₂ , the temperature is 700° C., and the time is 30 s to complete the fabrication of the entire device.

Embodiment 3: A capacitive pressure sensor with the insulating layer made of SiO ₂ , the isolation layer made of SiN, the passivation layer made of HfO ₂ , and the number of insulating layers N=5 was fabricated.

In step A, the single crystal silicon in the region of the 5-layer insulating layer is etched on the single crystal silicon substrate, as shown in FIG. 3a.

First, make a mask on the single crystal silicon substrate, use reactive ion etching technology to etch the first layer of insulating layer area, the thickness t of the first layer of insulating layer area is 0.16μm, the radius r ₁ is 500μm; A secondary mask was made on the crystalline silicon substrate, using reactive ion etching technology to etch the second insulating layer region with a thickness t of 0.16 μm and a radius r ₂ of 260 μm, and then made a three-time mask on the single crystal silicon substrate. mold, using reactive ion etching technology, etching thickness t is 0.16μm, radius r3 is 213μm in the _third layer of insulating layer region; then make four masks on the single crystal silicon substrate, using reactive ion etching technology , the etching thickness t is 0.16μm, the radius _r4 is 177μm in the fourth insulating layer region, and then five masks are made on the single crystal silicon substrate, using reactive ion etching technology, the etching thickness t is 0.16μm , the 5th insulating layer region with radius r ₅ of 142 μm,

Among them, the process conditions of reactive ion etching are: the flow rate of CF4 is _25sccm , the pressure is 30mT, and the power is 120W.

In step B, an insulating layer dielectric is deposited in the etched insulating layer region on the single crystal silicon substrate and planarized to obtain an insulating layer, as shown in Figure 3b.

Under the process conditions of N ₂ O flow rate of 900 sccm, SiH ₄ flow rate of 300 sccm, temperature of 250 °C, RF power of 40 W, and pressure of 1300 mT, an insulating layer was deposited in the region of the insulating layer etched on the single crystal silicon substrate. medium to obtain an insulating layer.

In step C, an isolation layer is deposited on the single crystal silicon substrate and the insulating layer, as shown in Figure 3c.

Plasma-enhanced chemical vapor deposition technology was used under the process conditions of NH ₃ , N ₂ and SiH ₄ gas, gas flow rate of 2.5sccm, 950sccm and 250sccm, temperature, RF power and pressure of 300℃, 25W and 950mTorr respectively , deposit an isolation layer SiN with a thickness g of 10 μm on the single crystal silicon substrate.

In step D, the isolation layer of the metal electrode region on the single crystal silicon substrate is removed, as shown in Figure 3d.

The mask was made on the isolation layer for the first time, and the reactive ion etching technology was used to etch and remove the single crystal silicon substrate under the process conditions of CF4 flow rate of _55sccm , _O2 flow rate of 8sccm, pressure of 18mT, and power of 280W. Isolation layer for metal electrode area.

In step E, a polycrystalline silicon film is deposited on the single crystal silicon substrate and the isolation layer, as shown in Figure 3e.

Using plasma-enhanced chemical vapor deposition technology, under the process conditions that the reaction chamber temperature and film growth rate are 1200 °C and 3 μm/min, respectively, and the SiCl4 flow rate is ₅ mol% in _H2 , the monocrystalline silicon lining A polysilicon film with a thickness h of 10 μm is deposited on the bottom and the isolation layer.

In step F, a through hole is etched on the polysilicon film, as shown in Figure 3f.

A second mask was made on the polysilicon film layer, and through-holes were etched on the polysilicon film by reactive ion etching technology under the conditions of CF4 flow rate of _15sccm , pressure of 10mT, and power of 100W.

In step G, the isolation layer is etched to form a cavity with a radius R of 500 μm, as shown in FIG. 3g.

Using wet etching technology, under the process conditions of H ₃ PO ₄ solution concentration of 92% and temperature of 200° C., a cavity is formed in the middle of the isolation layer.

In step H, a polysilicon film with a radius _rs of 600 μm is obtained, as shown in Figure 3h.

A mask is made on the polysilicon film layer for the third time, and the reactive ion etching technology is used to etch the medium around the polysilicon film under the process conditions of CF4 flow rate of _15sccm , pressure of 10mT, and power of 100W to obtain a radius _rs of 600μm. polysilicon film.

In step I, a passivation layer is deposited on the polysilicon film, the isolation layer and the single crystal silicon substrate, as shown in Figure 3i.

Using RF magnetron reactive sputtering technology, under the process conditions of _O2 and Ar, gas flow rate of 1sccm and 8sccm, temperature, Hf target RF power and reaction chamber sputtering pressure of 200°C, 150W and 0.1Pa, respectively , and deposit a HfO ₂ passivation layer with a thickness of 0.12 μm on the monocrystalline silicon substrate, the isolation layer and the polycrystalline silicon film.

In step J, the passivation layer of the metal electrode region on the single crystal silicon substrate and the polycrystalline silicon film is removed, as shown in Figure 3j.

A mask was made for the fourth time on the polycrystalline silicon thin film and single crystal silicon substrate, and the reactive ion etching technology was used under the process conditions of CF4 flow rate of _20sccm , _O2 flow rate of 2sccm, pressure of 20mT, and bias voltage of 100V. The passivation layer of the metal electrode region on the single crystal silicon substrate and the polycrystalline silicon film is removed by etching.

In step K, metal electrodes are deposited on the monocrystalline silicon substrate and the polycrystalline silicon thin film, as shown in Figure 3k.

的工艺条件下，在单晶硅衬底和多晶硅薄膜上依次淀积Al/Au金属，制作厚度为0.08μm/1.2μm的金属电极，再采用快速退火技术在气体为N₂，温度为700℃，时间为30s的工艺条件下进行快速退火,完成整个器件的制作。The fifth time mask was made on the polycrystalline silicon film and single crystal silicon substrate, and the vacuum degree was less than 1.8×10 ^-3 Pa, the power was 240W, and the evaporation rate was less than

Under the same process conditions, Al/Au metal was sequentially deposited on the single crystal silicon substrate and polycrystalline silicon film to make metal electrodes with a thickness of 0.08 μm/1.2 μm, and then the rapid annealing technology was used in the gas of N ₂ and the temperature of 700 ℃. , and rapid annealing was performed under the process conditions of 30s to complete the fabrication of the entire device.

The effects of the present invention can be further illustrated by the following simulations.

1. Simulation parameters

Suppose the traditional contact capacitive pressure sensor and the sensor of the present invention have the same size except for the insulating layer, the thickness h of the polysilicon film is 5 μm, the height g of the cavity is 5.5 μm, and the radius R is 250 μm;

The thickness of the insulating layer of the traditional pressure sensor is 0.36μm and the radius is 250μm;

The sensor of the present invention has ten insulating layers, the total thickness T is 0.36 μm, the thickness t of each layer is 36 nm, and the radii of the ten insulating layers are respectively r ₁ =250 μm, r ₂ =148 μm, r ₃ =130 μm, r ₄ =117 μm, r ₅ =106 μm, r ₆ =97 μm, r ₇ =88 μm, r ₈ =80 μm, r ₉ =71 μm, r ₁₀ =61 μm.

2. Simulation content

Simulation 1: The change of the output capacitance of the present invention and the traditional contact capacitive pressure sensor in the pressure range of 0 to 3000KPa is simulated, and the change of the output capacitance with the pressure is shown in Figure 4. It can be seen from FIG. 4 that the linearity of the output capacitance of the sensor of the present invention with the pressure change is better than that of the conventional sensor.

Simulation 2: The change of the sensitivity of the present invention and the traditional capacitive pressure sensor in the pressure range of 0 to 3000KPa is simulated, and the change of the sensitivity with the pressure is shown in Figure 5.

It can be seen from Fig. 5 that the linear pressure range of both the traditional sensor and the sensor of the present invention starts from 260KPa. When the pressure is greater than 320KPa, the sensitivity of the traditional sensor begins to decrease significantly, while the sensitivity of the sensor of the present invention remains in the pressure range of 3000KPa. stable, so the sensor of the present invention has a larger linear pressure range.

The above descriptions are all three specific examples of the present invention. For those skilled in the art, after understanding the content and principles of the present invention, they can use the method according to the present invention without departing from the principles and scope of the present invention. Various modifications and changes in form and details are carried out, for example, in addition to the materials used in the three specific examples, the passivation layer can also use any one of SiO ₂ and Sc ₂ O ₃ , but these modifications and Changes are still within the scope of the claims of the present invention.

Claims (5)

1. A method of making a capacitive pressure sensor, comprising:

A) and etching the monocrystalline silicon in the region of the N-layer insulating layer on the monocrystalline silicon substrate by adopting an ion etching process:

A1) making a mask on a monocrystalline silicon substrate, and etching the monocrystalline silicon substrate with the mask to obtain a substrate with a radius r₁A1 st insulating layer region with the thickness t;

A2) manufacturing a secondary mask on the monocrystalline silicon substrate, and etching the monocrystalline silicon substrate with the radius r by using the secondary mask₂A2 nd insulating layer region with the depth of t;

and so on until the radius is r_NThe Nth insulating layer area with the thickness of t is determined according to the actual use requirement of the device, and the value of N is an integer which is more than or equal to 2;

B) depositing an insulating layer medium in an N insulating layer region etched on a monocrystalline silicon substrate by adopting a plasma enhanced chemical vapor deposition process, and flattening to obtain an insulating layer with the total thickness T of 250-800 nm, wherein the insulating layer consists of N laminated circular steps with the radius gradually reduced from top to bottom, the thickness of each circular step is T ═ T/N, N is an integer, and N is more than or equal to 2;

C) Depositing an isolation layer with the thickness g of 4-10 mu m on the monocrystalline silicon substrate and the insulating layer;

D) manufacturing a mask on the isolation layer for the first time, and removing the isolation layer medium in the metal electrode area on the monocrystalline silicon substrate by etching by using the mask;

E) depositing a polycrystalline silicon film with the thickness h of 2-10 mu m on the isolation layer;

F) manufacturing a mask on the polycrystalline silicon film for the second time, and etching to form a through hole by using the mask;

G) through the through hole on the polycrystalline silicon film, the isolating layer is etched by adopting a wet etching process to form a cavity with the radius R of 100-500 mu m and the height g of 4-10 mu m, and the cavity meets the requirement of 15T/R⁶×(R-r_i)⁵×r_i(i-1) T/N, wherein i is an integer, and 1 ≦ i ≦ N;

H) making a mask on the polysilicon film for the third time, and obtaining the radius r by using the mask_sA polysilicon thin film of 150 to 600 μm;

I) covering a passivation layer on the polycrystalline silicon thin film, the through hole, the isolation layer and the monocrystalline silicon substrate;

J) manufacturing a mask on the passivation layer for the fourth time, and etching and removing the passivation layer medium in the metal electrode area on the passivation layer by using the mask;

K) and manufacturing a mask on the passivation layer for the fifth time, and depositing the metal electrodes on the monocrystalline silicon substrate and the polycrystalline silicon film by using the mask through an electron beam evaporation process to finish the manufacture of the whole device.

2. The method of claim 1, wherein: the ion etching process conditions in the step A are as follows: CF (compact flash)₄The flow rate ranges from 15 sccm to 25sccm, the pressure ranges from 10 mT to 30mT, and the power ranges from 80W to 120W.

3. The method of claim 1, wherein: the plasma enhanced chemical vapor deposition process conditions in the step B are as follows: n is a radical of₂The flow rate of O is 800-900 sccm and SiH₄The flow rate is 200-300 sccm, the temperature is 250 ℃, the RF power is 25-40W, and the pressure is 1100-1300 mT.

4. The method of claim 1, wherein: the wet etching process conditions in the step G are as follows: h₃PO₄The concentration range of the solution is 90-92%, and the temperature range is 180-200 ℃.

5. The method of claim 1, wherein: the electron beam evaporation process condition in the step K is that the vacuum degree is less than 1.8 multiplied by 10^-3Pa, power range of 220-240W, evaporation rate less than

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