CN110504302A - A high-K metal gate structure and its manufacturing method - Google Patents

Abstract

The invention provides a high-K metal gate structure and a manufacturing method thereof. A TaN barrier layer is added between TiN and TiAl, so that the inside and outside of the TiN are protected by the TaN barrier layer, and the internally deposited filling metal layer cannot diffuse into the PMOS. The work function metal TiN layer improves the stability of the PMOS device. After the deposition of the newly added TaN barrier layer is completed, the NMOS structure is exposed through photolithography and etching processes, and the PMOS structure as a whole is protected by the sacrificial layer, and then the newly added TaN layer is fluorinated to replace the N element in the TaN layer , so that the TaN layer is completely formed into a TaFx compound, and removed by washing, so that the newly added TaN layer is completely removed without affecting other layers, thereby realizing the above-mentioned improved PMOS gate structure without affecting the NMOS structure.

Description

A high-K metal gate structure and its manufacturing method

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a high-K metal gate structure and a manufacturing method thereof.

Background technique

With the continuous reduction of transistor size and the continuous improvement of device performance requirements, HKMG (high dielectric constant dielectric/metal gate) technology has almost become a necessary technology for 28nm high-performance devices. In order to reduce gate leakage, reduce gate capacitance, and improve transistor performance, HKMG architecture and technical solutions are generally adopted at the 28nm technology node.

The high dielectric constant material replaces the traditional silicon dioxide, which has a high dielectric constant, and at the same time has the superior performance of silicon dioxide, good insulation, high temperature resistance, etc. High dielectric constant materials are poorly compatible with polysilicon. The Fermi level pinning effect caused by the interface defects between the two leads to an increase in the threshold voltage. The surface phonon scattering effect of the high-K value (High-K) material itself will cause the carrier Reduced mobility. Introducing metal instead of polysilicon gates can solve the above problems.

In the metal gate (metal gate) process, optimizing the work function of the metal electrode is an important means to adjust the performance of the device. In the gate-last technology, a dual-metal electrode technology is used to deposit metal films with different metal work functions for PMOS and NMOS respectively to obtain the best work function control. The work function metal of the PMOS tube is TiN, and the work function is close to the valence band. The work function metal of the NMOS tube is TiAl, and the work function is close to the conduction band. In order to protect the work function metal, the outside must be additionally covered with a barrier layer, such as TiN, TaN, Ta, etc.

As shown in Figures 1 to 6, the current mainstream foundry technology is to deposit P-type work function metal TaN/TiN first, expose the NMOS area by photolithography, and wet-etch away the P-type metal. Stop on TaN, then deposit N-type work function metal TiAl, and finally fill metal Al or W. The metals used here are all well-known materials in the industry, and the metal work function can only be adjusted through the deposition process to meet the different work function requirements of the valence band and the conduction band. Among them, the PMOS work function metal film layer is TiN/TaN/TiN, The NMOS work function metal is TiAlN formed by mutual diffusion of TiAl and TiN.

The existing HKMG manufacturing process is as follows: provide a silicon substrate, perform shallow trenches, polysilicon gates, and source-drain region forming processes in sequence, and perform chemical mechanical polishing (CMP) on the interlayer dielectric layer (ILD0). Gate removal; deposition of PMOS metal work function TiN; sequentially remove the TiN deposited in the NMOS area by photolithography and etching; deposit NMOS metal work function TiN/Ti in the NMOS and PMOS areas, and fill with Al, and finally perform the metal gate ( Metal gate) CMP process.

In the HKMG structure scheme, the work function metal in the PMOS gate structure is TiN, there is a layer of TaN barrier layer outside, and the inside is deposited and filled with TiAl layer and metal layer, and the TiAl layer is easy to diffuse into the work function metal layer TiN, and then Affect the stability of PMOS.

Therefore, it is necessary to propose a new high-K metal gate structure and a fabrication method thereof to solve the above problems.

Contents of the invention

In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a high-K metal gate structure and its manufacturing method, which is used to solve the problem that the work function metal in the PMOS gate structure in the prior art is TiN, and there is a The TaN barrier layer is deposited and filled with a TiAl layer and a metal layer inside, and the TiAl layer is easy to diffuse into the work function metal layer TiN, thereby affecting the stability of the PMOS.

In order to achieve the above object and other related objects, the present invention provides a high-K metal gate structure, at least comprising: a groove and an external barrier layer deposited in the groove; a metal work function layer deposited on the external barrier layer ; an internal barrier layer deposited on the metal work function layer; a metal compound layer deposited on the internal barrier layer; an adhesive layer deposited on the metal compound layer, filled in the groove, the The metal on the surface of the bonding layer.

Preferably, the high-K metal gate structure is a PMOS high-K metal gate.

Preferably, the outer barrier layer is a first TaN layer.

Preferably, the metal work function layer is a TiN layer.

Preferably, the inner barrier layer is a second TaN layer.

Preferably, the metal compound layer is a TiAl layer.

Preferably, the metal compound layer is a metal work function layer of the NMOS in the same manufacturing process as the PMOS.

Preferably, the adhesive layer is a stack of TiN and Ti.

Preferably, the metal is aluminium.

Preferably, the high-K metal gate structure further includes stacked layers located between the groove-shaped external barrier layer and the silicon substrate; the stacked layers are an interlayer dielectric layer, an HfO2 layer, and TiN layer.

Preferably, the thickness of the interlayer dielectric layer in the stack is 8-10 angstroms; the thickness of the HfO2 layer is 20 angstroms; and the thickness of the TiN layer is 20 angstroms.

The present invention also provides a method for fabricating the high-K metal gate structure. The method includes the following steps: Step 1: Provide grooves for fabricating PMOS and NMOS high-K metal gate structures respectively, and the grooves are located in the same semiconductor structure On; Step 2, depositing a first TaN layer on the semiconductor structure, the first TaN layer deposited in the groove forms a groove-shaped outer barrier layer; Step 3, depositing the first TaN layer on the first TaN layer A TiN layer is deposited on the top, and the TiN layer deposited in the groove for making the PMOS high-K metal gate structure forms a metal work function layer; step 4, depositing a second TaN layer on the TiN layer , the second TaN layer deposited in the groove for making the PMOS high-K metal gate structure forms an internal barrier layer; Step 5, using the photolithography and etching process to make the NMOS high-K metal gate structure The upper surface area of the groove of the gate structure is exposed; step 6, fluorinating the second TaN layer in the groove for making the NMOS high-K metal gate structure, so that it forms a TaFx compound; step 7 1. Washing to remove the TaFx compound; step 8, wet etching to remove the TiN layer in the groove for making the NMOS high-K metal gate structure; step 9, successively on the upper surface of the semiconductor structure and the Depositing a metal compound layer, an adhesive layer attached to the metal compound layer, and metal in the groove; Step 10, planarizing and grinding the upper surface of the semiconductor structure until the interlayer dielectric layer between the grooves is exposed.

Preferably, the semiconductor structure at least includes: a silicon substrate and a PWell region and an NWell region located on the silicon substrate; the PWell region and the NWell region are isolated by STI; the NMOS high-K metal gate structure is located Above the PWell region; the PMOS high-K metal gate structure is located above the NWell region; source and drain regions are formed on both sides of the PWell region and NWell region.

Preferably, the gas used in the fluoridation process in step six is produced by a combination of plasma gases containing CxFy, NF3, BF3, SiF4, Ar, H2, and N2.

Preferably, in step 8, hot SC1 cleaning solution is used to perform the wet etching.

Preferably, the hot SC1 cleaning solution includes deionized water, hydrogen peroxide, and NH ₄ OH.

Preferably, the ratio of deionized water, hydrogen peroxide and NH ₄ OH in the hot SC1 cleaning solution is 5:1.1:1.

Preferably, the temperature for performing the wet etching with hot SC1 cleaning solution in step 8 is 60 degrees Celsius.

Preferably, the metal compound layer in step 9 is a TiAl layer.

As mentioned above, the high-K metal gate structure and its manufacturing method of the present invention have the following beneficial effects: the present invention adds a layer of TaN barrier layer between TiN and TiAl, so that the inside and outside of TiN are protected by the TaN barrier layer, The internally deposited filling metal layer cannot diffuse into the PMOS work function metal TiN layer, which improves the stability of the PMOS device. After the work function TiN is deposited on the PMOS, this new TaN barrier layer is deposited. At the same time as the deposition of the TaN barrier layer inside the PMOS, this layer of TaN will also be deposited on the NMOS. It is necessary to remove the TaN and TiN on the NMOS side together, and do not damage to the outer barrier TaN layer. If the traditional pickling removal method is used, when removing the newly added TaN layer, since the etching rate of pickling for TiN is much greater than that of TaN, the lower TiN layer is easily removed together, making the outer barrier layer TaN Exposed and damaged by acid. The present invention also discloses the realization of the above-mentioned PMOS gate structure and the avoidance of damage to the NMOS structure. After the deposition of the new TaN barrier layer is completed, the NMOS structure is exposed through photolithography and etching processes, and the PMOS structure as a whole is protected by a sacrificial layer, and then the new TaN layer is fluorinated using plasma (Plasma) equipment , replacing the N element in the TaN layer, so that the TaN layer completely forms a TaFx compound, and is removed by washing, so that the newly added TaN layer is completely removed without affecting other layers. Furthermore, the above-mentioned improved PMOS gate structure is realized without affecting the NMOS structure.

Description of drawings

Fig. 1 shows that the present invention is used to make the semiconductor structure schematic diagram of PMOS high-K metal gate structure;

FIG. 2 shows a schematic structural view of removing the dummy gate to form a groove 01 in the semiconductor structure of the present invention;

FIG. 3 is a schematic structural diagram after depositing an external barrier layer and a metal work function layer on the semiconductor structure of the present invention;

Figure 4 shows a schematic diagram of the semiconductor structure after depositing an internal barrier layer on the metal work function layer in the present invention;

FIG. 5 is a schematic diagram of the semiconductor structure after the upper surface area of the groove used to make the NMOS high-K metal gate structure is exposed in the present invention;

FIG. 6 is a schematic diagram of the structure after removing the second TaN layer and the metal work function layer in the groove for making the NMOS high-K metal gate structure;

FIG. 7 is a schematic diagram of the structure after depositing a metal compound layer, an adhesive layer and a metal on the semiconductor structure in the present invention;

FIG. 8 is a schematic view of the surface of the semiconductor structure in the present invention after grinding;

9 is a schematic diagram of a PMOS high-K metal gate structure in the prior art;

10 is a schematic diagram of the PMOS high-K metal gate structure of the present invention;

FIG. 11 is a flow chart of the manufacturing method of the high-K metal gate structure of the present invention.

Detailed ways

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

See Figures 1 through 11. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.

The present invention provides a high-K metal gate structure. As shown in FIG. 8, the high-K metal gate structure at least includes: a groove and an external barrier layer 02 deposited in the groove; The metal work function layer 03 on the metal work function layer; the internal barrier layer 04 deposited on the metal work function layer 03; the metal compound layer 06 deposited on the internal barrier layer 04; the adhesive deposited on the metal compound layer 06 The composite layer 07 is filled in the groove and the metal 08 on the surface of the adhesive layer. As shown in FIG. 8 , the high-K metal gate structure is a PMOS high-K metal gate. In FIG. 8, the high-K metal gate of the PMOS and the high-K metal gate structure of the NMOS are formed on the same silicon substrate. The high-K metal gate structure of the NMOS is formed using the groove on the left side of FIG. 8 . The groove in the present invention is formed after removing the polysilicon through the dummy gate.

In the high-K metal gate structure of the PMOS, the outer barrier layer 02 deposited in the groove is a first TaN layer, that is, the material of the outer barrier layer is TaN, and the first TaN layer A layer of TaN is formed on the inner wall and bottom of the groove as a barrier layer. Therefore, the structural shape of the outer barrier layer 02 is also groove-shaped. A layer of metal work function layer 03 is deposited in the outer barrier layer, and the metal work function layer 03 is preferably a TiN layer in the present invention, that is, on the inner sidewall of the groove-shaped outer barrier layer 02 and A layer of TiN is deposited on the bottom to form the metal work function layer 03 of the present invention, and the metal work function layer 03 is also grooved.

As shown in Figure 8, the internal barrier layer 04 deposited on the metal work function layer 03, the internal barrier layer 04 is used as the second TaN layer of the PMOS high-K metal gate structure, that is, the internal barrier layer 04 In the present invention, a TaN layer is preferred. The second TaN layer is deposited on the inner sidewall and bottom of the inner barrier layer 04 , so the second TaN layer is also groove-shaped. The PMOS high-K metal gate structure further includes a metal compound layer 06 deposited on the internal barrier layer 04 , preferably in the present invention, the metal compound layer is a TiAl layer. That is, a layer of TiAl is deposited on the inner wall and bottom of the inner barrier layer 04, and the TiAl layer is also grooved. As shown in FIG. 8, since the NMOS high-K metal gate structure and the PMOS high-K metal gate structure are formed on the same silicon substrate, the two are in the same manufacturing process, and the metal compound layer TiAl is deposited The function is to use it as the metal work function layer of the NMOS in the same manufacturing process as the PMOS.

The PMOS high-K metal gate structure further includes an adhesive layer 07 deposited on the metal compound layer. Further in the present invention, the adhesive layer is a laminated layer composed of TiN and Ti. The PMOS high-K metal gate structure further includes metal filled in the groove and on the surface of the adhesive layer, and the metal is preferably aluminum. The function of the bonding layer is to better bond the metal aluminum and the metal compound TiAl layer together.

As shown in Figure 10, Figure 10 is an enlarged schematic diagram of the PMOS high-K metal gate structure described in Figure 8, and Figure 9 is a schematic diagram of the PMOS high-K metal gate structure in the prior art, the structure in Figure 9 and Figure 10 Compared with the high-K metal gate structure of the present invention, an internal barrier layer 04 is added between the metal compound layer 06 and the metal work function layer 03 to prevent the metal compound layer 06 (TiAl layer) from The work function layer 03 (TiN layer) is diffused. The stability of the PMOS device is improved.

As shown in FIG. 10 , further, the high-K metal gate structure of the present invention also includes stacked layers between the groove-shaped external barrier layer and the silicon substrate; the stacked layers are sequentially arranged from bottom to top For the interlayer dielectric layer, HfO ₂ layer, TiN layer. Furthermore, the thickness of the interlayer dielectric layer in the stack is 8-10 angstroms; the thickness of the HfO ₂ layer is 20 angstroms; and the thickness of the TiN layer is 20 angstroms.

The present invention also provides a method for manufacturing the high-K metal gate structure, as shown in FIG. 11 , which is a flow chart of the method for manufacturing the high-K metal gate structure of the present invention. The method includes the following steps:

Step 1, providing grooves for making PMOS and NMOS high-K metal gate structures respectively, the grooves are located on the same semiconductor structure; as shown in Figure 1, Figure 1 shows that the present invention is used to make PMOS high-K metal gate structures A schematic diagram of the semiconductor structure of the gate structure. In the semiconductor structure in FIG. 1 , the dummy gate has not been removed, so the grooves for making the PMOS and NMOS high-K metal gate structures have not been formed yet. The semiconductor structure includes a silicon substrate and a PWell region and an NWell region located on the silicon substrate; the PWell region and the NWell region are isolated by STI; the NMOS high-K metal gate structure is located in the PWell region above; the PMOS high-K metal gate structure is located above the NWell region; source and drain regions are formed on both sides of the PWell region and the NWell region.

As shown in Figure 2, what Figure 2 shows is the structure diagram of removing the dummy gate to form the groove 01 in the semiconductor structure of the present invention; there are multiple grooves on the semiconductor structure, which can be used to make PMOS high K metal gate structure and NMOS metal gate structure. For example, the groove at the right end in Figure 2 is used to form the PMOS high-K metal gate structure, and the groove at the left end of Figure 2 is used to form the NMOS high-K metal gate structure. After (chemical mechanical polishing), the dummy gate is removed and formed.

Step 2, depositing a first TaN layer on the semiconductor structure, the first TaN layer deposited in the groove forms a groove-shaped external barrier layer; as shown in Figure 3, Figure 3 shows the embodiment of the present invention A schematic diagram of the structure after depositing an external barrier layer and a metal work function layer on the semiconductor structure. While depositing the first TaN layer on the semiconductor structure, a layer of TaN is also deposited inside the groove, forming the The first TaN layer serves as an external barrier layer 02 of the PMOS high-K metal gate structure. The first TaN layer is not only deposited in the groove for making the PMOS high-K metal gate structure, but also deposited in the groove for making the NMOS high-K metal gate structure, and the semiconductor the upper surface of the structure.

Step 3, depositing a TiN layer on the first TaN layer, the TiN layer deposited in the groove for making the PMOS high-K metal gate structure forms a metal work function layer; as shown in Figure 3 As shown, the TiN layer deposited on the external barrier layer 02 serves as the metal work function layer 03 of the PMOS high-K metal gate structure. The metal work function layer 03 (TiN layer) is simultaneously deposited on the first TaN layer in the groove for making PMOS and NMOS high-K metal gate structures and on the first TaN layer on the upper surface of the semiconductor structure.

Step 4, depositing a second TaN layer on the TiN layer, the second TaN layer deposited in the groove for making the PMOS high-K metal gate structure forms an internal barrier layer; as shown in Figure 4, FIG. 4 is a schematic diagram of a semiconductor structure after depositing an internal barrier layer on the metal work function layer in the present invention. The internal barrier layer 04 is simultaneously deposited on the TiN layer in the groove for making PMOS and NMOS high-K metal gate structures and on the TiN layer on the upper surface of the semiconductor structure.

Step 5, using photolithography and etching processes to expose the upper surface area of the groove used to make the NMOS high-K metal gate structure; as shown in Figure 5, Figure 5 shows that the present invention will be used to make NMOS A schematic diagram of the semiconductor structure after the upper surface area of the groove of the high-K metal gate structure is exposed, and the upper surface area of the PMOS high-K metal gate structure is also covered with photoresist 05 . The entire PMOS structure area is protected by the sacrificial layer.

Step 6. Perform fluorination treatment on the second TaN layer in the groove for making the NMOS high-K metal gate structure to form a TaFx compound; the gas used in the fluorination treatment process in this step is composed of Combination of plasma gas containing CxFy, NF3, BF3, SiF4, Ar, H2, N2 is generated. A plasma (Plasma) device is used to perform fluorination treatment on the second TaN layer to replace the N element in the TaN layer, so that the TaN layer completely forms a TaFx compound.

Step 7, washing to remove the TaFx compound; the TaFx compound can be easily removed by water washing, so that the second TaN layer can be completely removed without affecting other layers. As shown in FIG. 6 , FIG. 6 is a schematic structural diagram after removing the second TaN layer and the metal work function layer in the groove used to fabricate the NMOS high-K metal gate structure. The first TaN layer (external barrier layer 02 ) is left in the groove for making the NMOS high-K metal gate structure. Washing with water allows removal of TaN in the NMOS region without damaging the TiN layer. If the traditional pickling removal method is used, when removing the second TaN layer, since the etching rate of pickling for TiN is much greater than that of TaN, the lower TiN layer is easily removed together, making the outer barrier layer The TaN is exposed and damaged by the acid.

Step 8, wet etching to remove the TiN layer in the groove used to make the NMOS high-K metal gate structure; as shown in Figure 6, Figure 6 shows the TiN layer that will be used to make the NMOS high-K metal gate structure Schematic diagram of the structure after removing the second TaN layer and metal work function layer in the groove. In step 8, the wet etching is carried out by using hot SC1 cleaning solution. Further, the hot SC1 cleaning solution includes deionized water, hydrogen peroxide, and NH ₄ OH. Furthermore, the ratio of deionized water, hydrogen peroxide, and NH ₄ OH in the hot SC1 cleaning solution in the present invention is: 5:1.1:1. And the ratio of deionized water, hydrogen peroxide and NH ₄ OH in the hot SC1 cleaning solution is: 5:1.1:1.

Step 9, sequentially depositing a metal compound layer, an adhesive layer attached to the metal compound layer, and metal on the upper surface of the semiconductor structure and in the groove; as shown in FIG. Schematic of the structure after depositing a metal compound layer, an adhesion layer, and metal on a semiconductor structure. Wherein the metal compound layer 06 is a TiAl layer, the bonding layer 07 is a stack of TiN and Ti, and the metal 08 deposited in this step is aluminum.

Step 10, planarizing and grinding the upper surface of the semiconductor structure until the interlayer dielectric layer between the grooves is exposed. As shown in FIG. 8 , FIG. 8 is a schematic view of the surface of the semiconductor structure in the present invention after grinding. Therefore, the outer barrier layer 02, the metal compound layer 06, the adhesive layer 07 and the metal 08 are deposited on the inner wall of the groove for making the NMOS high-K metal gate structure, while the PMOS high-K metal gate structure is made An outer barrier layer 02 , a metal work function layer 03 , an inner barrier layer 04 , a metal compound layer 06 , an adhesive layer 07 and a metal 08 are deposited on the inner wall of the groove.

In summary, the present invention adds a TaN barrier layer between TiN and TiAl, so that the inside and outside of TiN are protected by the TaN barrier layer, and the internal deposition filling metal layer cannot diffuse into the PMOS work function metal TiN layer, thereby improving the performance of PMOS devices. stability. After the work function TiN is deposited on the PMOS, this new TaN barrier layer is deposited. At the same time as the deposition of the TaN barrier layer inside the PMOS, this layer of TaN will also be deposited on the NMOS. It is necessary to remove the TaN and TiN on the NMOS side together, and do not damage to the outer barrier TaN layer. If the traditional pickling removal method is used, when removing the newly added TaN layer, since the etching rate of pickling for TiN is much greater than that of TaN, the lower TiN layer is easily removed together, making the outer barrier layer TaN Exposed and damaged by acid. The present invention also discloses the realization of the above-mentioned PMOS gate structure and the avoidance of damage to the NMOS structure. After the deposition of the new TaN barrier layer is completed, the NMOS structure is exposed through photolithography and etching processes, and the PMOS structure as a whole is protected by a sacrificial layer. Afterwards, plasma equipment is used to fluorinate the newly added TaN layer to replace TaN The N element in the layer makes the TaN layer completely form a TaFx compound. This compound can be easily removed by water washing, so that the newly added TaN layer can be completely removed without affecting other layers, thereby achieving the above-mentioned improvement. PMOS gate structure, and does not affect the NMOS structure. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention shall still be covered by the claims of the present invention.

Claims (19)

1. A high-K metal gate structure, characterized in that it at least comprises: A groove and an outer barrier layer deposited in the groove; a metal work function layer deposited on the outer barrier layer; an inner barrier layer deposited on the metal work function layer; an inner barrier layer deposited on the inner barrier layer Metal compound layer; an adhesive layer deposited on the metal compound layer, filled in the groove and the metal on the surface of the adhesive layer. 2 . The high-K metal gate structure according to claim 1 , wherein the high-K metal gate structure is a PMOS high-K metal gate. 3. The high-K metal gate structure according to claim 3, wherein the outer barrier layer is a first TaN layer. 4. The high-K metal gate structure according to claim 4, wherein the metal work function layer is a TiN layer. 5. The high-K metal gate structure according to claim 5, wherein the inner barrier layer is a second TaN layer. 6. The high-K metal gate structure according to claim 6, wherein the metal compound layer is a TiAl layer. 7 . The high-K metal gate structure according to claim 2 , wherein the metal compound layer is a metal work function layer of an NMOS in the same process as the PMOS. 8 . The high-K metal gate structure according to claim 1 , wherein the adhesive layer is a stack of TiN and Ti. 9. The high-K metal gate structure according to claim 1, wherein the metal is aluminum. 10. The high-K metal gate structure according to claim 6, characterized in that: the high-K metal gate structure further comprises a laminate between the recessed outer barrier layer and the silicon substrate; The stacked layers are an interlayer dielectric layer, an HfO2 layer, and a TiN layer in sequence from bottom to top. 11. The high-K metal gate structure according to claim 10, characterized in that: the thickness of the interlayer dielectric layer in the stack is 8-10 angstroms; the thickness of the HfO2 layer is 20 angstroms; The thickness of the TiN layer is 20 angstroms. 12. The method for manufacturing a high-K metal gate structure according to any one of claims 1 to 11, characterized in that the method comprises the following steps: Step 1, providing grooves for making PMOS and NMOS high-K metal gate structures respectively, and the grooves are located on the same semiconductor structure; Step 2, depositing a first TaN layer on the semiconductor structure, the first TaN layer deposited in the groove forms a groove-shaped external barrier layer; Step 3, depositing a TiN layer on the first TaN layer, the TiN layer deposited in the groove for making the PMOS high-K metal gate structure forms a metal work function layer; Step 4, depositing a second TaN layer on the TiN layer, the second TaN layer deposited in the groove for making the PMOS high-K metal gate structure forms an internal barrier layer; Step 5, using photolithography and etching processes to expose the upper surface area of the groove used to make the NMOS high-K metal gate structure; Step 6, performing fluorination treatment on the second TaN layer in the groove for making the NMOS high-K metal gate structure to form a TaFx compound; Step 7, washing to remove the TaFx compound; Step 8, wet etching to remove the TiN layer in the groove for making the NMOS high-K metal gate structure; Step 9, sequentially depositing a metal compound layer, an adhesive layer attached to the metal compound layer, and metal on the upper surface of the semiconductor structure and in the groove; Step 10, planarizing and grinding the upper surface of the semiconductor structure until the interlayer dielectric layer between the grooves is exposed. 13. The manufacturing method of the high-K metal gate structure according to claim 12, characterized in that: the semiconductor structure at least comprises: a silicon substrate and a PWell region and an NWell region located on the silicon substrate; the PWell The region and the NWell region are isolated by STI; the NMOS high-K metal gate structure is located above the PWell region; the PMOS high-K metal gate structure is located above the NWell region; the PWell region, the NWell region Both sides are formed with source and drain regions. 14. The manufacturing method of the high-K metal gate structure according to claim 13, characterized in that: the gas used in the fluorination process described in step 6 consists of CxFy, NF3, BF3, SiF4, Ar, H2, The plasma gas combination of N2 is produced. 15 . The method for fabricating a high-K metal gate structure according to claim 12 , wherein in step eighth, hot SC1 cleaning solution is used to perform the wet etching. 16 . 16 . The method for fabricating a high-K metal gate structure according to claim 15 , wherein the hot SC1 cleaning solution includes deionized water, hydrogen peroxide, and NH ₄ OH. 17 . The method for manufacturing a high-K metal gate structure according to claim 16 , wherein the ratio of deionized water, hydrogen peroxide, and NH ₄ OH in the hot SC1 cleaning solution is 5:1.1:1. 18 . The method for fabricating a high-K metal gate structure according to claim 17 , wherein in step eight, the temperature for performing the wet etching with hot SC1 cleaning solution is 60 degrees Celsius. 19 . 19. The method for manufacturing a high-K metal gate structure according to claim 12, wherein the metal compound layer in step 9 is a TiAl layer.