CN110504168A - A method for manufacturing a multi-slot gate lateral high-voltage power device - Google Patents

Abstract

The invention belongs to the technical field of power semiconductors, and in particular relates to a method for manufacturing a multi-slot gate lateral high-voltage power device. Compared with the traditional structure, the present invention has the N-type storage layer at the emitter end, the N-type buffer layer at the collector end, and the P-type well region at the emitter end and the collector end of the new structure, which can be pushed and completed synchronously to reduce the thermal budget cost of the device. ; The multi-slot gate structure of the emitter terminal and the collector terminal can also be manufactured simultaneously, and a multi-channel trench gate structure is formed at both ends of the device, so as to improve the turn-on voltage drop and turn-off loss of the device. The invention has the beneficial effects of simplifying device process steps and cost, and realizing easy integration and low power consumption SOI LIGBT.

Description

A method for manufacturing a multi-slot gate lateral high-voltage power device

technical field

The invention belongs to the technical field of power semiconductors, and relates to a method for manufacturing a multi-slot gate SOI LIGBT (Lateral Insulated Gate Bipolar Transistor, lateral insulated gate bipolar transistor).

Background technique

Insulated-gate bipolar transistor (IGBT) combines the advantages of high input impedance of MOS gate-controlled devices and low conduction voltage drop of bipolar devices to achieve high breakdown voltage and large conduction current, and has become a power electronic system Representative devices in the field, widely used in smart grid, high-speed rail drive, aerospace and household appliances and other fields. Due to the development of SOI technology, SOIL IGBT devices have smaller leakage currents and smaller parasitic effects, thus becoming the core components of monolithic power integrated chips.

As a bipolar device, the LIGBT device will have a conductance modulation effect when it is turned on, and a large number of carriers will be stored in the drift region. The problem of increased loss. In addition, the presence of parasitic thyristors in the body may cause latch-up of the device, thereby limiting the safe operating area. Therefore, improving the contradictory relationship between the IGBT's safe operating area, forward voltage drop, and turn-off loss has become a hot research topic.

Contents of the invention

The object of the present invention is to provide a method for manufacturing a multi-groove gate SOI LIGBT to solve the above problems. The technical solution of the present invention is: a method for manufacturing a multi-slot gate SOI LIGBT, which is characterized in that it comprises the following steps:

The first step: preparing SOI material, said SOI material includes bottom-up substrate layer 1, insulating dielectric layer 2 and N-type drift region 3;

Step 2: Implanting N-type impurities into one end of the surface of the N-type drift region 3 through ion implantation technology, and the impurity implantation windows are distributed in segmented patterns;

Step 3: Implanting N-type impurities into the other end of the surface of the N-type drift region 3 by ion implantation technology;

The fourth step: push the junction at high temperature simultaneously with the N-type impurity implanted in the second step and the third step, corresponding to form the N-type storage layer 41 at the emitter end and the N-type buffer layer 42 at the collector end;

Step 5: Implanting P-type impurities into the end of the N-type drift region 3 having the N-type storage layer 41 by ion implantation technology;

Step 6: Implanting P-type impurities above the N-type buffer layer 42 by ion implantation technology;

Step 7: Simultaneously push the P-type impurity implanted with neutrons in Step 5 and Step 6 into a high-temperature push-in junction, correspondingly forming the P-well 51 at the emitter end and the P-well 52 at the collector end;

Step 8: using an etching process to simultaneously etch multiple deep grooves at both ends of the N-type drift region 3 that are deeper than the P well 51 and the P well 52; and then using an oxidation process to form a gate dielectric layer on the side walls of the groove , followed by filling the deep groove with polysilicon material, planarization, and reverse patterning, and finally forming an interrupted or interconnected emitter control groove gate composed of the groove gate dielectric layer 81 and the groove gate polysilicon 82, consisting of the groove gate dielectric layer 83 and the groove gate dielectric layer 83. The emitter blocking groove gate composed of the groove gate polysilicon 84, the collector blocking groove gate composed of the groove gate dielectric layer 91 and the groove gate polysilicon 92, the discontinuous or interconnected collection composed of the groove gate dielectric layer 93 and the groove gate polysilicon 94 Electrode groove gate; wherein the etching window of the emitter control groove gate is located between the injection windows of the N-type storage layer 41;

Step 9: forming a P+ collector region 62 on the upper part of the N-type buffer layer 42 by ion implanting P-type impurities, and the groove gate dielectric 91 is in contact with the P+ collector region 62 on the side close to the emitter;

Step 10: Implanting N-type impurities by ion implantation to simultaneously pattern the N+ emitter region 71 on the upper part of the P well 51 and the N+ collector region 72 on the upper part of the P well 52, wherein the trench gate dielectric layer 81 In contact with the N+ emitter region 71, the groove gate dielectric layer 93 is in contact with the N+ collector region 72, and the groove gate dielectric layer 91 is in contact with the N+ collector region 72 at the end far away from the emitter;

The eleventh step: by ion implanting P-type impurities to simultaneously pattern the body contact P+ region 61 formed on the upper part of the P well 51 and the body contact P+ region 63 on the upper part of the P well 52, the contact P+ region 61 In contact with the N+ emitter region 71, the body contact P+ region 63 is in contact with the N+ collector region 72, and the groove gate dielectric layer 83 is in contact with the contact P+ region 61 at the end far away from the collector;

The twelfth step: form an emitter metal on the upper surface of the body contact P+ region 61, the N+ emitter region 71 and the groove gate polysilicon 84, and form an emitter metal on the P+ collector region 62, body contact P+ region 63, N+ collector The collector metal is formed on the upper surface of the electrical region 72 , the trench gate polysilicon 92 and the trench gate polysilicon 94 , and the gate metal is formed on the upper surface of the trench gate polysilicon 82 ;

Further, the manufacturing method of a multi-groove gate SOI LIGBT according to claim 1 is characterized in that: after the deep groove etching step described in the eighth step, the deep groove near the N-type storage layer 41 P-type impurities are implanted into the groove bottom to form a P-type buried layer 53 .

Further, according to any one of the manufacturing methods of multi-groove gate SOI LIGBT described in claims 1-2, it is characterized in that: the discontinuous or interconnected emitter control groove gate, discontinuity or interconnection formed in the eighth step The shape of the collector grid can be rectangular, rhombus or hexagonal;

The beneficial effect of the present invention is that, compared with the traditional LIGBT structure, the new structure has high compatibility between the process steps of the emitter terminal and the collector terminal, and not only effectively eliminates the snapback phenomenon when it is turned on, but also enhances the carrier injection efficiency and the resistance of the emitter terminal of the device. Latch-up capability, and achieve faster turn-off speed and lower turn-off loss.

Description of drawings

Figure 1 is SOI material preparation;

FIG. 2 is an N-type impurity implantation to form an N-type buffer layer and an N-type storage layer;

Figure 3 shows the P-well regions at both ends formed by P-type impurity implantation;

Fig. 4 shows multi-groove gate etching, gate oxide layer growth, and polysilicon deposition;

Figure 5 shows the P+ collector region formed by P-type impurity implantation;

Figure 6 is the formation of N+ emitter region, N+ collector region, body contact P+ region;

Fig. 7 is the electrode metal interconnection;

Figure 8 is the ion implantation at the bottom of the emitter trench gate to form a P-type buried layer;

Figures 9 and 10 show the layout of the intermittently distributed emitter control slots and collector slots as rectangles or hexagons;

Fig. 11 is a rectangular layout layout interconnection type emitter control slot gate and collector slot gate;

Detailed ways

Below in conjunction with accompanying drawing and embodiment, describe technical solution of the present invention in detail:

Example 1

The manufacturing process of the multi-groove gate SOI LIGBT device in this example is as follows:

A method for manufacturing multi-groove gate SOI LIGBT, characterized in that it comprises the following steps:

The first step: preparing SOI material, the SOI material includes a bottom-up substrate layer 1, an insulating dielectric layer 2 and an N-type drift region 3, as shown in Figure 1;

Step 2: Implanting N-type impurities into one end of the surface of the N-type drift region 3 through ion implantation technology, and the impurity implantation windows are distributed in segmented patterns;

Step 3: Implanting N-type impurities into the other end of the surface of the N-type drift region 3 by ion implantation technology;

Step 4: The N-type impurity ion-implanted in the second step and the third step are simultaneously subjected to high-temperature push junction, correspondingly forming the N-type storage layer 41 at the emitter end and the N-type buffer layer 42 at the collector end, as shown in FIG. 2 Show;

Step 5: Implanting P-type impurities into the end of the N-type drift region 3 having the N-type storage layer 41 by ion implantation technology;

Step 6: Implanting P-type impurities above the N-type buffer layer 42 by ion implantation technology;

Step 7: Simultaneously push the P-type impurity implanted with neutrons in the fifth and sixth steps into a junction at high temperature, correspondingly forming a P-well 51 at the emitter end and a P-well 52 at the collector end, as shown in FIG. 3 ;

Step 8: using an etching process to simultaneously etch multiple deep grooves at both ends of the N-type drift region 3 that are deeper than the P well 51 and the P well 52; and then using an oxidation process to form a gate dielectric layer on the side walls of the groove , followed by filling the deep groove with polysilicon material, planarization, and reverse patterning, and finally forming an interrupted or interconnected emitter control groove gate composed of the groove gate dielectric layer 81 and the groove gate polysilicon 82, consisting of the groove gate dielectric layer 83 and the groove gate dielectric layer 83. The emitter blocking groove gate composed of the groove gate polysilicon 84, the collector blocking groove gate composed of the groove gate dielectric layer 91 and the groove gate polysilicon 92, the discontinuous or interconnected collection composed of the groove gate dielectric layer 93 and the groove gate polysilicon 94 An electrode groove gate; wherein the etching window of the emitter control groove gate is located between the injection windows of the N-type storage layer 41, as shown in FIG. 4 ;

Step 9: Form a P+ collector region 62 on the upper part of the N-type buffer layer 42 by ion implanting P-type impurities, and the groove gate dielectric 91 is in contact with the P+ collector region 62 on the side close to the emitter, as As shown in Figure 5;

Step 10: Implanting N-type impurities by ion implantation to simultaneously pattern the N+ emitter region 71 on the upper part of the P well 51 and the N+ collector region 72 on the upper part of the P well 52, wherein the trench gate dielectric layer 81 In contact with the N+ emitter region 71, the groove gate dielectric layer 93 is in contact with the N+ collector region 72, and the groove gate dielectric layer 91 is in contact with the N+ collector region 72 at the end far away from the emitter;

The eleventh step: by ion implanting P-type impurities to simultaneously pattern the body contact P+ region 61 formed on the upper part of the P well 51 and the body contact P+ region 63 on the upper part of the P well 52, the contact P+ region 61 In contact with the N+ emitter region 71, the body contact P+ region 63 is in contact with the N+ collector region 72, and the groove gate dielectric layer 83 is in contact with the contact P+ region 61 at the end far away from the collector, as shown in Figure 6 shown;

The twelfth step: form an emitter metal on the upper surface of the body contact P+ region 61, the N+ emitter region 71 and the groove gate polysilicon 84, and form an emitter metal on the P+ collector region 62, body contact P+ region 63, N+ collector The collector metal is formed on the upper surface of the electrical region 72, the trench gate polysilicon 92 and the trench gate polysilicon 94, and the gate metal is formed on the upper surface of the trench gate polysilicon 82, as shown in FIG. 7;

This example works as follows:

In terms of process preparation, the groove gate structure of the emitter terminal and the collector terminal of the new device is produced synchronously, and the N-type storage layer 41 and N-type buffer layer 42, and the P-well region 51 and P-well region 52 can be respectively pushed and completed synchronously to reduce Device thermal budget cost. When the new device is forward-conducting, the N+ collector region 72 is surrounded by the P well region 52 and the collector groove gate structure, the groove gate polysilicon layer 92 in the collector groove gate is short-circuited with the collector, and the collector groove gate channel is turned off. The path corresponding to the N+ collector region 72 and the N-type buffer layer 42 is blocked, so the snapback effect is eliminated when the new device is conducting forward. The blocking groove gate and the control groove gate play a physical blocking role, and the N-type storage layer 41 between the groove gates can be used as a hole barrier, which can prevent holes from passing through the P well region 51 at the emitter end and being rapidly absorbed by the P+ body contact region 61. Pumping away is beneficial to increase the carrier concentration in the drift region. At the same time, the segmented control of the trench gate can increase the channel density of the device to reduce the resistance of the channel region. Under the combined effect, the V _on of the device can be significantly reduced. Different from the traditional planar gate structure LIGBT, the emitter of the new structure adopts a trench gate structure, and only a small part of the hole current flows under the N+ collector region 72, thus greatly improving the anti-latch-up capability of the device. During the shutdown process of the device, as the collector voltage rises, the channel on the sidewall of the collector groove gate will gradually open, and the electrons will be quickly extracted through the N-type buffer layer 42-the sidewall channel of the collector groove gate-N+collector region 72 The path is opened, and at the same time, a hole bypass is formed by blocking the groove gate from contacting the P+ body contact region 61 , both of which can accelerate device turn-off and reduce E _off . In the off state of the device, the short-circuit between the collector slot gate and the collector is at a high potential, the channel on the side wall of the collector slot gate is opened, and the N+ collector region 72 is equivalently connected to the N-type buffer layer 42 and is almost equipotential, so that the new The device structure has a MOS-like unipolar breakdown mode, which reduces the influence of the P+ collector region 62 on the withstand voltage of the device.

The beneficial effect of the present invention is that, compared with the traditional short-circuited anode-LIGBT structure, the new structure has high compatibility between the process steps of the emitter terminal and the collector terminal, and not only effectively eliminates the snapback phenomenon when it is turned on, but also enhances carrier injection at the emitter terminal of the device Efficiency and anti-latch-up ability, and achieve faster turn-off speed and lower turn-off loss.

Example 2

As shown in FIG. 8 , the difference between this example and FIG. 4 in Example 1 is that in this example, in the eighth step, ion implantation at the bottom of the emitter-side control slot gate and the blocking slot gate forms a P-type buried layer 53 . The working mechanism of device shutdown in this embodiment is consistent with that of Embodiment 1, the difference is that: when conducting forward conduction, the P-type buried layer 53 introduced in this example can assist in depleting the N-type storage layer 41, thereby improving the efficiency of the N-type storage layer. 41 Optimize the doping concentration and enhance the carrier storage effect, so in this example, the carrier concentration in the drift region of the device is higher, and the conduction voltage drop can be further reduced; at the same time, in the blocking state, the P-type buried layer 53 can also The electric field peak at the bottom of the emitter groove gate structure is reduced, and the reliability of the device is improved. Therefore, compared with Example 1, the new device in this example can obtain a lower forward conduction voltage drop and improve the reliability of the trench gate structure at the emitter terminal.

Example 3

As shown in Figures 9 and 10, the difference between this example and Figure 7 in Embodiment 1 is that the layout of the emitter control slots and the collector slots can be a rectangular or hexagonal discontinuous distribution; Figure 11 shows The emitter control slots and the collector slots are respectively interconnected in a rectangular layout, and of course the emitter control slots and the collector slots may also be interconnected in a hexagonal layout. The device turn-off working mechanism in this embodiment is the same as that in Embodiment 1, the difference is that the shape of the groove gate can change the channel density of the device, which is beneficial to design the turn-on voltage drop and turn-off loss of the device.

Claims (3)

1. a kind of multiple-grooved grid transverse direction high voltage power device manufacturing method, which comprises the following steps:

Step 1: preparing SOI material, the SOI material includes substrate layer (1), insulating medium layer (2) and N-type from bottom to top Drift region (3)；

Step 2: N-type impurity is injected in the one end on the N-type drift region (3) surface, by ion implantation technique with three-dimensional straight Angular coordinate system is defined the three-dimensional of device: definition device transverse direction is x-axis direction, device vertical direction is y-axis Direction, device longitudinal direction, that is, third dimension direction are z-axis direction, and along the z-axis direction, the injection window of N-type impurity is in piecewise graph Distribution；

Step 3: the other end on the N-type drift region (3) surface injects N-type impurity by ion implantation technique；

Step 4: the N-type impurity of second step and the injection of third step intermediate ion is carried out high temperature knot simultaneously, it is correspondingly formed emitter The N-type accumulation layer (41) at end and the N-type buffer layer (42) of collector terminal；

Step 5: in the N-type drift region (3) there is one end of the N-type accumulation layer (41) to inject by ion implantation technique P type impurity；

Step 6: by ion implantation technique, the injecting p-type impurity above the N-type buffer layer (42)；

Step 7: the p type impurity that the 5th step and the 6th step neutron are injected is carried out high temperature knot simultaneously, it is correspondingly formed emitter terminal P-well (51) and collector terminal p-well (52)；

Step 8: etching multiple depth simultaneously more than the p-well (51) at the N-type drift region (3) both ends using etching technics With the deep trouth of p-well (52)；Then gate dielectric layer is formed in groove sidewall using oxidation technology, polysilicon material is then filled in deep trouth It anti-carves graphical after material, planarization, eventually forms the interruption being made of slot gate dielectric layer (81) and slot gate polysilicon (82) or mutual Emitter control flume grid even stop slot grid by the emitter that slot gate dielectric layer (83) and slot gate polysilicon (84) form, by slot The collector of gate dielectric layer (91) and slot gate polysilicon (92) composition stops slot grid, by slot gate dielectric layer (93) and slot gate polysilicon (94) the collector slot grid of the interruption or interconnection that form；Wherein the etching window of the emitter control flume grid is located at the N-type Between the injection window of accumulation layer (41)；

Step 9: P+ collecting zone (62) are formed on N-type buffer layer (42) top by ion implanting p type impurity, the slot Gate medium (91) is contacted in the side close to emitter with the P+ collecting zone (62)；

Step 10: being graphically formed in the N+ emitter region (71) on the p-well (51) top simultaneously by ion implanting N-type impurity With the N+ collecting zone (72) on the p-well (52) top, wherein the slot gate dielectric layer (81) connects with the N+ emitter region (71) Touching, the slot gate dielectric layer (93) contact with the N+ collecting zone (72), and the slot gate dielectric layer (91) is far from emitter terminal It is contacted with the N+ collecting zone (72)；

Step 11: contacting the area P+ by ion implanting p type impurity with the body for being graphically formed in the p-well (51) top simultaneously (61) area P+ (63) are contacted with the body on the p-well (52) top, the area contact P+ (61) connects with the N+ emitter region (71) Touching, the body contact area P+ (63) contact with the N+ collecting zone (72), and the slot gate dielectric layer (83) is far from collector terminal It is contacted with the area contact P+ (61)；

Step 12: contacting the upper surface shape of the area P+ (61), the N+ emitter region (71) and slot gate polysilicon (84) in the body At emitter metal, the P+ collecting zone (62), the body contact area P+ (63), N+ collecting zone (72), slot gate polysilicon (92) with The upper surface of slot gate polysilicon (94) forms collector electrode metal, forms grid gold in the upper surface of the slot gate polysilicon (82) Belong to.

2. a kind of multiple-grooved grid transverse direction high voltage power device manufacturing method according to claim 1, it is characterised in that: the 8th step Described in deep etching step after, in the deep trouth bottom ion implanting p type impurity of the N-type accumulation layer (41) nearby to be formed P type buried layer (53).

3. a kind of multiple-grooved grid transverse direction high voltage power device manufacturing method according to claim 1 or 2, it is characterised in that: the The shape of the emitter control flume grid of the interruption or interconnection formed in eight steps, interruption or the collector of interconnection slot grid is rectangle, water chestnut Shape or hexagon.