CN110502061A - An Ultra-Low Power Consumption Reference Circuit - Google Patents

Abstract

The invention discloses a kind of super low-power consumption reference circuits, comprising: a start-up circuit, for starting the reference circuit；One core circuit, optimization has used three branch current structures in current-mirror structure, and the different gate oxide thicknesses metal-oxide-semiconductor of simultaneous selection eliminates temperature influence, obtains stable reference current；One output circuit, series stack transistor, is exaggerated reference voltage.A kind of super low-power consumption reference circuit of the present invention, does not use resistance, also without using triode, entirely MOS transistor, the advantages that it is small to possess area, low pressure and super low-power consumption.

Description

An Ultra-Low Power Consumption Reference Circuit

technical field

The invention relates to the field of reference voltage circuits, in particular to an ultra-low power consumption reference circuit.

Background technique

In the Internet of Things, EEPROM and most wireless communication applications, the relevant receiving circuits or transmitting circuits require low power consumption, so a reference circuit that can generate low power consumption is very critical and necessary for the entire application . As an important part of the analog circuit, the reference circuit generally needs to work normally in a wide temperature range. Therefore, not only low power consumption is required, but also stable performance and good temperature characteristics are required. The traditional method can be designed with a bandgap reference circuit, but its power consumption is at the microwatt level, which does not belong to the low-power design category.

Contents of the invention

In order to overcome the above-mentioned problems in the prior art, the main purpose of the present invention is to provide an ultra-low power consumption reference circuit, which has the advantages of low voltage, ultra-low power consumption and smaller silicon area.

In order to achieve the above and other purposes, the present invention provides an ultra-low power consumption reference circuit, which at least includes:

A start-up circuit for starting the reference circuit; a core circuit, which optimizes the use of a three-branch current structure on the current mirror structure, and selects different gate oxide thickness MOS tubes at the same time, eliminating the influence of temperature and obtaining a stable Reference current; an output circuit, stacking transistors in series, amplifies the reference voltage.

The present invention proposes an ultra-low power consumption reference circuit, comprising: the startup circuit is composed of a first PMOS transistor PM1, a first NMOS transistor NM1, a second NMOS transistor NM2, and a third NMOS transistor NM3; the source of the PM1 transistor Connect the power supply voltage VDD; the gate of the PM1 tube is connected to the drain of the PM1 tube, and the gate of the NM1 tube is connected to the drain of the NM1 tube; the source of the NM1 tube is connected to the gate of the NM2 tube and the drain of the NM3 tube Connection; the source of the NM2 tube and the source of the NM3 tube are grounded.

The core circuit consists of the second PMOS transistor PM2, the third PMOS transistor PM3, the fourth PMOS transistor PM4, the fifth PMOS transistor PM5, the sixth PMOS transistor PM6, the seventh PMOS transistor PM7, the thirteenth PMOS transistor PM13, the fourth The NMOS tube NM4, the fifth NMOS tube NM5, the sixth NMOS tube NM6 and the seventh NMOS tube NM7 are composed; the source of the PM2 tube, the source of the PM4 tube and the source of the PM6 tube are all connected to the power supply voltage VDD; the PM2 tube The gate and the gate of the PM3 tube, the drain of the PM3 tube, the drain of the NM2 tube, the drain of the NM4 tube, the grid of the PM4 tube, the grid of the PM5 tube, the grid of the PM6 tube and the grid of the PM7 tube The drain of the PM2 tube is connected to the source of the PM3 tube; the drain of the PM4 tube is connected to the source of the PM5 tube; the drain of the PM6 tube is connected to the source of the PM7 tube; the drain of the PM5 tube The pole is connected to the drain of the NM5 tube, the grid of the NM5 tube is connected to the grid of the NM6 tube; the drain of the PM7 tube is connected to the grid of the NM4 tube, the grid of the NM7 tube, and the drain of the NM6 tube; the drain of the NM4 tube The source of the NM5 tube is connected to the source of the PM13 tube; the source of the NM7 tube, the drain of the NM7 tube, the drain of the PM13 tube, the gate of the PM13 tube and the source of the NM6 tube are all grounded.

The output circuit is composed of the eighth PMOS transistor PM8, the ninth PMOS transistor PM9, the tenth PMOS transistor PM10, the eleventh PMOS transistor PM11 and the twelfth PMOS transistor PM12; the source of the PM8 transistor is connected to the power supply voltage VDD; the PM8 transistor The grid of the PM2 tube is connected to the grid of the PM9 tube; the drain of the PM8 tube is connected to the source of the PM9 tube; the drain of the PM9 tube is connected to the source of the PM10 tube and the grid of the NM3 tube Connection, whose node is marked as A, as the output terminal of the reference voltage VREF; the gate of the PM10 tube is connected to the drain of the PM10 tube and the source of the PM11 tube; the gate of the PM11 tube is connected to the drain of the PM11 tube and the PM12 tube The source of the tube is connected; the gate of the PM12 tube and the drain of the PM12 tube are grounded.

Description of drawings

The accompanying drawings constituting a part of this application are used to provide further understanding of the present invention, and the schematic embodiments and descriptions of the present invention are used to explain the present invention, and do not constitute an improper limitation of the present invention. In the attached picture:

Fig. 1 is an ultra-low power consumption reference circuit diagram of the present invention.

Detailed ways

As shown in FIG. 1, in the following embodiments, the ultra-low power consumption reference circuit at least includes: a start-up circuit for starting the reference circuit; a core circuit, which optimizes the use of the current mirror structure Three-branch current structure, while selecting MOS transistors with different gate oxide thicknesses, eliminates the influence of temperature and obtains a stable reference current; an output circuit, stacking transistors in series, amplifies the reference voltage. In actual circuit design, the NM5 tube chooses a MOS tube with a thick gate oxide, and its threshold is relatively large.

The start-up circuit is composed of the first PMOS transistor PM1, the first NMOS transistor NM1, the second NMOS transistor NM2 and the third NMOS transistor NM3; both the PM1 transistor and the NM1 transistor adopt the diode connection method, and are forward-conducting, and the grid of the NM2 transistor When the high potential is obtained, the NM2 tube is turned on, and the gate voltage of the PM2 tube and the PM8 tube connected to it are pulled down, and the core circuit and the output circuit are started. When the whole circuit works stably and VREF outputs a normal value, the gate of NM3 tube gets a high potential, NM3 tube is turned on, the gate voltage of NM2 tube is pulled down, and NM2 tube is turned off, thereby closing the startup circuit, and the whole startup circuit is also Startup is done.

The core circuit consists of the second PMOS transistor PM2, the third PMOS transistor PM3, the fourth PMOS transistor PM4, the fifth PMOS transistor PM5, the sixth PMOS transistor PM6, the seventh PMOS transistor PM7, the thirteenth PMOS transistor PM13, the fourth The NMOS tube NM4, the fifth NMOS tube NM5, the sixth NMOS tube NM6 and the seventh NMOS tube NM7; the branch circuit composed of PM4 tube, PM5 tube, NM5 tube and the branch circuit composed of PM6 tube, PM7 tube, NM6 tube Constitutes a traditional current mirror structure. In order to solve the current mirror mismatch and OPAMP offset, the circuit adds another negative feedback branch composed of PM2 tube, PM3 tube, and NM4 tube to ensure that I1 is equal to I2. Because of the existence of NM4 tube, three The current difference of the branches is amplified, but since the gain obtained by the two negative feedback branches is greater than that of the positive feedback branch, there is no offset. The NM6 tube of the NM5 tube has selected different oxide thicknesses, so that the two have opposite temperature characteristics, further eliminating the temperature effect. The NM7 tube is used as a capacitor for stability compensation. At the same time, the circuit adopts a self-cascode structure, which improves the accuracy of the branch current ratio and the power supply rejection ratio. In a traditional bias circuit, the source of the NM5 tube is connected to a resistor of about 100k ohms, so that the NM5 tube works in the sub-threshold region, making the branch circuit current small, for example, the branch current is 2uA, then in The voltage drop on this resistor is 200mv; and in the present invention, the source of the NM5 tube is not directly connected to the resistor, but a MOS tube connected to a diode, so the voltage drop is the threshold value of the MOS tube, which is marked in the figure △VGS, in the 0.18μm process, the △VGS of the PMOS tube is generally about 0.6V, so the NM5 tube works in a more sub-threshold area, and the branch current is even smaller. The simulation results show that the branch current is only 14nA, Therefore, the current consumed by the whole circuit is very small, and the power consumption is also very small. Use PM13 tube instead of resistor, and save current and chip area.

The output circuit is composed of the eighth PMOS transistor PM8, the ninth PMOS transistor PM9, the tenth PMOS transistor PM10, the eleventh PMOS transistor PM11 and the twelfth PMOS transistor PM12; three layers of MOS transistors are stacked in series, so VREF is NM5 Three times the VGS between the NM6 tube and the NM6 tube, this multiple can be adjusted by adjusting the stacked MOS tubes in series.

The present invention proposes a non-impedance ultra-low power consumption reference circuit, the circuit is designed with 0.18μm CMOS technology, the entire circuit area is only 0.0094mm ^2, after circuit simulation, the entire circuit has only 50nA quiescent current, which belongs to low power Power consumption reference circuit, the circuit can work with a supply voltage as low as 1V to 2.5V, and provide an output voltage of 600mV in the range of -25°C to 125°C. When the power supply voltage is 1V, the power consumption is only 55nW at room temperature.

Although the invention has been described using specific examples, the description of the examples does not limit the scope of the invention. Those skilled in the art can easily make various modifications or combine the embodiments without departing from the spirit and scope of the present invention by referring to the description of the present invention, and these should also be regarded as the protection scope of the present invention .

Claims (4)

1. a kind of super low-power consumption reference circuit characterized by comprising

One start-up circuit, for starting the reference circuit；One core circuit, optimization has used three branches in current-mirror structure Circuit configuration, the different gate oxide thicknesses metal-oxide-semiconductor of simultaneous selection eliminate temperature influence, obtain stable reference current； One output circuit, series stack transistor finally generate accurately reference voltage on the basis of reference current.

2. super low-power consumption reference circuit as described in claim 1, it is characterised in that: the start-up circuit is by the first PMOS tube PM1, the first NMOS tube NM1, the second NMOS tube NM2 and third NMOS tube NM3 are constituted；The source electrode of PM1 pipe connects supply voltage VDD；The drain electrode of the grid and PM1 pipe of PM1 pipe, the grid of NM1 pipe are connected with the drain electrode of NM1 pipe；The source electrode of NM1 pipe with The grid of NM2 pipe is connected with the drain electrode of NM3 pipe；The source electrode of NM2 pipe and the source electrode ground connection of NM3 pipe.

3. super low-power consumption reference circuit as described in claim 1, it is characterised in that: the core circuit is by the second PMOS tube PM2, third PMOS tube PM3, the 4th PMOS tube PM4, the 5th PMOS tube PM5, the 6th PMOS tube PM6, the 7th PMOS tube PM7, 13 PMOS tube PM13, the 4th NMOS tube NM4, the 5th NMOS tube NM5, the 6th NMOS tube NM6 and the 7th NMOS tube NM7 are constituted； The source electrode of PM2 pipe, the source electrode of PM4 pipe and the source electrode of PM6 pipe are all connected with supply voltage VDD；The grid and PM3 of PM2 pipe are managed Grid, the drain electrode of PM3 pipe, the drain electrode of NM2 pipe, the drain electrode of NM4 pipe, the grid of PM4 pipe, the grid of PM5 pipe, the grid of PM6 pipe Pole is connected with the grid of PM7 pipe；The drain electrode of PM2 pipe is connected with the source electrode of PM3 pipe；The drain electrode of PM4 pipe and the source electrode of PM5 pipe It is connected；The drain electrode of PM6 pipe is connected with the source electrode of PM7 pipe；Drain electrode and the drain electrode of NM5 pipe of PM5 pipe, the grid of NM5 pipe and The grid of NM6 pipe is connected；The drain electrode and the grid of NM4 pipe, the drain electrode of the grid of NM7 pipe, NM6 pipe of PM7 pipe are connected；NM4 The source electrode of pipe is connected with the source electrode of the source electrode of NM5 pipe and PM13 pipe；The source electrode of NM7 pipe, the drain electrode of NM7 pipe, the leakage of PM13 pipe Pole, the grid of PM13 pipe and the source electrode of NM6 pipe are all grounded.

4. super low-power consumption reference circuit as described in claim 1, it is characterised in that: the output circuit is by the 8th PMOS tube PM8, the 9th PMOS tube PM9, the tenth PMOS tube PM10, the 11st PMOS tube PM11 and the 12nd PMOS tube PM12 are constituted；PM8 pipe Source electrode connect supply voltage VDD；The grid of PM8 pipe is connected with the grid of the grid of PM2 pipe and PM9 pipe；The drain electrode of PM8 pipe It is connected with the source electrode of PM9 pipe；The drain electrode of PM9 pipe is connected with the grid of the source electrode of PM10 pipe and NM3 pipe, and node label is A, the output end as reference voltage VREF；The grid of PM10 pipe is connected with the source electrode of the drain electrode of PM10 pipe and PM11 pipe； The grid of PM11 pipe is connected with the source electrode of the drain electrode of PM11 pipe and PM12 pipe；The drain electrode of the grid and PM12 pipe of PM12 pipe all connects Ground.