CN110491945B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The application discloses a semiconductor device and a manufacturing method thereof, and belongs to the technical field of semiconductors. The semiconductor device sequentially comprises a bottom layer, an isolation layer and a pattern layer along the thickness direction of the semiconductor device; the pattern layer comprises a top layer structure, a first N-type region, a first grid electrode, a second grid electrode, a P-type well, an N-type drift region and a second N-type region; the first grid electrode and the second grid electrode are oppositely arranged along the width direction of the semiconductor device, and the first N-type region, the P-type well, the N-type drift region and the second N-type region are positioned between the first grid electrode and the second grid electrode; the first N-type region, the P-type well, the N-type drift region and the second N-type region are sequentially arranged along the length direction of the semiconductor device. According to the application, the threshold voltage of the semiconductor device is reduced by arranging the first grid electrode and the second grid electrode in parallel; meanwhile, leakage prevention capability of the semiconductor device is improved by arranging the isolation layer.

Description

Semiconductor device and manufacturing method thereof

technical field

The present application relates to the field of semiconductor technology, in particular to a semiconductor device and a manufacturing method thereof.

Background technique

In semiconductor integrated circuits, the circuit based on double-diffused field-effect transistors is called double-diffused metal oxide semiconductor (Double-diffused Metal Oxide Semiconductor, DMOS), which uses the difference in lateral diffusion speed of two impurity atoms to form a self-pair Accurate sub-micron channel can achieve higher operating frequency and speed.

In the related art, DMOS devices are usually provided with an N-type drift region (N Drift) to increase the operating voltage (V _DD ) of the semiconductor device. However, with the increase of V _DD , the leakage problem of the DMOS device is caused, and it also causes the DMOS device The threshold voltage (V _t ) is higher.

Contents of the invention

Embodiments of the present application provide a semiconductor device and a manufacturing method thereof, which can solve the problems of high threshold voltage and electric leakage of the semiconductor device provided in the related art.

On the one hand, an embodiment of the present application provides a semiconductor device, including:

Along the thickness direction of the semiconductor device, sequentially comprising a bottom layer, an isolation layer and a pattern layer;

The pattern layer includes a top layer structure, a first N-type region, a first gate, a second gate, a P-type well, an N-type drift region and a second N-type region;

Along the width direction of the semiconductor device, the first gate and the second gate are arranged oppositely, and the first N-type region, the P-type well, the N-type drift region and the second An N-type region is located between the first gate and the second gate;

The first N-type region, the P-type well, the N-type drift region and the second N-type region are sequentially arranged along the length direction of the semiconductor device.

In an optional embodiment, the isolation layer includes a silicon oxide layer.

In an optional embodiment, the top layer structure includes a silicon top layer structure, and the bottom layer includes a silicon bottom layer.

In one aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, the method comprising:

A substrate is provided, and along the thickness direction of the substrate, the substrate sequentially includes a bottom layer, an isolation layer and a top layer;

performing the first ion implantation and the second ion implantation sequentially along the length direction of the substrate, respectively forming a P-type well and an N-type drift region in the top layer;

A first channel and a second channel are formed on the top layer by an etching process, and the first channel and the second channel are sequentially located in the P-type well and the Both sides of the N-type drift region;

Filling polysilicon in the first trench to form a first gate, filling polysilicon in the second trench to form a second gate;

Performing a third ion implantation on the top layer in a region close to the first gate and the second gate along the length direction of the substrate to form a first N-type region;

Performing fourth ion implantation on the top layer in a region close to the N-type drift region along the length direction of the substrate to form a second N-type region, the top layer except the first N-type region, the The first gate, the second gate, the P-type well, and other regions of the N-type drift region form a top layer structure.

In an optional embodiment, before filling the first trench with polysilicon to form a first gate, and filling the second trench with polysilicon to form a second gate, the method further includes:

A gate oxide layer is formed on surfaces of the first channel, the second channel, the P-type well, the N-type drift region and the top layer.

In an optional embodiment, filling the first trench with polysilicon to form a first gate, and filling the second trench with polysilicon to form a second gate include:

filling the polysilicon in the first channel through a furnace tube, and filling the polysilicon in the second channel through the furnace tube;

The polysilicon is planarized by a chemical mechanical polishing (CMP) process to obtain the first gate and the second gate.

In an optional embodiment, the third ion implantation is lightly doped drain LDD ion implantation.

In an optional embodiment, the fourth ion implantation is source-drain SDN type ion implantation.

The technical solution of the present application at least includes the following advantages:

By arranging the first gate and the second gate in parallel, the problem of high threshold voltage caused by setting the N-type region is solved, the opening ability of the gate of the semiconductor device to the channel is increased, and the threshold voltage of the semiconductor device is reduced. ; At the same time, the anti-leakage capability of the semiconductor device is increased by setting the isolation layer.

Description of drawings

In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the accompanying drawings that need to be used in the description of the specific embodiments or prior art. Obviously, the accompanying drawings in the following description The figures show some implementations of the present application, and those skilled in the art can obtain other figures based on these figures without any creative effort.

FIG. 1 is a plan view of a semiconductor device provided by an exemplary embodiment of the present application;

FIG. 2 is a cross-sectional view along a first direction of a semiconductor device provided by an exemplary embodiment of the present application;

FIG. 3 is a cross-sectional view along a second direction of a semiconductor device provided by an exemplary embodiment of the present application;

FIG. 4 is a flowchart of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application;

5 to 10 are schematic flowcharts of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application.

Detailed ways

The technical solutions in the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Apparently, the described embodiments are part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

In the description of this application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, or in a specific orientation. construction and operation, therefore should not be construed as limiting the application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and should not be construed as indicating or implying relative importance.

In the description of this application, it should be noted that unless otherwise specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connected, or integrally connected; it can be mechanically connected or electrically connected; it can be directly connected, or indirectly connected through an intermediary, or it can be the internal communication of two components, which can be wireless or wired connect. Those of ordinary skill in the art can understand the specific meanings of the above terms in this application in specific situations.

In addition, the technical features involved in the different embodiments of the present application described below may be combined as long as they do not constitute a conflict with each other.

Fig. 1 shows a top view of a semiconductor device provided by an exemplary embodiment of the present application; Fig. 2 shows a left cross-sectional view of a semiconductor device provided by an exemplary embodiment of the present application; Fig. 3 shows a A front cross-sectional view of a semiconductor device provided in an exemplary embodiment of the application.

Referring to FIG. 1 , the D1 direction where the thickness of the semiconductor device 100 provided by the embodiment of the present application is defined as the first direction, the D2 direction where the width of the semiconductor device 100 is located is the second direction, and the D3 direction where the length of the semiconductor device 100 is located is the second direction. Three directions.

Referring to FIG. 2, the semiconductor device 100 includes a bottom layer 110, an isolation layer 120, and a pattern layer 130 along the direction D1 in sequence; The direction is "down". Wherein, the isolation layer 120 may be oxide (such as silicon oxide), nitride (such as silicon nitride) or oxynitride (such as silicon oxynitride); the bottom layer 110 may be a semiconductor, such as silicon, germanium and the like.

1 to 3, the pattern layer 130 includes a first N-type region 131, a first gate 132, a second gate 133, a P-type well 134, an N-type drift region 135, a second N-type region 136 and a top layer structure 137; as shown in FIG. 1, the top layer structure 137 surrounds the first N-type region 131, the first gate 132, the second gate 133, the P-type well 134, the N-type drift region 135 and the second N-type region 136 outside. Wherein, the top layer structure 137 may be a semiconductor material, such as silicon, germanium and the like. Optionally, the top layer structure 137 and the bottom layer 110 are made of the same material.

Referring to Fig. 1 and Fig. 2, in the D2 direction, define the direction from the first gate 133 to the first gate 132 as "front", define the direction from the first gate 132 to the second gate 133 as "rear"; refer to 1 and 3, in the D3 direction, the direction defining the first N-type region 131 to the second N-type region 136 is "right", and the direction defining the second N-type region 136 to the first N-type region 131 is "left". ".

Referring to FIG. 1 and FIG. 2, along the D2 direction, the first gate 132 and the second gate 133 are arranged oppositely, and the first N-type region 131, the P-type well 134, the N-type drift region 135 and the second N-type region 136 is located in the region between the first gate 132 and the second gate 133 in the pattern layer 130 .

Referring to FIG. 1 and FIG. 3 , along the direction D3, a first N-type region 131 , a P-type well 134 , an N-type drift region 135 and a second N-type region 136 are sequentially arranged from left to right.

To sum up, the semiconductor device of the embodiment of the present application solves the problem of high threshold voltage caused by setting the N-type region by arranging the first gate and the second gate in parallel, and increases the gate-to-channel ratio of the semiconductor device. The opening ability of the channel reduces the threshold voltage of the semiconductor device; at the same time, the anti-leakage capability of the semiconductor device is increased by setting the isolation layer.

Fig. 4 shows a flowchart of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application. The semiconductor manufacturing method in this embodiment can be used to manufacture the semiconductor device in the embodiment in FIG. 1 to FIG. 3 , and the directions involved in the embodiment of the present application are the same as those in the embodiment in FIG. 1 to FIG. 3 . The method includes:

Step 401, providing a substrate.

Exemplarily, as shown in FIG. 5 , along the D1 direction where the thickness of the substrate 500 lies, the substrate 500 includes a bottom (Substrate) layer 510 , an isolation (Box) layer 520 and a top (Top) layer 530 in sequence. Wherein, the isolation layer 520 can be oxide (such as silicon oxide), nitride (such as silicon nitride) or oxynitride (such as silicon oxynitride); the bottom layer 510 and the top layer 530 can be the same material, which can be a semiconductor, such as Silicon, germanium, etc. The substrate 500 is generally referred to as a Silicon-On-Insulator (SOI) structure.

In step 402, the first ion implantation and the second ion implantation are sequentially performed along the length direction of the substrate, and a P-type well and an N-type drift region are sequentially formed on the top layer.

Exemplarily, as shown in FIG. 6 , the first ion implantation and the second ion implantation are sequentially performed to the right along the direction D3 to form a P-type well 531 and an N-type drift region 532 respectively. Wherein, the first ion implantation is P-well ion implantation, and the second ion implantation is N-type drift ion implantation.

Step 403 , forming a first channel and a second channel on the top layer by an etching process.

Exemplarily, as shown in FIG. 7 , along the direction D2, a first channel 5331 and a second channel 5341 are respectively formed on the top layer 530 through photolithography and dry etching processes, and the first channel 5331 and the second channel The channel 5341 is sequentially located on both sides of the P-type well 531 and the N-type drift region 532 along the D2 direction.

Step 404, filling the first trench with polysilicon to form a first gate, and filling the second trench with polysilicon to form a second gate.

Exemplarily, as shown in FIG. 8, a gate oxide layer 5301 is formed on the surfaces of the first channel 5331, the second channel 5341, the P-type well 531, the N-type drift region 534, and the top layer 530; as shown in FIG. 9 Fill polysilicon in the first channel 5331 through the furnace tube, and fill polysilicon in the second channel 5341 through the furnace tube; planarize the polysilicon through a chemical mechanical polishing (CMP) process to obtain the first gate 533 and the second grid 534 .

Step 405 , performing third ion implantation and fourth ion implantation on the top layer in regions close to the first gate and the second gate along the length direction of the substrate to form a first N-type region.

Exemplarily, as shown in FIG. 10 , lightly doped drain (Lightly Doped Drain, LDD) ion implantation and source are performed on the top layer 530 in the region close to the first gate 533 and the second gate 534 along the direction D3 The drain (Source Drain, SD) is implanted with N-type ions to form a first N-type region 535 .

Step 406, along the length direction of the substrate, perform the third ion implantation and the fourth ion implantation respectively on the top layer in the region close to the N-type drift region to form the second N-type region 536, the top layer except the first N-type region, the first The gate, the second gate, the P-type well, and other regions of the N-type drift region form a top layer structure.

Exemplarily, as shown in FIG. 10 , along the D3 direction, LDD ion implantation and SDN type ion implantation are performed on the top layer 530 in the area close to the N-type drift region 532 to form a second N-type region 536, and the top layer except the first N-type The region 535 , the first gate 533 , the second gate 534 , the P-type well 531 , and other regions of the N-type drift region 532 form a top layer structure 537 .

Apparently, the above-mentioned embodiments are only examples for clearly illustrating, rather than limiting the implementation. For those of ordinary skill in the art, on the basis of the above description, other changes or changes in different forms can also be made. It is not necessary and impossible to exhaustively list all the implementation manners here. However, the obvious changes or changes derived therefrom are still within the protection scope of the invention of the present application.

Claims (6)

1. A semiconductor device, comprising:

the semiconductor device comprises a bottom layer, an isolation layer and a pattern layer in sequence along the thickness direction of the semiconductor device, wherein the isolation layer comprises a silicon oxide layer, and the bottom layer comprises a silicon bottom layer;

the pattern layer comprises a top layer structure, a first N-type region, a first grid electrode, a second grid electrode, a P-type well, an N-type drift region and a second N-type region, and the top layer structure comprises a silicon top layer structure;

the first grid electrode and the second grid electrode are oppositely arranged along the width direction of the semiconductor device, and the first N-type region, the P-type well, the N-type drift region and the second N-type region are positioned between the first grid electrode and the second grid electrode;

the first N-type region, the P-type well, the N-type drift region and the second N-type region are sequentially arranged along the length direction of the semiconductor device.

2. A method of manufacturing a semiconductor device, the method comprising:

providing a substrate, wherein the substrate sequentially comprises a bottom layer, an isolation layer and a top layer along the thickness direction of the substrate, and the bottom layer comprises a silicon bottom layer;

sequentially performing first ion implantation and second ion implantation along the length direction of the substrate, and sequentially forming a P-type well and an N-type drift region on the top layer respectively;

forming a first channel and a second channel on the top layer through an etching process, wherein the first channel and the second channel are sequentially positioned on two sides of the P-type well and the N-type drift region along the width direction of the substrate;

filling polycrystalline silicon in the first channel to form a first grid electrode, and filling polycrystalline silicon in the second channel to form a second grid electrode;

respectively carrying out third ion implantation and fourth ion implantation on the top layer in the area close to the first grid electrode and the second grid electrode along the length direction of the substrate to form a first N-type area;

and respectively carrying out third ion implantation and fourth ion implantation on the top layer in a region close to the N-type drift region along the length direction of the substrate to form a second N-type region, wherein the top layer forms a top layer structure except for the first N-type region, the first grid electrode, the second grid electrode, the P-type well and other regions of the N-type drift region, and the top layer structure comprises a silicon top layer structure.

3. The method of claim 2, wherein forming a first gate in the first trench-filled polysilicon and forming a second gate in the second trench-filled polysilicon further comprises:

and forming a gate oxide layer on the surfaces of the first channel, the second channel, the P-type well, the N-type drift region and the top layer.

4. The method of claim 3, wherein the filling polysilicon in the first channel to form a first gate and filling polysilicon in the second channel to form a second gate comprises:

filling the polysilicon in the first channel through a furnace tube, and filling the polysilicon in the second channel through the furnace tube;

and carrying out planarization treatment on the polysilicon through a Chemical Mechanical Polishing (CMP) process to obtain the first grid electrode and the second grid electrode.

5. The method of any of claims 2 to 4, wherein the third ion implantation is a lightly doped drain LDD ion implantation.

6. The method of any of claims 2 to 4, wherein the fourth ion implantation is a source drain SDN type ion implantation.