CN110473790B - Integrated circuit packaging method and semiconductor device - Google Patents
Integrated circuit packaging method and semiconductor device Download PDFInfo
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- CN110473790B CN110473790B CN201910701507.2A CN201910701507A CN110473790B CN 110473790 B CN110473790 B CN 110473790B CN 201910701507 A CN201910701507 A CN 201910701507A CN 110473790 B CN110473790 B CN 110473790B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
- H01L21/4875—Connection or disconnection of other leads to or from bases or plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
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- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention provides an integrated circuit packaging method and a semiconductor device, wherein the method comprises the following steps: (a) identifying a bottom plate with an attached bare chip of an integrated circuit, and generating a plastic package model according to identification information of the bottom plate with the attached bare chip of the integrated circuit, wherein contact electrodes of the bare chip of the integrated circuit are correspondingly connected with pins on the bottom plate through bonding wires one by one; (b) and according to the plastic package model, sequentially forming a plurality of overlapped and insulated light-cured adhesive layers on one side of the bottom plate, which is attached with the integrated circuit bare chip, and wrapping the integrated circuit bare chip and the bonding wire in the plurality of light-cured adhesive layers. According to the invention, the plurality of overlapped and insulated photocuring adhesive layers are sequentially formed on the side, where the integrated circuit bare chip is attached, of the lead frame, so that the warping of the lead frame and the snapping of the bonding wire in the plastic packaging process are avoided, and the packaging yield of the integrated circuit is improved.
Description
Technical Field
The present invention relates to the field of integrated circuit packaging, and more particularly, to an integrated circuit packaging method and a semiconductor device.
Background
Modern products are thin, light, small, and small, so many discrete circuits are integrated into an integrated circuit. Currently, integrated circuits have been widely used in personal computers, mobile phones, digital cameras, and other electronic devices. In order to provide a stable and reliable working environment for the integrated circuit and perform mechanical or environmental protection on the integrated circuit, so that the integrated circuit can perform normal functions and has high stability and reliability, the integrated circuit needs to be packaged.
For the existing general integrated circuit, most of the integrated circuits adopt a plastic packaging form, and the main packaging forms include: PDIP (plastic dual in-line package), PLCC (plastic leaded chip carrier), QFP (quad flat package), QFN (no lead quad flat package), SOP (small outline package), Thin Small Outline Package (TSOP), scaled-down SOP (ssop), and thin scaled-down SOP (tssop), and the like.
The existing plastic package mainly comprises the processing steps of grinding (Back grinding), stretching film (Wafer Mounting), scribing (Wafer winding/Dicing Saw), Bonding (Die Attach/Die Bonding), Bonding (Wire Bonding), Molding (Molding), Curing (Curing), electroplating (Plating), Trimming Forming (Trimming Forming), Testing/sorting (Testing/Bonding), printing (Marking), packaging (packaging) and the like.
In the packaging process, the plastic package adhesive needs to be heated to 180 ℃ and then injected to the surfaces of the lead frame and the bare integrated circuit (Die), and due to the fact that the thermal coefficients of the bare integrated circuit and the plastic package material are different, when the plastic package adhesive is cooled, the lead frame can be warped, and the bonding wires can be pulled apart.
Disclosure of Invention
The invention aims to solve the technical problem that the integrated circuit is easy to warp a lead frame and stretch a bonding wire due to different thermal coefficients of a bare chip of the integrated circuit and a plastic packaging material in the plastic packaging process, and provides an integrated circuit packaging method and a semiconductor device.
The technical solution of the present invention for solving the above technical problems is to provide an integrated circuit packaging method, which includes the following steps:
(a) identifying a bottom plate with an attached bare chip of an integrated circuit, and generating a plastic package model according to identification information of the bottom plate with the attached bare chip of the integrated circuit, wherein contact electrodes of the bare chip of the integrated circuit are correspondingly connected with pins on the bottom plate through bonding wires one by one;
(b) and according to the plastic package model, sequentially forming a plurality of overlapped and insulated light-cured adhesive layers on one side of the bottom plate, which is attached with the integrated circuit bare chip, and wrapping the integrated circuit bare chip and the bonding wire in the plurality of light-cured adhesive layers.
Preferably, the plastic package model comprises a sintered pattern of each photo-curing glue layer; the step (b) comprises the steps of:
(b1) dipping the bottom plate with the bare crystal of the integrated circuit in a photocuring glue solution;
(b2) and lifting the bottom plate with the bare chips of the integrated circuit or immersing the bottom plate downwards, and performing layer-by-layer illumination sintering on the part of the bottom plate with the bare chips of the integrated circuit, which is exposed out of the liquid level of the photocuring glue solution, according to the sintering pattern of each photocuring glue layer.
Preferably, the base plate is a substrate or a lead frame, and in the step (b2), a portion of the base plate to which the bare chips of the integrated circuit are attached, which is away from the liquid surface of the photo-curing glue solution, is sintered using a surface light source, which includes a plurality of light emitting points controlled independently, and emits light to cover the surface of the base plate to which the bare chips of the integrated circuit are attached.
Preferably, in the step (b1), the substrate with the bare chip mounted thereon is immersed in a photo-curing glue solution upside down, and the surface light source is positioned below the photo-curing glue solution;
or, in the step (b1), the substrate with the bare integrated circuit mounted thereon is immersed in the photo-curing glue solution in a manner that the side of the bare integrated circuit is upward, and the surface light source is located above the substrate with the bare integrated circuit mounted thereon.
Preferably, the plastic package model comprises a moving path of the spray head and the light source on each light-cured adhesive layer; the step (b) comprises the steps of:
(b 1') according to the moving path of the spray head and the light source on each photo-curing glue layer, controlling the spray head to spray the photo-curing glue solution on the side of the bottom plate where the integrated circuit bare chips are attached, and sintering and curing the photo-curing glue solution attached to the side of the bottom plate where the integrated circuit bare chips are attached through the light source.
Preferably, in the step (b 1'), the light-curing glue solution is sprayed on the side of the base plate where the bare integrated circuit die is attached through a plurality of spray heads arranged in a row, and the spray range of the plurality of spray heads is equal to the length of one side of the base plate; the moving path includes a path perpendicular to an arrangement direction of the plurality of heads.
Preferably, each spray head is integrated with a light source, and the irradiation area of the light source is consistent with the spraying area of the spray head.
Preferably, the bottom plate is a lead frame, the plastic package mold includes a sintered pattern of each photo-curing adhesive layer on a side of the lead frame facing away from the integrated circuit die, and the method further includes the following steps:
(b 2') dipping the lead frame into the photo-curing glue solution at the side opposite to the side where the integrated circuit bare chip is attached;
(b 3') lifting the lead frame upwards, and performing light sintering on the part of the lead frame exposed out of the liquid level of the light curing glue solution layer by layer according to the sintering pattern of each light curing glue layer.
Preferably, the base plate is a lead frame, and the step (a) is preceded by:
(a01) sequentially forming a plurality of overlapped and insulated light-cured adhesive layers on one side of the lead frame;
(a02) and fixing the bare chip of the integrated circuit on the other side of the lead frame, and connecting the contact electrodes of the bare chip of the integrated circuit with the pins on the bottom plate in a one-to-one correspondence manner through bonding wires.
The present invention also provides a semiconductor device packaged by the integrated circuit packaging method as described in any one of the above.
According to the integrated circuit packaging method and the semiconductor device, the plurality of overlapped and insulated photocuring glue layers are sequentially formed on the side, where the bare chip of the integrated circuit is attached, of the lead frame, so that the warping of the lead frame and the stretch breaking of the bonding wire in the plastic packaging process are avoided, and the qualification rate of integrated circuit packaging is improved.
Drawings
FIG. 1 is a flow chart of an integrated circuit packaging method according to an embodiment of the invention;
FIG. 2 is a schematic flow chart illustrating the formation of a photo-curing adhesive layer in the integrated circuit packaging method according to an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating a photo-curing adhesive layer formed in a method for packaging an integrated circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of another photo-curing adhesive layer formation in the integrated circuit packaging method according to the embodiment of the invention;
FIG. 5 is a schematic diagram illustrating a photo-curing adhesive layer formed in the integrated circuit packaging method according to an embodiment of the present invention;
fig. 6 is a schematic view illustrating a photo-curing adhesive layer formed in the integrated circuit packaging method according to the embodiment of the invention.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, etc., are set forth below to simplify the present embodiments. Of course, these are merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, etc. are contemplated. For example, forming a first feature "over" or "on" a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, embodiments of the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Furthermore, for ease of description, spatially relative terms such as "under", "below", "lower", "above", "upper", and the like may be used herein to describe one element or feature's relationship to another (other) element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as well.
Additionally, for ease of description, terms such as "first," "second," and the like may be used herein to describe similar or different elements or features shown in the figures, and these terms may be used interchangeably depending on the order of presentation or context of description.
As shown in fig. 1, the flowchart of the method for packaging an integrated circuit according to the embodiment of the present invention is used for performing glue sealing on a bare chip (die) of an integrated circuit and a bottom board to protect the die of the integrated circuit mechanically or environmentally, so that the integrated circuit can perform normal functions. The integrated circuit die may have a passivation layer thereon, the passivation layer covering an active surface of the die, the passivation layer including one or more conductive pillars electrically connected to one or more metal pads (pads) on the active surface of the die, respectively, and the conductive pillars forming a die pad. Of course, in practical applications, the active surface of the ic die may not have a passivation layer, i.e., the chip pad may be directly formed by a metal pad on the ic die. The integrated circuit packaging method of the embodiment comprises the following steps:
step S1: and identifying the bottom plate with the bare chips of the integrated circuit, and generating a plastic package model according to the identification information of the bottom plate with the bare chips of the integrated circuit.
The base plate is used for providing circuit connection and fixing the bare chip of the integrated circuit, and the bare chip of the integrated circuit is bonded to the base plate through silver paste and the like after being subjected to grinding, grinding and scribing. On the bottom plate with the bare chips of the integrated circuit, the contact electrodes of the bare chips of the integrated circuit are correspondingly connected with the pins on the bottom plate one by one through bonding wires. The base plate may be a substrate or a lead frame.
In this step, the base plate on which the bare chip of the integrated circuit is mounted may be identified by means of camera scanning, laser scanning, ultrasonic scanning, or the like, so as to obtain information (i.e., identification information) such as the shape of the base plate on the side on which the bare chip of the integrated circuit is mounted, the size and position of the bare chip of the integrated circuit, and the height of the bare chip protruding from the base plate. Correspondingly, the plastic package model generated according to the identification information comprises patterns at each height of the bottom plate at the side where the integrated circuit bare chip is attached, for example, when the patterns are lower than the height of the integrated circuit bare chip protruding out of the surface of the bottom plate, the patterns of the plastic package model are in a shape of a Chinese character hui (the outer frame is matched with the outer contour of the bottom plate, and the inner frame is matched with the outer contour of the bare chip); when the height of the bare chip of the integrated circuit is higher than the height of the bare chip protruding out of the surface of the bottom plate, the pattern of the plastic package model is a rectangle or other shapes matched with the bottom plate.
Step S2: according to the plastic package model, a plurality of light-cured adhesive layers which are sequentially overlapped and insulated are formed on one side of the bottom plate, wherein the integrated circuit bare chips are attached to the side, and the integrated circuit bare chips and the bonding wires are wrapped in the plurality of light-cured adhesive layers. The filling layer is formed by a plurality of light-cured glue layers, the filling layer formed by the existing glue pouring and injection molding is replaced to wrap the bare chip and the bonding wire of the integrated circuit, and the bare chip of the integrated circuit is mechanically or environmentally protected.
The photo-curing adhesive layer can be formed by curing a photo-curing adhesive solution after being irradiated by light with a specific wavelength, for example, the photo-curing adhesive solution can be an ultraviolet curing adhesive solution and can be cured under the irradiation of an ultraviolet light source.
Because the light-cured adhesive layer is not required to be heated, melted and cooled (the highest temperature in the whole plastic packaging process does not exceed 60 ℃) in the forming process of the light-cured adhesive layer, the warping of the base plate and the stretching and breaking of bonding wires caused by the difference of the heat conductivity coefficients of the base plate and the packaging adhesive in the plastic packaging process can be avoided, and compared with the existing injection molding scheme with the highest temperature reaching 180 ℃, the yield of the integrated circuit bare chip packaging can be greatly improved.
In the integrated circuit packaging method, the plastic package model generated according to the identification information comprises a sintered pattern of each photocuring glue layer; as shown in fig. 2, the step S2 may specifically include:
step S21: referring to fig. 3, the bottom plate 31 is inversely immersed in the photo-curing adhesive solution 34, that is, the side of the bottom plate 31 where the bare chips of the integrated circuit are attached is immersed in the photo-curing adhesive solution 34, the bare chips 32 of the integrated circuit are attached to the bottom plate 31, and the bare chips 32 of the integrated circuit are connected with the pins of the bottom plate 31 through the bonding wires 33 in a one-to-one correspondence manner.
Step S22: and lifting the bottom plate 31 with the bare integrated circuit 32, and performing layer-by-layer illumination sintering on the part, exposed out of the liquid level of the photocuring glue solution 34, of the bottom plate 31 with the bare integrated circuit 32 according to the sintering pattern of each photocuring glue layer in the plastic package model to form a plurality of overlapped photocuring glue layers 35.
Specifically, when the photo-curing glue solution 34 is photo-sintered, a surface light source 36 (e.g., ultraviolet light) may be used to sinter a portion of the bottom plate 31 attached with the bare integrated circuit 32, which is away from the liquid surface of the photo-curing glue solution 34, wherein the surface light source 36 includes a plurality of light emitting points which are independently controlled, and the light emitted by the plurality of light emitting points covers the surface of the bottom plate 31 attached with the bare integrated circuit 32, i.e., the photo-curing glue layer 35 is formed at the same time in a whole layer. In this step, the light source 36 of the control surface is illuminated and sintered according to the corresponding sintering pattern in the plastic mold according to the height of the lifting of the bottom plate 31 with the bare integrated circuit 32 mounted thereon, thereby forming the light-cured adhesive layer.
In particular, the surface light source 36 may be located below the light-curing glue solution 34. That is, light emitted from the surface light source 36 (or light reflected by the mirror or the triangular mirror) passes through the photo-curing glue solution 34 to be sintered.
Of course, in practical application, the bottom plate 31 may be dipped into the photo-curing glue solution 34 on the side opposite to the side on which the bare chips of the integrated circuit are mounted, as shown in fig. 4, and then the bottom plate 31 is slowly dipped downward, and the surface light source 36 may be positioned above the photo-curing glue solution 34, and the part of the bottom plate 31 exposed out of the liquid surface of the photo-curing glue solution 34 is photo-sintered.
In addition, the speed of lifting the base plate 31 can be reduced in consideration of the curing time of the photo-curing glue solution 34, so that the lifting operation of the base plate 31 is a continuous process, thereby ensuring the curing effect of the photo-curing glue solution 34.
Besides the light-cured glue layer formed by adopting the immersion sintering, the light-cured glue layer can also be formed by a 3D printing mode. In another embodiment of the integrated circuit package method of the present invention, the plastic package model generated according to the identification information includes a moving path of the nozzle and the light source on each photo-curing adhesive layer; with reference to fig. 5, the step S2 may specifically include:
step S21': according to the moving path of the spray head and the light source in each light-cured adhesive layer in the plastic package model, the spray head 47 is controlled to spray the light-cured adhesive solution 44 on the side of the bottom plate 41 where the integrated circuit bare dies 42 are attached (on the side, the integrated circuit bare dies 42 are correspondingly connected with the pins on the bottom plate 41 one by one through the bonding wires 43), and the light-cured adhesive solution 44 attached on the side of the bottom plate 41 where the integrated circuit bare dies 42 are attached is sintered and cured through the light source 46 to form a plurality of stacked light-cured adhesive layers 45.
Specifically, in this step, a plurality of heads 47 may be arranged in a row, and the ejection range of the plurality of heads 47 is equal to the length of one side of the base plate 41. Accordingly, the moving path in the plastic mold includes a path perpendicular to the arrangement direction of the plurality of nozzles 47. Therefore, when the light-cured adhesive layer 45 is formed, the plurality of nozzles 47 can be controlled to move according to the moving path, that is, each light-cured adhesive layer 45 is formed by linearly splicing a plurality of light-cured adhesives.
Specifically, each of the nozzles 47 is integrated with a light source 46, the light source 46 may specifically include a light emitting body 461 and a light guiding body 462, and an irradiation area of the light source 46 is consistent with (e.g., slightly behind) a spraying area of the corresponding nozzle 47. Thus, the photo-curing glue solution 44 attached to the side of the base plate 41 where the bare integrated circuit 42 is mounted is sintered and cured while the photo-curing glue solution 44 is sprayed, and the control is simplified. The precision of the spray head 47 can reach 2880DPI (Dots Per Inch), and of course, different precisions can be selected according to requirements.
In one embodiment of the present invention, when the bottom plate is a lead frame, the light-curing glue layer may be formed on both sides of the lead frame. As shown in fig. 6, the light-curing adhesive layer 65 on the lead frame 61 (i.e., on the side where the bare integrated circuit 62 is mounted) can be formed by spraying a light-curing adhesive solution 63 and a light source 66 (the light source 66 includes a light emitter 661 and a light guide 662) through a nozzle 67 and curing by light irradiation; and the photo-curing glue layer 69 on the side and below the lead frame 61 can be formed by immersing the photo-curing glue solution 64 and then sintering the photo-curing glue solution. Also, the photo-curing adhesive layers 65 and 69 of the upper and lower sides of the lead frame 61 may be simultaneously formed, thereby improving the process efficiency.
Specifically, when the photo-curing adhesive layers 69 on the side and below the side of the lead frame 61 are formed, the side of the lead frame 61 opposite to the side on which the bare integrated circuit 62 is mounted is dipped in the photo-curing adhesive solution 64, and then the lead frame 61 is lifted upwards, and the part of the lead frame 61 exposed out of the liquid surface of the photo-curing adhesive solution is subjected to light sintering layer by the surface light source 68 below the photo-curing adhesive solution 64 according to the sintering pattern of each photo-curing adhesive layer.
In addition, when the bottom plate is a lead frame, a mold structure may be formed on one side of the lead frame in advance, that is, before step S1, the method may include: sequentially forming a plurality of overlapped and insulated light-cured adhesive layers on one side of the lead frame (for example, in a manner shown in fig. 3 or fig. 4); the integrated circuit die is then attached to the other side of the leadframe (e.g., in the manner shown in fig. 3 or 4), and the contact electrodes of the integrated circuit die are connected to the leads on the backplane in a one-to-one correspondence via bond wires.
In practical applications, the side of the lead frame facing away from the die for bonding the integrated circuit may also be formed into a plastic-molded structure by other methods, such as a glue injection molding method.
The invention also provides a semiconductor device, and the semiconductor device is packaged by the integrated circuit packaging method.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (5)
1. An integrated circuit packaging method, comprising the steps of:
(a) identifying a bottom plate with an attached bare chip of an integrated circuit, and generating a plastic package model according to identification information of the bottom plate with the attached bare chip of the integrated circuit, wherein contact electrodes of the bare chip of the integrated circuit are correspondingly connected with pins on the bottom plate through bonding wires one by one;
(b) according to the plastic package model, a plurality of overlapped and insulated light-cured adhesive layers are sequentially formed on one side, where the integrated circuit bare chips are attached, of the bottom plate, and the integrated circuit bare chips and the bonding wires are wrapped in the plurality of light-cured adhesive layers;
the plastic package model comprises a sintered pattern of each photocuring glue layer; the step (b) comprises the steps of:
(b1) dipping the bottom plate with the bare crystal of the integrated circuit in a photocuring glue solution;
(b2) and lifting the bottom plate with the bare chips of the integrated circuit or immersing the bottom plate downwards, and performing layer-by-layer illumination sintering on the part of the bottom plate with the bare chips of the integrated circuit, which is exposed out of the liquid level of the photocuring glue solution, according to the sintering pattern of each photocuring glue layer.
2. The method of claim 1, wherein the substrate is a substrate or a lead frame, and in the step (b2), the portion of the substrate with the bare integrated circuit mounted thereon, which is away from the liquid surface of the photo-curing glue solution, is sintered by a surface light source, wherein the surface light source comprises a plurality of independently controlled light emitting points, and the light emitted from the light emitting points covers the surface of the substrate with the bare integrated circuit mounted thereon.
3. The method of claim 2, wherein in step (b1), the substrate with the bare integrated circuit mounted thereon is immersed in a photo-curing glue solution upside down, and the surface light source is located below the photo-curing glue solution;
or, in the step (b1), the substrate with the bare integrated circuit mounted thereon is immersed in the photo-curing glue solution in a manner that the side of the bare integrated circuit is upward, and the surface light source is located above the substrate with the bare integrated circuit mounted thereon.
4. The integrated circuit packaging method of claim 1, wherein the base plate is a lead frame, and step (a) is preceded by:
(a01) sequentially forming a plurality of overlapped and insulated light-cured adhesive layers on one side of the lead frame;
(a02) and fixing the bare chip of the integrated circuit on the other side of the lead frame, and connecting the contact electrodes of the bare chip of the integrated circuit with the pins on the bottom plate in a one-to-one correspondence manner through bonding wires.
5. A semiconductor device packaged by the integrated circuit packaging method according to any one of claims 1 to 4.
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|---|---|---|---|
| CN202110288385.6A CN113140467A (en) | 2019-07-31 | 2019-07-31 | Integrated circuit packaging method and semiconductor device |
| CN201910701507.2A CN110473790B (en) | 2019-07-31 | 2019-07-31 | Integrated circuit packaging method and semiconductor device |
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| CN201910701507.2A CN110473790B (en) | 2019-07-31 | 2019-07-31 | Integrated circuit packaging method and semiconductor device |
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|---|---|---|---|---|
| US6309943B1 (en) * | 2000-04-25 | 2001-10-30 | Amkor Technology, Inc. | Precision marking and singulation method |
| DE10038998A1 (en) * | 2000-08-10 | 2002-02-21 | Bosch Gmbh Robert | Semiconductor component and method for identifying a semiconductor component |
| JP2003124241A (en) * | 2001-10-18 | 2003-04-25 | Shinko Electric Ind Co Ltd | Semiconductor device and method of manufacturing the same |
| US20040038442A1 (en) * | 2002-08-26 | 2004-02-26 | Kinsman Larry D. | Optically interactive device packages and methods of assembly |
| CN1755908A (en) * | 2004-09-29 | 2006-04-05 | 上海贝岭股份有限公司 | Method for improving qualification rate of plastic encapsulated integrated circuit |
| SG155779A1 (en) * | 2008-03-10 | 2009-10-29 | Micron Technology Inc | Apparatus and methods of forming wire bonds |
| US9403296B2 (en) * | 2012-04-12 | 2016-08-02 | Telsa Motors, Inc. | Embedded optics in modular assemblies |
| KR101542622B1 (en) * | 2013-01-02 | 2015-08-06 | 제일모직주식회사 | Composition for encapsulation, barrier layer comprising the same and encapsulated apparatus comprising the same |
| CN103280516B (en) * | 2013-05-15 | 2015-07-01 | 陕西煤业化工技术研究院有限责任公司 | Light-emitting diode packaging material and packaging forming method |
| JP2015026655A (en) * | 2013-07-25 | 2015-02-05 | 住友重機械工業株式会社 | Method and apparatus for forming thin film |
| CN109243982B (en) * | 2018-08-31 | 2020-02-14 | 华中科技大学 | Electrofluid spray printing etching method for manufacturing curved integrated circuit |
-
2019
- 2019-07-31 CN CN201910701507.2A patent/CN110473790B/en active Active
- 2019-07-31 CN CN202110288385.6A patent/CN113140467A/en active Pending
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| Publication number | Publication date |
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| CN113140467A (en) | 2021-07-20 |
| CN110473790A (en) | 2019-11-19 |
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