CN110462825B - Semiconductor packaging device and manufacturing method thereof - Google Patents
Semiconductor packaging device and manufacturing method thereof Download PDFInfo
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- CN110462825B CN110462825B CN201880021991.8A CN201880021991A CN110462825B CN 110462825 B CN110462825 B CN 110462825B CN 201880021991 A CN201880021991 A CN 201880021991A CN 110462825 B CN110462825 B CN 110462825B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 97
- 238000004519 manufacturing process Methods 0.000 title description 20
- 238000004806 packaging method and process Methods 0.000 title description 12
- 239000011347 resin Substances 0.000 claims abstract description 18
- 229920005989 resin Polymers 0.000 claims abstract description 18
- 238000007789 sealing Methods 0.000 claims abstract description 9
- 238000007599 discharging Methods 0.000 claims 1
- 238000000034 method Methods 0.000 description 25
- 239000000758 substrate Substances 0.000 description 17
- 239000000853 adhesive Substances 0.000 description 12
- 230000001070 adhesive effect Effects 0.000 description 12
- 238000007747 plating Methods 0.000 description 12
- 239000004020 conductor Substances 0.000 description 6
- 238000009413 insulation Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000010485 coping Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/11—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in subclass H10D
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/18—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of the types provided for in two or more different main groups of the same subclass of H10B, H10D, H10F, H10H, H10K or H10N
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Inverter Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
A semiconductor package device includes: a wiring layer having an insulating portion and a conductive portion; a plurality of semiconductor packages disposed in contact with an upper surface of the wiring layer; and a resin portion sealing the semiconductor package.
Description
Technical Field
The present invention relates to a semiconductor package device and a method of manufacturing the same.
Background
Patent document 1 discloses an example of a conventional packaging device. In the integrated circuit package system of patent document 1, the 1 st integrated circuit chip is fixed on the package substrate by bonding. The 1 st integrated circuit chip and the package substrate are connected by wire bonding. The adhesive spacer is disposed between the 1 st integrated circuit chip and the integrated circuit package system.
The integrated circuit package system has a 2 nd integrated circuit chip, terminals, and a sealing resin. The 2 nd integrated circuit chip is connected to the terminals by bonding wires. The 2 nd integrated circuit chip and the terminals are sealed with a sealing resin. The terminals and the package substrate are connected by bonding wires.
The package substrate, the 1 st integrated circuit chip, the adhesive spacer, and the integrated circuit package system are encapsulated by a sealing resin, thereby forming the integrated circuit package system.
Prior art literature
Patent literature
Patent document 1: japanese patent application laid-open No. 2012-169664
Disclosure of Invention
Problems to be solved by the invention
However, in patent document 1, since the integrated circuit package system including the 2 nd integrated circuit chip is disposed above the 1 st integrated circuit chip, in order to electrically connect the integrated circuit package system and the 1 st integrated circuit chip, it is necessary to connect the terminals of the integrated circuit package system to the package substrate by wire bonding. When wire bonding is performed, accordingly, space for transferring the wire is required.
In addition, in patent document 1, when the same package device is further stacked above the integrated circuit package system, the length of the bonding wire for connection to the package substrate increases as the package device is further stacked above. Therefore, in patent document 1, the number of packaged devices to be packaged is limited.
In view of the above, an object of the present invention is to provide a semiconductor package device in which wire bonding is not required for wiring and in which the number of semiconductor packages to be mounted is less limited.
Means for solving the problems
An exemplary semiconductor package device according to the present invention includes: a wiring layer having an insulating portion and a conductive portion; a plurality of semiconductor packages disposed in contact with an upper surface of the wiring layer; and a resin portion sealing the semiconductor package.
The exemplary method for manufacturing a semiconductor package according to the present invention includes the steps of: step 1, disposing a plurality of semiconductor packages on an adhesive disposed on a support substrate; a step 2 of sealing the semiconductor package with a resin; a step 3 of detaching the support substrate and the adhesive from the resin; and a 4 th step of forming an insulating layer on the lower surface side of the resin, forming a via hole in the insulating layer, and forming a wiring pattern portion on the via hole and the lower surface of the insulating layer at least once by plating.
Effects of the invention
According to the exemplary semiconductor package apparatus of the present invention, wire bonding is not required for wiring, and the number of semiconductor packages to be mounted is less limited.
Drawings
Fig. 1 is a diagram showing a circuit configuration of a semiconductor package apparatus according to an embodiment of the present invention.
Fig. 2A is a schematic side cross-sectional view showing one process of the manufacturing process of the semiconductor package apparatus.
Fig. 2B is a schematic side cross-sectional view showing one process of the manufacturing process of the semiconductor package apparatus.
Fig. 2C is a schematic side cross-sectional view showing one process of the manufacturing process of the semiconductor package apparatus.
Fig. 2D is a schematic side cross-sectional view showing one process of the manufacturing process of the semiconductor package apparatus.
Fig. 2E is a schematic side cross-sectional view showing one process of the manufacturing process of the semiconductor package apparatus.
Fig. 2F is a schematic side cross-sectional view showing one process of the manufacturing process of the semiconductor package apparatus.
Fig. 2G is a schematic side cross-sectional view showing one process of the manufacturing process of the semiconductor package apparatus.
Fig. 3A is a bottom view showing one process of the manufacturing process of the semiconductor package apparatus.
Fig. 3B is a bottom view showing one process of the manufacturing process of the semiconductor package apparatus.
Fig. 3C is a bottom view showing one process of the manufacturing process of the semiconductor package apparatus.
Fig. 3D is a bottom view showing one process of the manufacturing process of the semiconductor package apparatus.
Detailed Description
Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
<1 > Circuit Structure of semiconductor Package
Fig. 1 shows a circuit configuration of a semiconductor package apparatus 50 according to an embodiment of the present invention. The semiconductor package apparatus 50 has a function of driving the motor 60. As shown in fig. 1, the semiconductor package device 50 has a 1 st package 1, a 2 nd package 2, a 3 rd package 3, a 4 th package 4, a 5 th package 5, a 6 th package 6, and a 7 th package 7. In the semiconductor package apparatus 50 of the present embodiment, 1 st to 7 th packages 7 are packaged as 1 st semiconductor packages.
The 1 st package 1 has a microcomputer 1A and a gate driver 1B. The 2 nd package 2 has a 1 st transistor M1 composed of an n-channel MOSFET (metal-oxide-semiconductor field-effect transistor: metal oxide semiconductor field effect transistor). The 3 rd package 3 has a 2 nd transistor M2 composed of a p-channel MOSFET. The 4 th package 4 has a 3 rd transistor M3 composed of an n-channel MOSFET. The 5 th package 5 has a 4 th transistor M4 composed of a p-channel MOSFET. The 6 th package 6 has a 5 th transistor M5 composed of an n-channel MOSFET. The 7 th package 7 has a 6 th transistor M6 composed of a p-channel MOSFET.
The 1 st to 6 th transistors M1 to M6 constitute an inverter IV.
The source of the 2 nd transistor M2 is connected to the application terminal of the input voltage Vin of the dc voltage. The drain of the 2 nd transistor M2 is connected to the drain of the 1 st transistor M1. The source of the 1 st transistor M1 is connected to the application terminal of the ground potential. That is, the 1 st transistor M1 and the 2 nd transistor M2 are connected in series.
The source of the 4 th transistor M4 is connected to the application terminal of the input voltage Vin. The drain of the 4 th transistor M4 is connected to the drain of the 3 rd transistor M3. The source of the 3 rd transistor M3 is connected to the application terminal of the ground potential. That is, the 3 rd transistor M3 and the 4 th transistor M4 are connected in series.
The source of the 6 th transistor M6 is connected to the application terminal of the input voltage Vin. The drain of the 6 th transistor M6 is connected to the drain of the 5 th transistor M5. The source of the 5 th transistor M5 is connected to the application terminal of the ground potential. That is, the 5 th transistor M5 and the 6 th transistor M6 are connected in series.
The motor 60 to be driven by the semiconductor package apparatus 50 is a 3-phase brushless DC motor. The connection node P1 connecting the 5 th transistor M5 and the 6 th transistor M6 is connected to the U-phase input terminal of the motor 60. The connection node P2 connecting the 3 rd transistor M3 and the 4 th transistor M4 is connected to the V-phase input terminal of the motor 60. The connection node P3 connecting the 1 st transistor M1 and the 2 nd transistor M2 is connected to the W-phase input terminal of the motor 60.
The gate driver 1B applies a driving voltage to the gates of the transistors M1 to M6 in response to an instruction from the microcomputer 1A, thereby performing switching control of the transistors M1 to M6. Thus, the motor 60 is driven by, for example, sinusoidal driving.
In the above embodiment, the p-channel MOSFET and the n-channel MOSFET are used for the upper transistor (for example, the 2 nd transistor M2) and the lower transistor (for example, the 1 st transistor M1) constituting one arm portion, but the present invention is not limited thereto, and for example, the upper transistor and the lower transistor may each be composed of an n-channel MOSFET. In this case, a bootstrap (bootstrap) capacitor for driving the upper transistor is included in the semiconductor package device.
The transistors are not limited to MOSFETs, and may be formed of, for example, IGBTs (insulated gate bipolar transistor: insulated gate bipolar transistors).
<2 > manufacturing Process of semiconductor packaging device
Next, a process for manufacturing the semiconductor package apparatus 50 according to the present embodiment will be described with reference to fig. 2A to 2G. Fig. 2A to 2G are schematic side sectional views showing the respective steps.
First, in the step shown in fig. 2A, a support substrate 52 having an adhesive 51 disposed on the upper surface is prepared, and 7 semiconductor packages 1 to 7 are arranged on the adhesive 51 as 1 st package 1 to 7 th package 7. In fig. 2A, the 4 th to 7 th packages 4 to 7 are not shown, but are actually disposed on the back side of the paper surface of fig. 2A. For example, a glass substrate, a silicon substrate, or the like is used as the support substrate 52.
Next, the process shown in fig. 2B is performed, and the adhesive 51 is sealed with a resin portion (mold resin) 501 so as to cover the entire 1 st package 1 to 7 th package 7.
Then, the process shown in fig. 2C is performed, and the support substrate 52 is detached from the 1 st to 7 th packages 1 to 7 sealed with the resin portion 501 together with the adhesive 51. Thus, as shown in fig. 2C, the lower surfaces of the 1 st to 7 th packages are exposed. That is, each terminal of each package is exposed downward. Further, a more specific configuration of each terminal will be described later.
Next, the process proceeds to a step shown in fig. 2D, and a 1 st insulating layer 502 is formed on the lower surface side of the 1 st to 7 th packages 1 to 7. Then, a via hole 502A is formed in the 1 st insulating layer 502 by laser processing or the like. The through hole 502A is a through hole penetrating in the thickness direction of the 1 st insulating layer 502, and is formed at a position corresponding to each terminal of the 1 st to 7 th packages.
Then, the process proceeds to a step shown in fig. 2E, and a 1 st wiring pattern portion 503 is formed inside the through hole 502A and on the lower surface of the 1 st insulating layer 502 by plating. In plating, copper plating is used, for example. In addition, for plating inside the through-hole, the inside of the through-hole may be filled with a conductive material (copper or the like) used for plating, or the conductive material may be formed only along the inner wall of the through-hole.
Next, the process shown in fig. 2F is performed, and a 2 nd insulating layer 504 is formed on the lower surface side of the 1 st insulating layer 502. Then, a via 504A is formed on the 2 nd insulating layer 504. The through hole 504A is formed at a position corresponding to a predetermined portion of the 1 st wiring pattern portion 503. Then, as shown in fig. 2F, a 2 nd wiring pattern portion 505 is formed inside the through hole 504A and on the lower surface of the 2 nd insulating layer 504 by plating.
Then, the process shown in fig. 2G is performed, and a resist layer 506 is formed on the lower surface side of the 2 nd insulating layer 504, thereby completing the semiconductor package apparatus 50. The resist layer 506 is laminated so that the resist layer 506 is not formed at a position of the 2 nd wiring pattern portion 505 corresponding to the portion exposed downward. The portion exposed downward is a terminal portion electrically connected to the printed board on which the semiconductor package apparatus 50 is mounted. By providing the resist layer 506, it is possible to suppress solder from shorting the terminal portions to each other when the semiconductor package apparatus 50 is mounted on the printed board by soldering. The resist layer 506 also has a function of protecting the circuit inside the semiconductor package apparatus 50 from external environments such as heat, dust, and moisture.
In addition, solder balls may be provided at the portions of the 2 nd wiring pattern portion 505 exposed downward.
In the semiconductor package apparatus 50 configured as shown in fig. 2G, the insulating portion 5001A is constituted by the 1 st insulating layer 502 and the 2 nd insulating layer 504. The 1 st wiring pattern portion 503 and the 2 nd wiring pattern portion 505 form a conductor portion 5001B. That is, the semiconductor package apparatus 50 has a wiring layer 5001, and the wiring layer 5001 includes an insulating portion 5001A and a conductor portion 5001B.
The semiconductor package device 50 of the present embodiment manufactured through the manufacturing process as described above can be wired by forming the conductor portion 5001B on the insulating portion 5001A by plating, and thus wire bonding is not required. In addition, the number of semiconductor packages to be mounted is less likely to be limited than in the conventional structure in which the package devices are stacked in the vertical direction.
In the semiconductor package apparatus 50, wiring is performed with respect to the insulating layers formed by stacking a plurality of layers such as the 1 st insulating layer 502 and the 2 nd insulating layer 504, and thus the degree of freedom of wiring can be increased in a limited space.
Further, since the transistor performance required for the motor to be driven is different, the semiconductor package device 50 is of various types in the case of coping with various motors, but a device packaged in advance is used, so that it is easy to cope with the case of various types.
<3 > wiring Structure of semiconductor packaging device
Next, a wiring structure of the semiconductor package apparatus 50 according to the present embodiment will be described with reference to fig. 3A to 3D.
Fig. 3A is a bottom view showing a state of the process shown in fig. 2C of the above-described manufacturing process, as viewed from below. That is, fig. 3A is a bottom view of the 1 st to 7 th packages sealed with the resin portion 501. As shown in fig. 3A, the plurality of terminals 10 of the 1 st package 1 are arranged on each side of the outer edge of the rectangular lower surface of the 1 st package 1 and are exposed downward. The terminal 10 includes driving terminals 10A to 10F described later.
The 2 nd package 2 has a control terminal 2A, a current-outflow terminal 2B, and a current-inflow terminal 2C, each of which is exposed downward. The 2 nd package 2 has a chip of the 1 st transistor M1 inside. The control terminal 2A is connected to the gate of the 1 st transistor M1. The current outflow terminal 2B is connected to the source of the 1 st transistor M1. The current inflow terminal 2C is connected to the drain of the 1 st transistor M1.
The 3 rd package 3 has a control terminal 3A, a current-outflow terminal 3B, and a current-inflow terminal 3C, each of which is exposed downward. The 3 rd package 3 has a chip of the 2 nd transistor M2 inside. The control terminal 3A is connected to the gate of the 2 nd transistor M2. The current outflow terminal 3B is connected to the drain of the 2 nd transistor M2. The current inflow terminal 3C is connected to the source of the 2 nd transistor M2.
The 4 th package 4 has a control terminal 4A, a current-outflow terminal 4B, and a current-inflow terminal 4C, each of which is exposed downward. The 4 th package 4 has a chip of the 3 rd transistor M3 inside. The control terminal 4A is connected to the gate of the 3 rd transistor M3. The current outflow terminal 4B is connected to the source of the 3 rd transistor M3. The current inflow terminal 4C is connected to the drain of the 3 rd transistor M3.
The 5 th package 5 has a control terminal 5A, a current-outflow terminal 5B, and a current-inflow terminal 5C, each of which is exposed downward. The 5 th package 5 has a chip of the 4 th transistor M4 inside. The control terminal 5A is connected to the gate of the 4 th transistor M4. The current outflow terminal 5B is connected to the drain of the 4 th transistor M4. The current inflow terminal 5C is connected to the source of the 4 th transistor M4.
The 6 th package 6 has a control terminal 6A, a current-outflow terminal 6B, and a current-inflow terminal 6C, each of which is exposed downward. The 6 th package 6 has a chip of the 5 th transistor M5 inside. The control terminal 6A is connected to the gate of the 5 th transistor M5. The current outflow terminal 6B is connected to the source of the 5 th transistor M5. The current inflow terminal 6C is connected to the drain of the 5 th transistor M5.
The 7 th package 7 has a control terminal 7A, a current-outflow terminal 7B, and a current-inflow terminal 7C, each of which is exposed downward. The 7 th package 7 has a chip of the 6 th transistor M6 inside. The control terminal 7A is connected to the gate of the 6 th transistor M6. The current outflow terminal 7B is connected to the drain of the 6 th transistor M6. The current inflow terminal 7C is connected to the source of the 6 th transistor M6.
Fig. 3B is a bottom view of the process shown in fig. 2D, as viewed from below. That is, fig. 3B shows a state after the 1 st insulating layer 502 is formed on the basis of the state of fig. 3A, and the via 502A is formed on the 1 st insulating layer 502.
As shown in fig. 3B, through holes 502A are formed at positions corresponding to the terminals 10 of the 1 st package 1. Further, through holes 502A are formed in the 2 nd to 7 th packages 2 to 7 at positions corresponding to the control terminals 2A to 7A, the current-flowing terminals 2B to 7B, and the current-flowing terminals 2C to 7C. In addition, 4 through holes 502A are formed for each of the current inflow terminals 2C to 7C, as an example.
Fig. 3C is a bottom view of the process shown in fig. 2E, as viewed from below. That is, fig. 3C shows a state after the 1 st wiring pattern portion 503 is formed inside the through hole 502A and the lower surface of the 1 st insulating layer 502 by plating in the state of fig. 3B.
As shown in fig. 3C, the 1 st wiring pattern portion 503 includes control wiring portions 503A to 503F, connection wiring portions 503G to 503I, a common connection wiring portion 503J, and a wiring portion 503K.
The control wiring portions 503A to 503F electrically connect the drive terminals 10A to 10F of the 1 st package 1 to the control terminals 2A to 7A, respectively. The 1 st package 1 can apply a driving voltage to the control terminals 2A to 7A via the control wiring portions 503A to 503F.
The connection wiring portions 503G to 503I electrically connect the current inflow terminals 3B, 5B, and 7B of the 3 rd package, the 5 th package, and the 7 th package to the current inflow terminals 2C, 4C, and 6C of the 2 nd package, the 4 th package, and the 6 th package, respectively.
The common connection wiring portion 503J electrically connects the current inflow terminals 3C, 5C, and 7C of the 3 rd package, the 5 th package, and the 7 th package in common.
The terminals 10 other than the driving terminals 10A to 10F of the 1 st package 1 are electrically connected to the wiring portion 503K.
Fig. 3D is a bottom view of the process shown in fig. 2F, as viewed from below. That is, fig. 3D shows a state in which the 2 nd insulating layer 504 is formed in the state of fig. 3C, the via hole 504A is formed on the 2 nd insulating layer 504, and the 2 nd wiring pattern portion 505 is formed inside the via hole 504A and on the lower surface of the 2 nd insulating layer 504 by plating.
As shown in fig. 3D, the 2 nd wiring pattern portion 505 includes ground wiring portions 505A to 505C, output wiring portions 505D to 505F, an input voltage application wiring portion 505G, and a circular wiring portion 505H.
The ground wiring portion 505A is electrically connected to the current-outflow terminal 2B of the 2 nd package 2 via the through hole 504A and the through hole 502A. The ground wiring portion 505B is electrically connected to the current-outflow terminal 4B of the 4 th package 4 via the through hole 504A and the through hole 502A. The ground wiring portion 505C is electrically connected to the current-outflow terminal 6B of the 6 th package 6 via the through hole 504A and the through hole 502A. The ground potential is applied to the ground wiring portions 505A to 505C by mounting the semiconductor package apparatus 50.
The ground wiring portion 505B overlaps the control wiring portion 503B in a bottom view. In addition, the ground wiring portion 505C overlaps the control wiring portions 503A to 503F in a bottom view. However, since the ground wiring portions 505B and 505C are different from the layers formed by the control wiring portions 503A to 503F, interference between the control wiring and the ground wiring of each transistor can be avoided in a limited wiring space.
The output wiring portions 505D to 505F are electrically connected to the connection wiring portions 503G to 503I via the through holes 504A, respectively. The output wiring portions 505D to 505F are electrically connected to input terminals of the respective phases of the motor 60.
The input voltage applying wiring portion 505G is electrically connected to the common connection wiring portion 503J via the through hole 504A. An input voltage Vin is applied to the input voltage application wiring portion 505G by mounting the semiconductor package apparatus 50. The input voltage Vin is, for example, 200V to 300V.
The output wiring portions 505D to 505F overlap the common connection wiring portion 503J in a bottom view. However, since the output wiring portions 505D to 505F are different from the layer formed by the common connection wiring portion 503J, interference between the output wiring and the input voltage application wiring can be avoided in a limited wiring space.
The circular wiring portion 505H is electrically connected to the connection terminal portion Tc via the through hole 504A, the wiring portion 503K, and other through holes 504A. Connection terminal portions Tc are arranged at positions corresponding to the circular wiring portions 505H. The 2 nd wiring pattern portion 505 includes a connection terminal portion Tc. In addition, the following structure may be adopted: the circular wiring portion 505H is connected to the circular wiring portion 503K via the through hole 504A, and the circular wiring portion 505H is connected to the connection terminal portion Tc by a wiring, not shown, in the 2 nd wiring pattern portion 505.
In the state of fig. 3D, a resist layer 506 is formed as in the process shown in fig. 2G, thereby completing the semiconductor package apparatus 50. Input terminals Tin1 and Tin2 are formed at the end of the input voltage application wiring portion 505G. Output terminals Tout1 to Tout3 are formed at the respective ends of the output wirings 505D to 505F. Ground terminals Tg1 to Tg3 are formed at the end portions of the ground wiring portions 505A to 505C, respectively. The resist layer 506 is formed so as to expose the input terminals Tin1, tin2, tout1 to Tout3, tg1 to Tg3 and the connection terminal portion Tc downward.
The connection terminal portion Tc is arranged along the 1 st side of the rectangular outer edge of the semiconductor package apparatus 50, along the 2 nd side opposite to the 1 st side, and along the 3 rd side sandwiched by the 1 st side and the 2 nd side. The input terminal Tin1 is arranged along the other side of the 2 nd side. The output terminals Tout1 to Tout3 and the input terminal Tin2 are arranged along the 4 th side opposite to the 3 rd side.
That is, the output terminals Tout1 to Tout3 and the input terminals Tin1 and Tin2 are adjacent to each other to form the 1 st group G1. The connection terminal portions Tc are adjacent to each other to form a group 2G 2. Since the 1 st group G1 and the 2 nd group G2 are disposed at the positions separated far from each other, insulation between the wiring of the high-voltage system connected to the output terminals Tout1 to Tout3 and the input terminals Tin1 and Tin2 and the wiring of the low-voltage system connected to the connection terminal portion Tc can be ensured when the semiconductor package device 50 is mounted on the printed board.
Further, as in group 2G 2, group 3G 3 including ground terminals Tg1 to Tg3 is disposed along side 1, but group 3G 3 is disposed apart from group 2G 2, and therefore insulation of the ground wiring connected to ground terminals Tg1 to Tg3 can be ensured at the time of mounting semiconductor package device 50.
<4 > the effects of the present embodiment
As described above, the semiconductor package apparatus (50) of the present embodiment includes: a wiring layer (5001) that has an insulating portion (5001A) and a conductive portion (5001B); a plurality of semiconductor packages (1-7) which are disposed in contact with the upper surface of the wiring layer; and a resin part (501) sealing the semiconductor package.
According to such a structure, wiring can be performed by forming the conductive portion on the insulating portion by plating, and wire bonding is not required. In addition, the limit on the number of semiconductor packages to be mounted can be reduced.
In the above configuration, the insulating portion has a plurality of insulating layers (502, 504) stacked in the vertical direction, and the conductive portion has wiring pattern portions (503, 505) arranged on the lower surface of the insulating layers. This can improve the degree of freedom of wiring in a limited wiring space.
In addition, the structure further comprises a resist layer (506) arranged on the lower surface of the wiring layer. This can suppress a short circuit of the conductive portion due to soldering or the like on the lower surface of the wiring layer.
In addition, the semiconductor package includes: 1 st package (1) having microcomputer (1A) and gate driver (1B); a 2 nd package (2) comprising a 1 st transistor (M1); and a 3 rd package (3) comprising a 2 nd transistor (M2) connected in series with the 1 st transistor. Since transistor performance required for a motor to be driven by the semiconductor package device is different, the semiconductor package device is a plurality of types in order to cope with various motors, but the semiconductor package device is constituted by packaged devices, and thus it is easy to cope with a plurality of types.
In addition, in the above structure, the semiconductor package further includes: a 4 th package (4) comprising a 3 rd transistor (M3); a 5 th package (5) comprising a 4 th transistor (M4) connected in series with the 3 rd transistor; a 6 th package (6) comprising a 5 th transistor (M5); and a 7 th package (7) including a 6 th transistor (M6) connected in series with the 5 th transistor. The insulating portion has a 1 st insulating layer (502) and a 2 nd insulating layer (504) located below the 1 st insulating layer.
Further, the conductive portion includes: control wiring sections (503A-503F) which are arranged on the lower surface of the 1 st insulating layer and electrically connect the terminals (10A-10F) of the 1 st package and the control terminals (2A-7A) of the 2 nd to 7 th packages; and each of the ground wiring portions (505A to 505C) disposed on the lower surface of the 2 nd insulating layer and electrically connected to the current outflow terminals (2B, 4B, 6B) of the 2 nd package, the 4 th package, and the 6 th package, wherein at least one of the control wiring portions overlaps at least one of the ground wiring portions when viewed from the bottom.
In this way, in the semiconductor package device for driving the motor including the inverter, the control wiring and the ground wiring of each transistor can be prevented from interfering with each other by forming 2 insulating layers in a limited wiring space.
In the above configuration, the conductive portion may include: connection wiring sections (503G-503I) which are arranged on the lower surface of the 1 st insulating layer and electrically connect the current outflow terminals (3B, 5B, 7B) of the 3 rd, 5 th, 7 th packages and the current inflow terminals (2C, 4C, 6C) of the 2 nd, 4 th, 6 th packages; a common connection wiring portion (503J) which is arranged on the lower surface of the 1 st insulating layer and electrically connects the current inflow terminals (3C, 5C, 7C) of the 3 rd, 5 th, and 7 th packages; output wiring portions (505D-505F) disposed on the lower surface of the 2 nd insulating layer and electrically connected to the connection wiring portions; and an input voltage applying wiring portion (505G) disposed on the lower surface of the 2 nd insulating layer and electrically connected to the common connecting wiring portion, wherein the common connecting wiring portion overlaps the output wiring portions when viewed from the bottom.
In this way, in the semiconductor package device for driving the motor including the inverter, the 2 insulating layers are formed in the limited wiring space, and the interference between the output wiring and the input voltage application wiring can be avoided.
In the above configuration, the conductive portion includes: output wiring sections (505D-505F) for electrically connecting the current-outflow terminals (3B, 5B, 7B) of the 3 rd, 5 th, 7 th packages and the connection points of the current-inflow terminals (2C, 4C, 6C) of the 2 nd, 4 th, 6 th packages; a voltage-application wiring section (505G) electrically connected to the current-inflow terminals (3C, 5C, 7C) of the 3 rd, 5 th, and 7 th packages; and connection terminal portions (Tc) for electrically connecting with the terminals (10) of the 1 st package. The output wiring portion and the voltage application wiring portion have respective ends (Tout 1 to Tout3, tin1, tin 2) located on the outer periphery of the wiring layer, and are adjacent to each other to form a 1 st group (G1), and the connection terminal portions are located on the outer periphery of the wiring layer, and are adjacent to each other to form a 2 nd group (G2), and the 1 st group and the 2 nd group are located at separate positions.
In this way, in the semiconductor package device for driving the motor including the inverter, since the respective ends of the output wiring portion and the voltage application wiring portion, which are the high voltage system, and the respective connection terminal portions, which are the low voltage system, are formed in different groups and are located at separate positions from each other, insulation between the wirings of the high voltage system and the low voltage system can be ensured on the substrate on which the semiconductor package device is mounted.
The method for manufacturing the semiconductor package device (50) according to the present embodiment includes the steps of: step 1, disposing a plurality of semiconductor packages (1-7) on an adhesive (51), wherein the adhesive (51) is disposed on a supporting substrate (52); step 2, sealing the semiconductor package by using resin (501); a step 3 of detaching the support substrate and the adhesive from the resin; and a 4 th step of forming insulating layers (502, 504) on the lower surface side of the resin, forming through holes (502A, 504A) in the insulating layers, and forming wiring pattern portions (503, 505) on the lower surfaces of the through holes and the insulating layers at least once by plating.
Thus, wire bonding is not required for wiring, and the number of semiconductor packages to be mounted is suppressed from being limited, so that the semiconductor package device can be easily manufactured.
<5 > other >
The embodiments of the present invention have been described above, but various modifications can be made to the embodiments within the scope of the gist of the present invention.
For example, although the semiconductor package device having the inverter including 6 transistors is used in the above embodiment, the semiconductor package device for driving the motor does not need to have an inverter, and may have a structure including only 2 transistors connected in series. The use of the semiconductor package device is not limited to motor driving.
In addition, the semiconductor package device may include a component such as a chip capacitor in addition to the semiconductor package having the transistor, and may be packaged.
Industrial applicability
The present invention can be suitably used for a semiconductor package device for driving a motor, for example.
Description of the reference numerals
50: a semiconductor package device; 60: a motor; 1: 1 st packaging; 2: packaging 2; 3: 3 rd packaging; 4: 4, packaging; 5: packaging 5 th; 6: packaging the 6 th part; 7: 7, packaging; 1A: a microcomputer; 1B: a gate driver; m1: a 1 st transistor; m2: a 2 nd transistor; m3: a 3 rd transistor; m4: a 4 th transistor; m5: a 5 th transistor; m6: a 6 th transistor; IV: an inverter; p1 to P3: connecting the nodes; 51: a support substrate; 52: an adhesive; 501: a resin section; 502: a 1 st insulating layer; 502A: a through hole; 503: a 1 st wiring pattern portion; 504: a 2 nd insulating layer; 504A: a through hole; 505: a 2 nd wiring pattern portion; 506: a resist layer; 5001: a wiring layer; 5001A: an insulating part; 5001B: a conductor section; 10: a terminal; 10A to 10F: a driving terminal; 2A to 7A: a control terminal; 2B-7B: a current outflow terminal; 2C-7C: a current inflow terminal; 503A-503F: a control wiring section; 503G-503I: a connection wiring section; 503J: a common connection wiring section; 503K: a wiring section; 505A to 505C: a ground wiring section; 505D to 505F: an output wiring section; 505G: an input voltage applying wiring section; 505H: a circular wiring portion; tg 1-Tg 3: a ground terminal; tin1, tin2: an input terminal; tout1 to Tout3: an output terminal; tc: a connection terminal portion; g1: group 1; and G2: group 2; and G3: group 3.
Claims (6)
1. A semiconductor package apparatus, comprising:
a wiring layer having an insulating portion and a conductive portion;
a plurality of semiconductor packages disposed in contact with an upper surface of the wiring layer; and
a resin portion sealing the semiconductor package,
the semiconductor package includes:
1 st package having microcomputer and gate driver;
a 2 nd package comprising a 1 st transistor; and
a 3 rd package comprising a 2 nd transistor connected in series with the 1 st transistor.
2. The semiconductor package apparatus of claim 1, wherein,
the insulating part has a plurality of insulating layers stacked in the up-down direction,
the conductive portion has a wiring pattern portion disposed on a lower surface of the insulating layer.
3. The semiconductor package apparatus according to claim 1 or 2, wherein,
the semiconductor package device further includes a resist layer disposed on a lower surface of the wiring layer.
4. The semiconductor package apparatus according to claim 1 or 2, wherein,
the semiconductor package further includes:
a 4 th package including a 3 rd transistor;
a 5 th package including a 4 th transistor connected in series with the 3 rd transistor;
a 6 th package including a 5 th transistor; and
a 7 th package including a 6 th transistor connected in series with the 5 th transistor,
the insulating part has a 1 st insulating layer and a 2 nd insulating layer positioned below the 1 st insulating layer,
the conductive part has:
each control wiring part, they dispose on the lower surface of the said 1 st insulating layer, make each terminal of the said 1 st capsulation and each control terminal of the said 2 nd capsulation to 7 th capsulation electrically connect; and
each of the ground wiring portions disposed on the lower surface of the 2 nd insulating layer and electrically connected to each of the current-discharging terminals of the 2 nd, 4 th and 6 th packages,
at least one of the control wiring portions overlaps at least one of the ground wiring portions when viewed from the bottom.
5. The semiconductor package apparatus according to claim 1 or 2, wherein,
the semiconductor package further includes:
a 4 th package including a 3 rd transistor;
a 5 th package including a 4 th transistor connected in series with the 3 rd transistor;
a 6 th package including a 5 th transistor; and
a 7 th package including a 6 th transistor connected in series with the 5 th transistor,
the insulating part has a 1 st insulating layer and a 2 nd insulating layer positioned below the 1 st insulating layer,
the conductive part has:
each connection wiring part, they dispose on the lower surface of the said 1 st insulating layer, make the above-mentioned 3 rd encapsulated, 5 th encapsulated, 7 th encapsulated each electric current flow out terminal and above-mentioned 2 nd encapsulated, 4 th encapsulated, 6 th encapsulated each electric current flow in terminal electric connection;
a common connection wiring portion arranged on a lower surface of the 1 st insulating layer and electrically connecting the current inflow terminals of the 3 rd, 5 th, and 7 th packages together;
each output wiring part is arranged on the lower surface of the 2 nd insulating layer and is electrically connected with each connecting wiring part; and
an input voltage applying wiring portion disposed on the lower surface of the 2 nd insulating layer and electrically connected to the common connection wiring portion,
the common connection wiring portion overlaps with each of the output wiring portions when viewed from the bottom.
6. The semiconductor package apparatus according to claim 1 or 2, wherein,
the semiconductor package further includes:
a 4 th package including a 3 rd transistor;
a 5 th package including a 4 th transistor connected in series with the 3 rd transistor;
a 6 th package including a 5 th transistor; and
a 7 th package including a 6 th transistor connected in series with the 5 th transistor,
the conductive part has:
each output wiring part electrically connecting each current-flowing terminal of the 3 rd package, the 5 th package, and the 7 th package with each connection point of each current-flowing terminal of the 2 nd package, the 4 th package, and the 6 th package;
a voltage-application wiring section electrically connected to each current-inflow terminal of the 3 rd package, the 5 th package, and the 7 th package; and
connection terminal portions for electrically connecting with the terminals of the 1 st package,
the output wiring portion and the voltage application wiring portion are positioned at the outer edge of the wiring layer, adjacent to each other to form group 1,
the connection terminal portions are located at the outer edges of the wiring layer, adjacent to each other to form group 2,
the group 1 and the group 2 are located at separate locations.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2017-064909 | 2017-03-29 | ||
| JP2017064909 | 2017-03-29 | ||
| PCT/JP2018/008270 WO2018180235A1 (en) | 2017-03-29 | 2018-03-05 | Semiconductor package device and manufacturing method therefor |
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| CN110462825A CN110462825A (en) | 2019-11-15 |
| CN110462825B true CN110462825B (en) | 2023-07-11 |
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| JP (1) | JPWO2018180235A1 (en) |
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| WO (1) | WO2018180235A1 (en) |
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| TWI839521B (en) * | 2019-08-29 | 2024-04-21 | 日商力森諾科股份有限公司 | Method for manufacturing electronic component device and electronic component device |
| TWI845013B (en) * | 2022-11-08 | 2024-06-11 | 京元電子股份有限公司 | Semiconductor package assembly and semiconductor package substrate module |
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| CN202662593U (en) * | 2010-07-30 | 2013-01-09 | 富士电机株式会社 | Semiconductor device |
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| JPH0738240A (en) * | 1993-07-21 | 1995-02-07 | Rohm Co Ltd | Structure of hybrid integrated circuit device |
| JPH09326467A (en) * | 1996-06-04 | 1997-12-16 | Matsushita Electric Ind Co Ltd | Electronics |
| JPH11298110A (en) * | 1998-04-06 | 1999-10-29 | Sony Corp | Method of mounting electronic parts, and its mounting structure |
| JP2004104115A (en) * | 2002-08-21 | 2004-04-02 | Matsushita Electric Ind Co Ltd | Power module and method of manufacturing the same |
| US20040129986A1 (en) * | 2002-11-28 | 2004-07-08 | Renesas Technology Corp. | Nonvolatile semiconductor memory device and manufacturing method thereof |
| JP3759131B2 (en) * | 2003-07-31 | 2006-03-22 | Ｎｅｃエレクトロニクス株式会社 | Leadless package semiconductor device and manufacturing method thereof |
| JP2005217072A (en) * | 2004-01-28 | 2005-08-11 | Renesas Technology Corp | Semiconductor device |
| JP2007235004A (en) * | 2006-03-03 | 2007-09-13 | Mitsubishi Electric Corp | Semiconductor device |
| KR101493865B1 (en) * | 2007-11-16 | 2015-02-17 | 페어차일드코리아반도체 주식회사 | Semiconductor power module package with simplified structure and method of fabricating the same |
| JP5262552B2 (en) * | 2008-10-14 | 2013-08-14 | 富士電機株式会社 | Semiconductor device manufacturing method and semiconductor device |
| JP5436259B2 (en) * | 2010-02-16 | 2014-03-05 | 日本特殊陶業株式会社 | Multilayer wiring board manufacturing method and multilayer wiring board |
| JP2013070530A (en) * | 2011-09-22 | 2013-04-18 | Renesas Electronics Corp | Gate drive circuit, power conversion circuit, three-phase inverter and gate drive method |
| JP5456843B2 (en) * | 2012-05-24 | 2014-04-02 | 三菱電機株式会社 | Power supply |
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- 2018-03-05 JP JP2019509079A patent/JPWO2018180235A1/en active Pending
- 2018-03-05 WO PCT/JP2018/008270 patent/WO2018180235A1/en active Application Filing
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1463043A (en) * | 2002-05-31 | 2003-12-24 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
| CN202662593U (en) * | 2010-07-30 | 2013-01-09 | 富士电机株式会社 | Semiconductor device |
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| WO2018180235A1 (en) | 2018-10-04 |
| JPWO2018180235A1 (en) | 2020-02-06 |
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