CN110460332B - Centered equal ratio predictive electronic system - Google Patents
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
The invention discloses a centered equal ratio prediction electronic system, which relates to the fields of electronic technology, electric power, communication and the like, and solves the problem that the design process is complex when a predicted synchronous signal is delayed in the existing signal synchronous system; the time quantity of the lead and the lag can be always equal, and the lead and the lag have no relation with the frequency and the phase difference of the input signal; it can be seen from the waveform that the edges of the output signal are always located exactly in the middle of the edges of the two input signals. The centering equal-ratio prediction electronic system is different from the traditional phase-locked loop in convergence mode, and the feedback loop of the traditional phase-locked loop converges most rapidly only when in a critical damping state; the circuit at critical damping still needs to undergo many cycles to gradually converge into the locked sync state much slower than the fast convergence of the circuit in the present invention.
Description
Technical Field
The invention relates to the fields of electronic technology, power, communication and the like, in particular to a centering equal ratio prediction electronic system.
Background
In electronics, communications, power, and other large electronic systems requiring accurate clock synchronization, it is often desirable to synchronize multiple subsystems with a single clock signal. The on-site construction cables are required to be laid through a bridge or a trench in each subsystem of the same machine room, and the actual line length is tens of meters and hundreds of meters. Sometimes also at different floors, the cable may be up to several hundred meters long. The clock synchronization signal is an electromagnetic wave and the speed in the cable is about two thirds of the speed of vacuum light, i.e. about one microsecond delay every two hundred meters. If the system distance differences are large or the synchronization signal frequency is high, the phase errors are very obvious everywhere.
The current method for correcting the synchronous clock error of each system is to delay the synchronous signal of the nearby system by using a delay device. That is, delay is additionally added to the synchronous signal of the short-distance system, so that the synchronous signal is consistent with the delay amount of the synchronous signal of the long distance. In actual field construction, the specific delay value can only be measured and adjusted after installation because the cable connected to each subsystem often needs to traverse various hidden trench holes and the length cannot be accurately designed in advance. If one more distant subsystem is added to the finished large system, then the delay of all other existing subsystems needs to be reset all the way through.
Disclosure of Invention
The invention provides a centering equal ratio prediction electronic system, which aims to solve the problem that the design process is complex when a synchronous signal delay is predicted in the existing signal synchronous system.
The central equal ratio prediction electronic system comprises an input end INA, an input end INB, an output end, a clock input end, a first D trigger, a second D trigger, a third D trigger, a fourth D trigger, a first AND gate, a second OR gate, an NOT gate, a first data latch, a second data latch, a third data latch, a reversible counter, a subtracter, a first comparator, a second comparator, a first OR gate and a T trigger;
the input end INA is connected with the C input end of the first D trigger, and the input end INB is connected with the C input end of the fourth D trigger;
the clock input end is respectively connected with the CLK input end of the reversible counter, the CP input end of the counter and the C input end of the T trigger;
VCC is connected with the D input end of the first D trigger, the D input end of the second D trigger, the D input end of the third D trigger and the D input end of the fourth D trigger respectively;
the output end of the first AND gate is respectively connected with the CLR asynchronous input end of the first D trigger and the CLR asynchronous input end of the second D trigger, and the output end of the second AND gate is respectively connected with the CLR asynchronous input end of the third D trigger and the CLR asynchronous input end of the fourth D trigger;
the Q end of the first D trigger is respectively connected with the A input end of the first AND gate, the input end of the NOT gate and the A input end of the second OR gate, the Q end of the second D trigger is connected with the B input end of the first AND gate, the Q end of the third D trigger is respectively connected with the A input end of the second AND gate and the B input end of the second OR gate, and the Q end of the fourth D trigger is connected with the B input end of the first AND gate;
the output end of the second OR gate is respectively connected with the CE input end of the reversible counter, C of the first data latch
The output end of the NOT gate is connected with the I/D input end of the reversible counter, the output end Q [ N.0 ] of the reversible counter is connected with the D [ N.0 ] input end of the first data latch through N+1 data lines, and the Q [ N.0 ] output end of the first data latch is connected with the A input end of the subtracter through a D [ N.0 ] data bus;
the Q [ N..1] output end of the first data latch is connected with the D [ N-1..0] input end of the second data latch through a D [ N..1] data bus, and the Q [ N..0] output end of the second data latch is connected with the B input end of the subtracter;
the Y output end of the subtracter is connected with the D [ N..0] input end of the third data latch,
the Q [ N.0 ] output end of the third data latch is connected with the A input end of the first comparator through a P [ N.0 ] data bus, the Q [ N.0 ] output end of the third data latch is connected with the B input end of the second comparator through a data bus P [ N.1 ], the output end of the second comparator is connected with the B input end of the first OR gate, the Q [ N.0 ] output end of the counter is connected with the B input end of the first comparator through a data bus Q [ N.0 ], the Q [ N-1.0 ] output end of the counter is connected with the A input end of the second comparator through a data bus Q [ N-1.0 ], the output end of the first comparator is respectively connected with the CLR input end of the counter and the A input end of the first OR gate, and the output end of the first OR gate is connected with the T input end of the T trigger;
the Q output end of the T trigger is respectively connected with the C input end of the third data latch, the C input end of the second D trigger, the C input end of the third D trigger and the output end.
The invention has the beneficial effects that: the electronic system provided by the invention can automatically output a signal which is lagging than the first arrival signal and is advanced than the second arrival signal according to different phases of two input signals; the time quantity of the lead and the lag can be always equal, and the lead and the lag have no relation with the frequency and the phase difference of the input signal; it can be seen from the waveform that the edges of the output signal are always located exactly in the middle of the edges of the two input signals.
Drawings
FIG. 1 is a schematic circuit diagram of a centered on-scale predictive electronic system according to the present invention;
FIG. 2 is a waveform diagram of three signals Fa, fb and Fx in a centered equal ratio predictive electronic system according to the invention; the three signal edges in the figure arrive in the sequence of the input signal Fa, the output signal Fx and the input signal Fb, with time difference ta=tb.
Detailed Description
In a first embodiment, a central equal ratio prediction electronic system is described with reference to fig. 1, and includes an input terminal INA, an input terminal INB, an output terminal OUT, a clock input terminal OSC, a first D flip-flop U1, a second D flip-flop U2, a third D flip-flop U10, a fourth D flip-flop U4, a first and gate U3, a second and gate U11, a second or gate U18, an not gate U5, a first data latch U7, a second data latch U8, a third data latch U12, a reversible counter U6, a counter U15, a subtractor U9, a first comparator U13, a second comparator U14, a first or gate U16, and a T flip-flop U17;
the input end INA is connected with the C input end of the first D trigger U1, and the input end INB is connected with the C input end of the fourth D trigger U4;
the clock input end OSC is respectively connected with the CLK input end of the reversible counter U6, the CP input end of the counter U15 and the C input end of the T trigger U17;
VCC is connected with the D input end of the first D trigger U1, the D input end of the second D trigger U2, the D input end of the third D trigger U10 and the D input end of the fourth D trigger U4 respectively;
the output end of the first AND gate U3 is respectively connected with the CLR asynchronous input end of the first D trigger U1 and the CLR asynchronous input end of the second D trigger U2, and the output end of the second AND gate U11 is respectively connected with the CLR asynchronous input end of the third D trigger U10 and the CLR asynchronous input end of the fourth D trigger U4;
the Q end of the first D trigger U1 is respectively connected with the A input end of the first AND gate U3, the input end of the NOT gate U5 and the A input end of the second OR gate U18, and the Q end of the second D trigger U2 is connected with the B input end of the first AND gate U3;
the Q end of the third D trigger U10 is respectively connected with the A input end of the second AND gate U11 and the B input end of the second OR gate U18, the Q end of the fourth D trigger U4 is connected with the B input end of the first AND gate U11, the output end of the second OR gate U18 is respectively connected with the CE input end of the reversible counter U6, the C input end of the first data latch U7 and the C input end of the second data latch U8, and the output end of the NOT gate U5 is connected with the reversible counter U6The input end is connected, and the output end Q [ N..0 of the reversible counter U6]D [ n..0] with the first data latch U7 through n+1 data lines]The input terminal is connected, Q [ N..0] of the first data latch U7]The output end passes through D [ N. ] 0]The data bus is connected to the A input of the subtractor U9, Q [ N..1] of the first data latch U7]The output end passes through D [ N. ] 1]D [ N-1..0] of the data bus and the second data latch U8]The input is connected, Q [ N..0] of the second data latch U8]The output end is connected with the B input end of the subtracter U9, and the Y output end of the subtracter U9 is connected with D [ N..0] of the third data latch U12]The input end is connected;
the Q [ N.0 ] output end of the third data latch U12 is connected with the A input end of the first comparator U13 through a P [ N.0 ] data bus, the Q [ N.0 ] output end of the third data latch U12 is connected with the B input end of the second comparator U14 through a data bus P [ N.1 ], and the output end of the second comparator U14 is connected with the B input end of the first OR gate U16;
the output end of the Q [ N.0 ] of the counter U15 is connected with the input end B of the first comparator U13 through a data bus Q [ N.0 ], and the output end Q [ N-1.0 ] of the counter U15 is connected with the input end A of the second comparator U14 through a data bus Q [ N-1.0 ];
the output end of the first comparator U13 is respectively connected with the CLR input end of the counter U15 and the A input end of the first OR gate U16, and the output end of the first OR gate U16 is connected with the T input end of the T trigger U17;
the Q output terminal of the T flip-flop U17 is connected to the C input terminal of the third data latch U12, the C input terminal of the second D flip-flop U2, the C input terminal of the third D flip-flop U10, and the output terminal OUT, respectively.
In this embodiment, the signal output period of the synchronization signal output circuit has a linear relationship with the input value; the third data latch U12, the counter U15, the first comparator U13, the second comparator U14, the first or gate U16 and the T flip-flop U17 form a synchronous signal output circuit, the signal is output from the output terminal OUT, the period of the output signal is equal to the period of the high-frequency clock signal input from the clock input terminal OSC multiplied by the value output by the third data latch U12, and the duty ratio is 50%; if the period of the high-frequency clock signal input by the clock input terminal OSC is T, the value output by the third data latch U12 is X, and the period T of the output terminal OUT signal has a linear relationship:
T＝Xt
the linear relation is very important to ensure the rapid convergence and stable operation of the loop synchronous locking, and if the output signal period and the input value are not in a linear relation, the rapid convergence performance of the circuit can be affected, and even self-oscillation can be caused in the synchronous adjustment process; in addition, the duty ratio is ensured to be close to 50%, the locking range in the synchronous process can be enlarged, and if the duty ratio is too large or too small, the frequency discrimination phase discrimination range of synchronous prediction can be reduced;
in this embodiment, two signals Fa and Fb with frequencies f are input to the input terminal INA and the input terminal INB respectively, and the rising edge of the input signal Fa arrives earlier than the rising edge of the input signal Fb, after the circuit enters the synchronous lock state, a square wave signal Fx can be output at the output terminal OUT, the frequency of the output signal Fx is automatically equal to f, the input signal Fa leads the output signal Fx and has a time difference TA, and the output signal Fx leads the input signal Fb and has a time difference TB; TA is equal to TB in value, and input signal Fa leads output signal Fx, which leads input signal Fb; as can be seen from the waveform diagram 2, the rising edge of the output signal Fx is always located in the middle of the rising edges of the input signal Fa and the input signal Fb, and this middle proportion of the operating state is independent of the frequency f and the time difference between the input signal Fa and the input signal Fb.
In this embodiment, a first D flip-flop U1, a second D flip-flop U2, a third D flip-flop U10, a fourth D flip-flop U4, a first and gate U3, and a second and gate U11 are adopted to form a three-input dual phase discriminator, and three-signal phase discrimination is performed on the square wave signal Fx output by the signal output terminal OUT, the signal Fa input by the signal a input terminal INA, and the input signal Fb input by the signal B input terminal INB; during the time difference TA and the time difference TB, the CE end of the reversible counter U6 is always kept valid and is in an up-counting or down-counting working state; during said time difference TA, a reversible counter U6The end is 0 and is in a count-down state, and each clock pulse is decremented by one; during the time difference TB +_6 of the up-down counter U>The end is 1, in an up-counting state, each clock pulse is increased by one; the three-input double-phase detector NAND gate U5, the second OR gate U18 and the reversible counter U6 form a proportional error measuring circuit, and if the numerical value in the reversible counter U6 is G before the time difference TA starts, and after the circuit experiences the TA and the TB with the same numerical value, the numerical value can be restored to G, and the circuit is in a synchronous locking state;
in the present embodiment, the output value of the proportional error measuring circuit is output from the subtractor U9; after the equality of TA and TB, the data latch U7 latches the value output by the up-down counter U6 as G; once TA is not equal to TB, the reversible counter U6 generates a count error 2Δ, the first data latch U7 latches a value equal to G-2Δ, and outputs it to the subtractor U9 and the data latch U8 via the bus D [ n..0 ];
the data input D N-1..0 of the second data latch U8 is connected to the bus D n..1 in the sense of a binary right shift by one bit, such that the data in the second data latch U8 is equal to half the output value of the first data latch U7; the clock input terminal C of the second data latch U8 is connected with the clock input terminal of the first data latch U7, and as can be seen from the time relation, the second data latch U8 outputs data with one period delay than the first data latch U7; the data characteristics output from the subtractor U9 can be described by the following formula;
G N+1 ＝G N -2d N+1 +Δ N
for the n+1th proportional synchronization process, the proportional error measures the output G N+1 Should be equal to the last output G N Subtracting the current measurement error delta N+1 Is 2 times of the previous measurement error delta N Adding;
the centering equal ratio prediction circuit can complete synchronous locking by two periods, and achieves rapid convergence; the value output by the third data latch U12 is X and has a linear relationship with the period T of the output terminal OUT signal, if the rising edge time of the input signal Fa or the input signal Fb is changed in the nth proportional synchronization process, so that the time difference TB is changed, the circuit only needs to be re-synchronized twice, that is, after the n+2th time, the re-synchronization process of ta=tb can be implemented.
The convergence mode of the centering equal ratio prediction electronic system is different from that of the traditional phase-locked loop, and the feedback loop of the traditional phase-locked loop only has the fastest convergence when in a critical damping state; the circuit at critical damping still needs to undergo many cycles to gradually converge into the locked-in state much slower than the fast convergence of the circuit in this embodiment.
Claims (6)
1. A centered geometric prediction electronic system; the device comprises an input end INA, an input end INB, an output end (OUT), a clock input end (OSC), a first D trigger (U1), a second D trigger (U2), a third D trigger (U10), a fourth D trigger (U4), a first AND gate (U3), a second AND gate (U11), a second OR gate (U18), a NOT gate (U5), a first data latch (U7), a second data latch (U8), a third data latch (U12), a reversible counter (U6), a counter (U15), a subtracter (U9), a first comparator (U13), a second comparator (U14), a first OR gate (U16) and a T trigger (U17); the method is characterized in that;
the input end INA is connected with the C input end of the first D trigger (U1), and the input end INB is connected with the C input end of the fourth D trigger (U4);
the clock input end (OSC) is respectively connected with the CLK input end of the reversible counter (U6), the CP input end of the counter (U15) and the C input end of the T trigger (U17);
VCC is respectively connected with the D input end of the first D trigger (U1), the D input end of the second D trigger (U2), the D input end of the third D trigger (U10) and the D input end of the fourth D trigger (U4);
the output end of the first AND gate (U3) is respectively connected with the CLR asynchronous input end of the first D trigger (U1) and the CLR asynchronous input end of the second D trigger (U2), and the output end of the second AND gate (U11) is respectively connected with the CLR asynchronous input end of the third D trigger (U10) and the CLR asynchronous input end of the fourth D trigger (U4);
the Q end of the first D trigger (U1) is respectively connected with the A input end of the first AND gate (U3), the input end of the NOT gate (U5) and the A input end of the second OR gate (U18), the Q end of the second D trigger (U2) is connected with the B input end of the first AND gate (U3), the Q end of the third D trigger (U10) is respectively connected with the A input end of the second AND gate (U11) and the B input end of the second OR gate (U18), the Q end of the fourth D trigger (U4) is connected with the B input end of the first AND gate (U11), the output end of the second OR gate (U18) is respectively connected with the CE input end of the reversible counter (U6), the C input end of the first data latch (U7) and the C input end of the second data latch (U8);
the output of the NOT gate (U5) and the reversible counter (U6)The input end is connected with the output end Q [ N..0] of the reversible counter (U6)]D [ N..0] with the first data latch (U7) through N+1 data lines]The input terminal is connected to Q [ N..0] of the first data latch (U7)]The output end passes through D [ N. ] 0]Data bus and subtracter (U9)Is connected to the A input of the first data latch (U7) Q [ N..1)]The output end passes through D [ N. ] 1]D [ N-1..0 of the data bus and the second data latch (U8)]The input end is connected;
the Q [ N..0] output end of the second data latch (U8) is connected with the B input end of the subtracter (U9), the Y output end of the subtracter (U9) is connected with the D [ N..0] input end of the third data latch (U12),
the Q [ N.0 ] output end of the third data latch (U12) is connected with the A input end of the first comparator (U13) through a P [ N.0 ] data bus,
the Q [ N..0] output end of the third data latch (U12) is connected with the B input end of the second comparator (U14) through the data bus P [ N..1], the output end of the second comparator (U14) is connected with the B input end of the first OR gate (U16);
the Q [ N.0 ] output end of the counter (U15) is connected with the B input end of the first comparator (U13) through a data bus Q [ N.0 ], and the Q [ N-1.0 ] output end of the counter (U15) is connected with the A input end of the second comparator (U14) through a data bus Q [ N-1.0 ];
the output end of the first comparator (U13) is respectively connected with the CLR input end of the counter (U15) and the A input end of the first OR gate (U16), and the output end of the first OR gate (U16) is connected with the T input end of the T trigger (U17);
the Q output end of the T trigger (U17) is respectively connected with the C input end of the third data latch (U12), the C input end of the second D trigger (U2), the C input end of the third D trigger (U10) and the output end (OUT).
2. The centered on-geometric prediction electronic system of claim 1, wherein; the signal output period of the synchronous signal output circuit has a linear relation with the input numerical value; a third data latch (U12), a counter (U15), a first comparator (U13), a second comparator (U14), a first OR gate (U16) and a T trigger (U17) form a synchronous signal output circuit, signals are output from an output end (OUT), the period of the output signals is equal to the period of a high-frequency clock signal input by a clock input end (OSC) multiplied by the value output by the third data latch (U12), and the duty ratio is 50%; if the period of the high-frequency clock signal input by the clock input terminal (OSC) is T and the value output by the third data latch (U12) is X, there is a linear relationship with the period T of the signal input by the output terminal (OUT):
T＝Xt。
3. the centered on-geometric prediction electronic system of claim 1, wherein; two input signals Fa and Fb with the frequency f are respectively input through an input end INA and an input end INB, the rising edge of the input signal Fa arrives earlier than the rising edge of the input signal Fb, after the circuit enters a synchronous locking state, a signal Fx is output at an output end (OUT), the frequency of the output signal Fx is automatically equal to f, the input signal Fa leads the output signal Fx and the time difference is TA, and the output signal Fx leads the input signal Fb and the time difference TB; the time difference TA and the time difference TB are equal in value; the rising edge of the output signal Fx is always located at the middle position of the rising edges of the input signal Fa and the input signal Fb.
4. A centered, geometric prediction electronic system according to claim 3, characterized in that; a first D trigger (U1), a second D trigger (U2), a third D trigger (U10), a fourth D trigger (U4), a first AND gate (U3) and a second AND gate (U11) form a three-input double-phase discriminator, and three-signal phase discrimination is carried OUT on a square wave signal Fx output by a signal output end (OUT), an input signal Fa of an input end INA and an input signal Fb of an input end INB; during the time difference TA and the time difference TB, the CE end of the reversible counter (U6) is kept valid and is in an up-counting or down-counting working state; during said time difference TA, a reversible counter (U6)The end is 0 and is in a count-down state, and each clock pulse is decremented by one; during said time difference TB +_of the reversible counter (U6)>The end is 1, in an up-counting state, each clock pulse is increased by one; the three-input double phase detector NAND gate (U5), the second OR gate (U18) and the reversible counter (U6)) And a proportional error measuring circuit is formed, if the numerical value in the reversible counter (U6) is G before the time difference TA starts, and after the proportional error measuring circuit passes through the time difference TA and the time difference TB, the numerical value returns to G, so that the whole system is in a synchronous locking state.
5. The centered on-geometric prediction electronic system of claim 4, wherein; the output value of the proportional error measuring circuit is output from the subtracter (U9); after the equal time difference TA and the time difference TB, the first data latch (U7) latches the value output by the reversible counter (U6) to be G; when the time difference TA is not equal to the time difference TB, the reversible counter (U6) generates a counting error of 2 delta, the first data latch (U7) latches a value equal to G-2 delta, and the value is output to the subtracter (U9) and the second data latch (U8) through a bus D [ N..0 ];
the data input D [ N-1..0] of the second data latch (U8) is connected to the bus D [ N..1], such that the data in the second data latch (U8) is equal to half the output value of the first data latch (U7); the clock input end C of the second data latch (U8) is connected with the clock input end of the first data latch (U7), and the second data latch (U8) has one period delay than the output data of the first data latch (U7); the data output from the subtractor (U9) is expressed as follows:
G N+1 ＝G N -2Δ N+1 +Δ N
namely: for the n+1th proportional synchronization process, the proportional error measures the output G N+1 Should be equal to the last output G N Subtracting the current measurement error delta N+1 Is 2 times of the previous measurement error delta N And (5) adding.
6. The centered on-geometric prediction electronic system of claim 5, wherein; the prediction circuit adopts two periods to complete synchronous locking; the value output by the third data latch (U12) is X and has a linear relationship with the period T of the input signal at the output terminal (OUT), if the rising edge time of the input signal Fa or the input signal Fb is changed during the nth proportional synchronization process, so that the time difference TB is changed, the circuit only needs to be re-synchronized twice, that is, after the n+2th time, the re-synchronization process of ta=tb is implemented.
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| CN102256118A (en) * | 2011-08-15 | 2011-11-23 | 成都市广达电子电讯技术开发有限公司 | Synchronous circuit and method for TS (Telecommunication Service) code streams |
| CN104485947A (en) * | 2014-12-30 | 2015-04-01 | 中南民族大学 | Digital phase discriminator used for GPS tame crystal oscillator |
| CN108710028A (en) * | 2018-04-28 | 2018-10-26 | 吉林省广播电视研究所(吉林省新闻出版广电局科技信息中心) | Random frequency modulation sampling probability measures the device and method of electronic signal phase difference |
| CN210518271U (en) * | 2019-09-11 | 2020-05-12 | 长春思拓电子科技有限责任公司 | Intermediate geometric proportion prediction circuit |
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