CN110457160A - A kind of error correction method and device - Google Patents
A kind of error correction method and device Download PDFInfo
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- CN110457160A CN110457160A CN201910590555.9A CN201910590555A CN110457160A CN 110457160 A CN110457160 A CN 110457160A CN 201910590555 A CN201910590555 A CN 201910590555A CN 110457160 A CN110457160 A CN 110457160A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
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- Quality & Reliability (AREA)
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- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Detection And Correction Of Errors (AREA)
Abstract
This application involves a kind of error correction method and devices, which comprises each data block of each first memory block is divided into multiple sub-blocks by preset rules；The sub-block chosen the first memory block of identical coding from each first passage, the identical data block for originating bit address is chosen from the first memory block of each selection, chooses identical starting bit address from the data block of each selection, the sub-block composition data groups of multiple identical starting bit address；The second check code for data group described in error correction is generated, and is stored in second memory block.Multiple error-correcting is carried out to the data of each first memory block by the first check code and the second check code, strengthen error correcting capability, improve the probability of successful correction, and the storage location of the data of each memory block is all one-to-one, the complexity and operand for reducing error correction, improve the speed of error correction.
Description
Technical field
This application involves solid-state storage control field more particularly to a kind of error correction methods and device.
Background technique
Certain Nand Flash storage devices for being strict with processing mistake are read such as the SSD of Enterprise grade
The data or lost data for getting mistake will cause serious consequence.Most start the error probability of Nand Flash and the matter of chip
It measures related, writes the increase of number as Nand Flash is smeared, it is other that higher and higher error probability concentrates on single channel
In Nand Flash, when reading the data on Nand Flash, it may appear that reading interference causes error in data.Therefore it is writing
When entering Nand Flash, other than data are written, additional again the ECC for being able to achieve error checking and correction techniques can be written
(Error Correct Code) check code come carry out it is such corrigendum error in data work, such as BCH (Bose Chaudhuri
Hocquenghem code), LDPC Code (Low Density parity check code) etc..ECC(Error
Correct Code) check code operation and calculation mode be to be carried out on Nand Flash storage device.In order to accommodate and
These ECC check codes are stored, Nand Flash will increase a small amount of additional memory space to store these ECC check codes；But by
It is limited in the free space for storing these ECC check codes, and the prior art is all under single channel, to single NandFlash
Using ECC error correction, cause ECC check code that can only realize primary verification to user data, or can only realize to limited quantity
Error in data is verified, therefore ECC check code corrects the ineffective of mistake.
Summary of the invention
In order to solve the above-mentioned technical problem or it at least is partially solved above-mentioned technical problem, this application provides one kind to entangle
Wrong method and device.
In a first aspect, this application provides a kind of error correction method, including second channel and at least one first passage, each
First passage is connected with multiple the first memory blocks that data are handled by the first passage, and second channel is connected with multiple pass through
Second memory block of the second channel processing data；
Each first memory block includes multiple data blocks, and each data block includes user data, and for error correction to application
First check code of user data；
The described method includes:
Each data block of each first memory block is divided into multiple sub-blocks by preset rules；
The first memory block that identical coding is chosen from each first passage is chosen identical from the first memory block of each selection
Originate bit address data block, from the data block of each selection choose it is identical starting bit address sub-block, multiple identical
The sub-block composition data group of beginning bit address；
The second check code for data group described in error correction is generated, and is stored in second memory block.
Preferably, corresponding multiple second check codes of same data block are by the sequential storage of corresponding sub-block in second
In memory block.
Preferably, the preset rules are as follows: be divided into the user data of the same data block by preset length equal length
Multiple sub-blocks；And the length of each sub-block is preset length.
Preferably, the preset rules are as follows: by the user data of the same data block and the user data corresponding
One check code is divided into multiple sub-blocks by preset length equal length；
The sub-block length that each data block finally divides is less than or equal to the preset length.
Preferably, the method also includes: according in each first passage it is identical starting bit address data block it is corresponding
Multiple second check codes generate the third check code for being used for the multiple second check code of error correction.
Preferably, before the third check code in the generation for the multiple second check code of error correction, the method
Further include: the filling of each second check code identical data is made that the length is preset lengths.
Preferably, each third check code is stored in the second memory block in multiple second check codes of its error correction most
Behind the second check code of the latter.
Because the length of the second check code has been filled with as preset length, third check code is stored in the second storage
In multiple second check codes of Qu Zhongqi error correction behind the last one second check code, third check code can be made in the second storage
Start bit of first check code of the starting bit address data block corresponding with the second check code of area's storage in the first memory block
Location is identical, plays one-to-one relationship, reduces the expense that addressing calculates.
Preferably, the sub-block composition data group of the multiple identical starting bit address, comprising:
It is logical that each first is successively laterally read since the first byte data of 1 sub-block of first first passage
First byte data of the sub-block of the identical starting bit address of the first memory block of the identical coding in road is read until successively lateral
After taking the first byte data of the sub-block of the last one first passage；
Jump and read the second byte data of the sub-block of first first passage, until successively laterally having read most
Second byte data of the sub-block of the latter first passage；
The third byte data for jumping and reading the sub-block of first first passage, it is logical until having read all first
The last byte data of the sub-block of the identical starting bit address of first memory block of the identical coding in road；
The whole byte data composition data group.
Second aspect, this application provides a kind of error correction devices, are equipped with second channel and at least one first passage, each
First passage is connected with the first memory block that at least one handles data by the first passage, and second channel, which is connected with, to be passed through
Second memory block of the second channel processing data；
Each first memory block includes several data blocks, and each data block includes user data, and for error correction to application
First check code of user data；
Described device includes:
Data division module, for each data block of each first memory block to be divided into multiple subnumbers by preset rules
According to block；
Data group comprising modules, for choosing the first memory block of identical coding from each first passage, from each selection
The first memory block choose the data block of identical starting bit address, choose identical starting bit address from the data block of each selection
Sub-block, the sub-block composition data group of multiple identical starting bit address；
Second check code generation module for generating the second check code for being used for data group described in error correction, and is stored in institute
It states in the second memory block in second channel.
The third aspect, this application provides a kind of error correction methods, which is characterized in that the described method includes:
The data block of identical starting bit address is read from the first memory block of the identical coding of each first passage, from each
The data block of reading reads user data and corresponds to the first check code of user data for error correction；
Error correction is carried out to corresponding user data according to first check code；
Obtain the erroneous user data that error correction can not be carried out by first check code；
It obtains the data group where the erroneous user data and is stored in the second storage for data group described in error correction
Second check code in area；
The data group is by choosing the first memory block of identical coding from each first passage, depositing from the first of each selection
Storage area chooses the data block of identical starting bit address, chooses the sub-block of identical starting bit address from the data block of each selection
And the sub-block composition of the multiple identical starting bit address obtained；
Error correction is carried out to the erroneous user data according to second check code；
If second check code can not carry out error correction to the erroneous user data, according to the erroneous user data
Corresponding first check code carries out error correction to the erroneous user data again.
Preferably, further include third check code for the second check code described in error correction, the acquisition can not be by described
The erroneous user data that one check code carries out error correction includes: identical in the second memory block for read the identical coding of second channel before
The second check code and third check code for originating bit address, according to the third check code to the second check code error correction.
Preferably, the third check code and the first check code are the of the same race check code different from second check code.
Above-mentioned technical proposal provided by the embodiments of the present application is had the advantages that compared with prior art compared to existing skill
The ECC error correction of art be by Nand Flash itself single under single channel storage ECC check code error correction for, the application is
An error correction is carried out using itself the first check code, uses second of the Nand Flash combination producing by different multiple channels
Check code carries out secondary error correction and strengthens the ability of error correction to form vertical and horizontal double error correction, be added significantly to success
The probability of error correction；In addition, the application also generates the third check code to the second check code error correction, entangled in the execution of the second check code
Before the changing of the relative positions is made, third check code first to the second check code error correction, ensure that the accuracy of the second check code in advance, thus further
Strengthen error correcting capability.
When generating the second check code and third check code, equal length is divided, to the curtailment finally divided
Carrying out data filling makes to reach preset length, generates the second check code of equal length, being filled to the second check code makes to reach
To preset length, to generate the third check code with the first check code equal length and be stored in the second memory block, make first
The data of the second memory block storage of first memory block and second channel in channel are all correspondingly, in error correction, to reduce
Addressing and address matching, the expense of data processing and computational complexity, accelerate the processing speed of error correction.
The additional cost for increasing second channel is not high, but the error correcting capability of data can but greatly improve, and with channel
Increase, the cost of Nand Flash memory chip can further decrease, and this design is that rationally and have economical and real very much
With value.
Detailed description of the invention
The drawings herein are incorporated into the specification and forms part of this specification, and shows and meets implementation of the invention
Example, and be used to explain the principle of the present invention together with specification.
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, for those of ordinary skill in the art
Speech, without any creative labor, is also possible to obtain other drawings based on these drawings.
Fig. 1 is the flow chart of the error correction method of one embodiment；
Fig. 2 is the application scenarios schematic diagram of the error correction method of one embodiment；
Fig. 3 is the data block schematic diagram of the error correction method of one embodiment；
Fig. 4 is that the error correction method neutron data block of one embodiment divides and the second check code generates schematic diagram；
Fig. 5 is that the error correction method neutron data block of another embodiment divides and the second check code generates schematic diagram；
Fig. 6 be one embodiment error correction method in generate the schematic diagram of the second check code and third check code；
Fig. 7 is the schematic diagram of the data block of the first memory block in the error correction method of one embodiment；
Fig. 8 is the schematic diagram that a data block is divided into sub-block in the error correction method of one embodiment；
Fig. 9 is to generate third check code after carrying out data filling to the second check code in the error correction method of one embodiment
Schematic diagram；
Figure 10 is the composition schematic diagram of data group in the error correction method of one embodiment；
Figure 11 is the schematic diagram of the error correction device of one embodiment；
Figure 12 is the flow chart of the error correction method of another embodiment.
Specific embodiment
To keep the purposes, technical schemes and advantages of the embodiment of the present application clearer, below in conjunction with the embodiment of the present application
In attached drawing, the technical scheme in the embodiment of the application is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the application, instead of all the embodiments.Based on the embodiment in the application, ordinary skill people
Member's every other embodiment obtained without making creative work, shall fall in the protection scope of this application.
Fig. 1 is the flow diagram of the error correction method of one embodiment.Described method includes following steps:
S110: each data block of each first memory block is divided into multiple sub-blocks by preset rules；
S120: choosing the first memory block of identical coding from each first passage, selects from the first memory block of each selection
The data block for taking identical starting bit address chooses the sub-block of identical starting bit address from the data block of each selection, multiple
The sub-block composition data group of identical starting bit address；
S130: the second check code for data group described in error correction is generated, and is stored in second memory block.
Fig. 2 is the application scenarios schematic diagram of the error correction method of one embodiment, and referring to Fig. 2, the error correction method is applied to
On Nand Flash storage device.One Nand Flash storage device includes multiple Block units, and 1 Block unit includes
Multiple Page units, 1 Page unit include storing the Main Area of user data and corresponding to for storing the user data
Check code Spare Area；One Nand Flash controller can once control simultaneously multiple channels to Nand Flash into
The processing such as reading and writing, erasing of row data；One channel is connected with multiple Nand that data processing is carried out by the channel
Flash.Nand Flash carries out the reading and writing processing of data as unit of Page unit, and data are carried out as unit of Block unit
Erasing processing.The first passage 11 corresponding first of the application stores 13rd area for storing user data 1311 and for error correction
First check code 1312 of user data, corresponding second memory block 14 of second channel 12 is for storing 1410 He of the second check code
Third check code 1412 for the second check code of error correction 1410；Wherein, the second check code 1410 is used for lateral error correction by difference
The identical coding of first passage 11 the first memory block 13 in user data 1311 or user data 1311 and its corresponding
The data of one check code 1312 composition；First memory block 13 and the second memory block 14 are Page unit.
Referring to Fig. 2, a Nand Flash controller controls multiple channels, and Channel 1-Channel N is first
Channel 11, several Nand Flash Page of lower connection are the first memory block 13, and Channel N+1 is second channel 12,
Its lower several Nand Flash Page connected is the second memory block 14.
Fig. 3 is 131 schematic diagram of data block of the error correction method of one embodiment；Referring to Fig. 3, the first memory block 13 packet
Including several data blocks 131, a data block includes user data 1311 and corresponding first check code 1312 of user data 1311,
Data 1-Data M is the storing data of user data 1311, and data length M, ECC Data 1-ECC Data K is first
The storing data of check code 1312, data length K.
Fig. 4 is that the error correction method neutron data block 1310 of one embodiment divides and the second check code 1410 generates signal
Figure；With reference to Fig. 4, the first memory block 13 of identical coding is chosen from the 1-N first passage 11, is stored from the first of each selection
It chooses the data block 131 of identical starting bit address, choose the son of identical starting bit address from the data block 131 of each selection in area 13
Data block 1310, the 1310 composition data group 132 of sub-block of multiple identical starting bit address；It generates and is used for error correction corresponding data
Second check code 1410 of group 132.Second check code 1410 is stored in corresponding second memory block 14 of second channel 12；
With reference to Fig. 4, sub-block 1310 is by by the user data 1311 and the number of users of the same data block 131
It is divided according to 1311 corresponding first check codes 1312 by preset length S equal length, at this point, what each data block 131 finally divided
1310 length of sub-block is less than or equal to the preset length S.
Fig. 5 is that the error correction method neutron data block 1310 of another embodiment divides and the second check code 1410 generates signal
Figure；With reference to Fig. 5, sub-block 1310 be by by the user data 1311 of the same data block 131 by preset length S equal length
It divides；And the data length M of user data 1311 can be predetermined length S and divide exactly, i.e., the length of each sub-block 1310
It is preset length S；At this point, the second check code 1410 generated is all that data length is equal.
Fig. 6 is the schematic diagram that the second check code 1410 and third check code 1412 is generated in one embodiment error correction method；
With reference to Fig. 6, a data block 131 is divided into the sub-block 1310 that multiple data lengths such as are at the preset lengths S, therefore 1-N
The data block 131 of the identical starting bit address in the first memory block 13 of identical coding is by the subdata divided under different first passages 11
Laterally binding forms several data groups 132 to 1310 form of block, generates multiple second check codes for data group 132 described in error correction
1410, according to this multiple second check code 1410, generate the third check code that multiple second check codes 1410 are corresponded to for error correction
1412。
Minimum unit based on Nand Flash damage is Block unit, chooses the first memory block 13 of identical coding (i.e.
Page unit), the usage amount of memory can be greatly reduced, the waste of memory is reduced.
Because the data length of the second check code 1410 be less than preset length S, generate third check code 1412 it
Before, it is preferable that filling each second check code 1410 with identical data makes the length is preset length S, such second verification
Code 1410 is in the starting bit address of the second memory block 14 storage and the rising in the first memory block 13 of sub-block 1310 of its error correction
Beginning bit address is identical, and 1412 length of third check code, first check code corresponding with the first memory block 13,1312 length generated
It is identical.
After filling, the starting bit address for recalculating corresponding second check code 1410 of user data 1311 is not needed,
It is not in the problem of being misaligned.
Third check code 1412 is stored in the second memory block 14 in multiple second check codes 1410 of its error correction finally
Behind one the second check code 1410, guarantee the starting bit address phase of third check code 1412 and the first check code 1312 in this way
Together, it is convenient to be convenient for addressing when error correction, accelerates calculation process speed.
Preferably, the first check code 1312 and third check code 1412 are LDPC code, and the second check code 1410 is BCH
Code.Using this 2 kinds of different codes can complementary error correction, greatly improve error correction effect and efficiency.
Fig. 7 is the schematic diagram of the data block 131 of the first memory block 13 in one embodiment error correction method；With reference to Fig. 7, N is taken
=4, Nand Flash controller control Channel 1-4 totally 4 first passages 11 and Channel 5 this second channel
12, each first passage 11 is connected with multiple Page units, and Page unit is the first memory block 13, and second channel 12 is connected with
Multiple Page units, the Page unit of second channel 12 are the second memory block 14, and the Page unit of first passage 11 includes 4
Data block 131, each data block 131 include the user data 1311 of (4096+16) Bytes and correspond to user data for error correction
The first check code 1312 of 1311 472Bytes, data block 131 are written sequentially in Page unit, first check code
1312 use LDPC code.
Fig. 8 is the schematic diagram that a data block 131 is divided into sub-block 1310 in the error correction method of one embodiment；Ginseng
Fig. 8 is examined, respectively taking a number from 1-4 first passage 11 is the Page unit of W, from the Page unit selection phase of each selection
With the data block 131 of starting bit address, the user data 1311 of the data block 131 including (4096+16) Bytes and for entangling
The LDPC code of the 472Bytes of the corresponding user data 1311 of mistake, takes preset length 257Bytes to the user of (4096+16) Bytes
Data equal length divides, and Byte 1-Byte 257 is first sub-block 1310, and Byte 258-Byte 514 is second
Sub-block 1310, and so on, the last one sub-block 1310 divided is Byte 3856-Byte 4112.Channel
5 be second channel 12, and the Page unit storage that number is W at Channel 5 is W's for the number of error correction first passage 11
Second check code 1410 of Page unit.
Fig. 9 is to generate third check code after carrying out data filling to the second check code in the error correction method of one embodiment
Schematic diagram；With reference to Fig. 9, the second check code 1410 uses BCH code, and each BCH code is less than preset length 257Bytes, to each
BCH code carries out data filling, and each BCH code is made to reach preset length 257Bytes, the i.e. data with a sub-block 1310
Equal length, multiple BCH codes of the data group 131 of the lower total 4 identical starting bit address of 4 first passages 11 of such error correction
It is 4112Bytes that total data length is identical as the data length of data group 131 of each error correction, to the multiple BCH error correction
Third check code 1412 and the first check code 1312 be checksum LDPC code of the same race, therefore corresponding third check code 1412
Data length identical as the data length of the first check code 1312 is also 472Bytes.It all corresponds, reduces in this way
Addressing and address matching, the expense of data processing and the cumbersome degree of operation, accelerate the processing speed of error correction.
The application also generates the third check code 1412 having to 1410 error correction of the second check code, holds in the second check code 1410
Before row corrective action, third check code 1412 first to 1410 error correction of the second check code, ensure that the second check code 1410 in advance
Accuracy, to further enhance error correcting capability.
In addition, equal length divides when generating the second check code 1410 and third check code 1412, divided to last
The sub-block 1310 of curtailment preset length S carry out data filling and make to reach preset length S, generate the of equal length
Two check codes 1410, being filled to the second check code 1410 makes to reach preset length S, to generate and the first check code 1312
The third check code 1412 of equal length is simultaneously stored in the second memory block 14, makes the first memory block 13 and second of first passage 11
The data of second memory block 14 storage in channel 12 are all correspondingly, in error correction, to reduce addressing and address matching, number
According to the expense of processing and the cumbersome degree of operation, the processing speed of error correction is accelerated.
Figure 10 is the composition schematic diagram of data group in the error correction method of one embodiment；With reference to Figure 10, from first first
1 sub-block 1310 in channel 11 starts the first memory block 13 for successively laterally reading the identical coding of each first passage 11
First byte data Byte 1 of the sub-block 1310 of identical starting bit address, until successively laterally read the last one the
After first byte data Byte 1 of the corresponding sub-block 1310 in one channel 11, jumps and read first first passage 11
Second byte data Byte 2 of sub-block 1310, the subdata until successively laterally having read the last one first passage 11
Second byte data Byte 2 of block 1310, then jump and read the third word of the sub-block 1310 of first first passage 11
Joint number is according to Byte 3, the son of the identical starting bit address in the first memory block 13 until having read the identical coding of all first passages 11
The last byte data of data block 1310 amount to 257Bytes*4=1028Bytes, the whole byte data
1028Bytes composition data group 132, and generate the second check code of 1 data group 132 for 1028Bytes described in error correction
1410, the second check code 1410 uses BCH code.
Above-described embodiment is the interior BCH code stored in the second memory block 14 and be used for error correction pair that a second channel 12 connects
The LDPC code for answering BCH code is carried out the user data 1311 stored in the first memory block 13 that 4 first passages 11 of error correction connect or is used
User data 1311 and the first check code 1312 that user data 1311 is corresponded to for error correction, but in practical applications, BCH code ratio is wanted
The length of the data of error correction is much smaller.
For example, in total number of first passage 11 on 33 SSD, the second channel 12 where BCH code accounts for Nand Flash
Use the 1/33=3.03% of data volume；
In total number of first passage 11 on 17 SSD, the second channel 12 where BCH code accounts for Nand Flash and uses number
According to the 1/17=5.88% of amount；
Therefore the additional cost for increasing second channel 12 is not high, but the error correcting capability of data can but greatly improve, and with
The increase in channel, cost can further decrease, it is this design be very rationally and have economy and practical value.
Figure 11 is the schematic diagram of the error correction device of one embodiment；The error correction device includes:
Data division module 01, for each data block of each first memory block to be divided into multiple sons by preset rules
Data block；
Data group comprising modules 02, for choosing the first memory block of identical coding from each first passage, from each choosing
It chooses the data block of identical starting bit address, choose identical starting bit address from the data block of each selection in the first memory block taken
Sub-block, it is multiple it is identical starting bit address sub-block composition data groups；
Second check code generation module 03 for generating the second check code for being used for data group described in error correction, and is stored in
In the second memory block in the second channel.
Figure 12 is the flow chart of the error correction method of another embodiment；The described method includes:
S210: read from the first memory block of the identical coding of each first passage it is identical starting bit address data block,
User data is read from the data block of each reading and the first check code of user data is corresponded to for error correction；
S220: error correction is carried out to corresponding user data according to first check code；
S230: the erroneous user data that error correction can not be carried out by first check code is obtained；
S240: it obtains the data group where the erroneous user data and is stored in second for data group described in error correction
Second check code of memory block；
Wherein, the data group by choosing the first memory block of identical coding from each first passage, from each selection
It chooses the data block of identical starting bit address, choose the son of identical starting bit address from the data block of each selection in the first memory block
Data block and obtain it is multiple it is identical starting bit address sub-blocks composition；
S250: error correction is carried out to the data group where the erroneous user data according to second check code；
S260: it if second check code can not carry out error correction to the erroneous user data, is used according to the mistake
Corresponding first check code of user data carries out error correction to the erroneous user data again.
Preferably, further include third check code for the second check code described in error correction, the acquisition can not be by described
The erroneous user data that one check code carries out error correction includes: identical in the second memory block for read the identical coding of second channel before
The second check code and third check code for originating bit address, according to the third check code to the second check code error correction.
When carrying out error-correction operation to data according to LDPC code or the error correction principle of BCH code, LDPC code or BCH code, if entangled
Mistake success, after the completion of correcting data error, the initial data of error correction can be by correct data cover；It, i.e., cannot be complete when error correction failure
Total correctness error correction, then LDPC code or BCH code will not modify to the original wrong data read out, initial data still reserved bit
Vicious unmodified initial data.
Step S230: the erroneous user data that error correction can not be carried out by first check code is obtained；The mistake obtained
User data, that is, original user data corrected without the first check code is misapplied, and the erroneous user data is through the first verification
What is confirmed in code error correction procedure error correction or cannot be unable to the user data of error correction completely completely, will not by part error correction,
Unmodified initial data can be left.
The error correction method of above-described embodiment carries out an error correction using itself the first check code 1312, using by different more
Second check code 1410 of the Nand Flash combination producing of a first passage 11 carries out secondary error correction, to be formed longitudinal and horizontal
To double error correction, the ability of error correction is strengthened, is added significantly to the probability of successful correction.
It should be noted that, in this document, the relational terms of such as " first " and " second " or the like are used merely to one
A entity or operation with another entity or operate distinguish, without necessarily requiring or implying these entities or operation it
Between there are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant are intended to
Cover non-exclusive inclusion, so that the process, method, article or equipment for including a series of elements not only includes those
Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or setting
Standby intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in the process, method, article or apparatus that includes the element.
The above is only a specific embodiment of the invention, is made skilled artisans appreciate that or realizing this hair
It is bright.Various modifications to these embodiments will be apparent to one skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and applied principle and features of novelty phase one herein
The widest scope of cause.
Claims (10)
1. a kind of error correction method, which is characterized in that including second channel and at least one first passage, each first passage connection
There are multiple the first memory blocks that data are handled by the first passage, second channel is connected with multiple by the second channel
Handle the second memory block of data；
Each first memory block includes multiple data blocks, and each data block includes user data, and corresponds to number of users for error correction
According to the first check code；
The described method includes:
Each data block of each first memory block is divided into multiple sub-blocks by preset rules；
Identical starting is chosen from the first memory block of each selection in the first memory block that identical coding is chosen from each first passage
The data block of bit address chooses the sub-block of identical starting bit address, multiple identical start bits from the data block of each selection
The sub-block composition data group of address；
The second check code for data group described in error correction is generated, and is stored in second memory block.
2. error correction method according to claim 1, which is characterized in that the preset rules are as follows:
The user data of the same data block is divided into multiple sub-blocks, and each sub-block by preset length equal length
Length be preset length.
3. error correction method according to claim 1, which is characterized in that the preset rules are as follows:
The user data of the same data block and corresponding first check code of the user data are drawn by preset length equal length
It is divided into multiple sub-blocks；
The sub-block length that each data block finally divides is less than or equal to the preset length.
4. error correction method according to claim 2, which is characterized in that the method also includes: according to each first passage
In identical starting bit address corresponding multiple second check codes of data block, generate and correspond to multiple second check codes for error correction
Third check code.
5. error correction method according to claim 4, which is characterized in that be used for the multiple second school of error correction in described generate
Test before the third check code of code, the method also includes: by each second check code identical data filling make the length is
Preset length.
6. error correction method according to claim 5, which is characterized in that the third check code is stored in the second memory block
In multiple second check codes of its error correction behind the last one second check code.
7. error correction method according to claim 1, which is characterized in that the sub-block of the multiple identical starting bit address
Composition data group, comprising:
Each first passage phase is successively laterally read since the first byte data of 1 sub-block of first first passage
With the first byte data of the sub-block of the identical starting bit address of the first memory block of coding, until successively laterally having read
After first byte data of the sub-block of the last one first passage；
Jump and read the second byte data of the sub-block of first first passage, until successively laterally having read last
Second byte data of the sub-block of a first passage；
The third byte data for jumping and reading the sub-block of first first passage again, until having read all first passages
The last byte data of the sub-block of the identical starting bit address of first memory block of identical coding；
The whole byte data composition data group.
8. a kind of error correction device, which is characterized in that be equipped with second channel and at least one first passage, each first passage connection
There is at least one to handle the first memory block of data by the first passage, second channel is connected with through the second channel
Handle the second memory block of data；
Each first memory block includes several data blocks, and each data block includes user data, and corresponds to number of users for error correction
According to the first check code；
Described device includes:
Data division module, for each data block of each first memory block to be divided into multiple subdatas by preset rules
Block；
Data group comprising modules, for choosing the first memory block of identical coding from each first passage, from the of each selection
It chooses the data block of identical starting bit address, choose the subnumber of identical starting bit address from the data block of each selection in one memory block
According to block, the sub-block composition data group of multiple identical starting bit address；
Second check code generation module for generating the second check code for being used for data group described in error correction, and is stored in described the
In the second memory block in two channels.
9. a kind of error correction method, which is characterized in that the described method includes:
The data block of identical starting bit address is read from the first memory block of the identical coding of each first passage, from each reading
Data block read user data and correspond to the first check code of user data for error correction；
Error correction is carried out to corresponding user data according to first check code；
Obtain the erroneous user data that error correction can not be carried out by first check code；
Obtain data group where the erroneous user data and second memory block that is stored in for data group described in error correction
Second check code；
Wherein, the data group by choosing the first memory block of identical coding from each first passage, from the first of each selection
It chooses the data block of identical starting bit address, choose the subdata of identical starting bit address from the data block of each selection in memory block
Block and obtain it is multiple it is identical starting bit address sub-blocks composition；
Error correction is carried out to the erroneous user data according to second check code；
If second check code can not carry out error correction to the erroneous user data, corresponding according to the erroneous user data
The first check code again to the erroneous user data carry out error correction.
10. error correction method according to claim 9, which is characterized in that further include for the second check code described in error correction
Third check code include: reading the before the erroneous user data that the acquisition can not be carried out error correction by first check code
The second check code and third check code of identical starting bit address in second memory block of the identical coding in two channels, according to described the
Three check codes are to the second check code error correction.
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