CN110456610B - Auxiliary graph and method for optimizing process window of through hole layer - Google Patents
Auxiliary graph and method for optimizing process window of through hole layer Download PDFInfo
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- CN110456610B CN110456610B CN201910810196.3A CN201910810196A CN110456610B CN 110456610 B CN110456610 B CN 110456610B CN 201910810196 A CN201910810196 A CN 201910810196A CN 110456610 B CN110456610 B CN 110456610B
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The invention discloses a method for optimizing a process window of a through hole layer, which comprises the steps of firstly carrying out OPC correction on a layout pattern based on rules to obtain a new target pattern, adding a sub-resolution auxiliary pattern into the new target pattern, then finding out the part with too small process window, cutting out the bad points, locally carrying out inversion lithography to obtain an optimal layout pattern, obtaining optimal SRAF width selection (SBW 1 and SBW 2) and position selection (S2M, S S), and adopting ring-like SRAF to surround the periphery of the through hole, thereby not only meeting the requirement of mask shop process manufacturing, but also improving the process window of the through hole layer.
Description
Technical Field
The invention relates to the field of semiconductor device manufacturing processes, in particular to an auxiliary graph and a method for optimizing a through hole layer process window in mask manufacturing in a photoetching process.
Background
In the back-end process of the semiconductor, in order to form the metal interconnection line, a via hole needs to be formed between two adjacent metal lines to realize the upper and lower metal interconnections. As circuit density increases and critical dimensions become smaller, the spacing between metal lines and the size of vias become smaller and denser, even below sub-micron, easily resulting in too small a photolithographic process window for the vias, affecting product yield.
Meanwhile, when the integrated circuit pattern on the mask is transferred to the photoresist layer on the wafer through exposure, deformation often occurs due to the optical proximity effect, and as the critical dimension is reduced, the more obvious the deformation is brought, different deformations are produced after the pattern is transferred to the through holes with the same size in the sparse pattern area and the dense pattern area, and blind holes are easily produced in the isolated through holes.
The Sub-resolution auxiliary pattern (SRAF: sub-Resolution Assist Feature) is inserted around the through hole layer, so that the spatial frequency and the spatial image of the pattern can be effectively improved, the optical proximity effect correction (OPC) precision is improved, and the Sub-resolution auxiliary pattern plays a certain role in improving a process window.
SRAF is commonly used to improve the contrast (contrast) of the photolithography process, the depth of field (DOF) of the pattern, and the process redundancy (tolerance), thereby improving the Optical Proximity Correction (OPC) accuracy, and thus playing a role in improving the process window.
The small fluctuation of the pattern size of the mask plate can cause the huge fluctuation of the pattern line width on the silicon wafer, so that higher requirements are put on the process window, and the simple SRAF can not effectively improve the process window of the through hole.
In the optical proximity effect correction process, the conventional auxiliary pattern (AF) of the via layer mainly includes a side AF (side AF) and a corner AF (corner AF), as shown in fig. 1. For side AF, the main parameters are SBW (line width of AF), S2M (distance between AF and main pattern) and S2S (distance between AF and AF); for the burner AF, the main parameters are SBW (line width of AF) and S2M (distance between AF and main pattern). However, as the size of the through hole is continuously reduced, the value of the mask error factor (Mask Error Effect, MEEF) of the pattern is continuously increased, and accordingly, the small fluctuation of the size of the mask pattern may cause the large fluctuation of the line width of the pattern on the silicon wafer, so that a higher requirement is put on the process window, thereby ensuring a certain yield, and therefore, the simple SRAF cannot effectively improve the process window of the through hole.
Disclosure of Invention
The invention aims to provide an auxiliary graph for optimizing a through hole layer process window in a photoetching process.
The invention also provides a method for optimizing the process window of the through hole layer.
The auxiliary graph for optimizing the through hole layer process window is suitable for correcting optical proximity effect in a mask, is of a closed structure, and also comprises a main graph positioned in the central area of the auxiliary graph, and the auxiliary graph is positioned at the periphery of the main graph to form a closed surrounding structure.
The auxiliary graph is a multi-layer nested closed structure with at least two layers, and a certain interval is arranged between each two layers of structures.
In a further improvement, the main pattern is a through hole.
A further development is that the auxiliary pattern is a closed polygon or ring-like shape.
Further improvements are that the polygon or ring-like shape comprises at least horizontal, vertical, 45 degree, 135 degree sides.
A further improvement is that the through holes are located in silicon areas or isolation structure areas on the substrate.
The method for optimizing the process window of the through hole layer comprises the following steps of:
step one: and inputting a layout graph.
Step two: and carrying out rule-based optical proximity effect correction on the layout graph to obtain a new target graph, and adding a sub-resolution auxiliary graph SRAF into the new target graph.
Step three: and D, simulating the target pattern formed in the second step, finding out the points with too small process window, cutting out the points, and generating the free-form layout pattern through an inversion lithography technology.
Step four: the layout pattern generated by the inversion photoetching technology is simplified, and a ring-like auxiliary pattern SRAF is adopted to be inserted around the main pattern.
Step five: and (3) performing simulation again on the target graph subjected to the steps, and comparing the target graph with the graph obtained in the step (III).
Further, the layout pattern in the first step is a chip layout.
In the second step, the original pattern to be exposed on the semiconductor substrate is corrected based on the optical proximity effect of the rule, and the original pattern is calculated and corrected by using a computer and a software package to obtain a result pattern different from the original pattern, and the result pattern is input into the computer for archiving.
Further, in the third step, the inversion lithography is a process of correcting the optical proximity effect or optimizing the interaction between the light source and the mask, which is regarded as a problem of reverse processing, the target pattern after lithography is set as an ideal imaging result, and the mask image is calculated by inversion according to a transformation model of the space image of the imaging system according to the known imaging result.
Further, in the third step, the width selection and the position selection of the optimal auxiliary pattern SRAF are obtained through the layout pattern obtained through the inversion lithography technology.
Further, in the third step, the point with the too small process window is the point with the PV-band value being more than or equal to 10% of the line width; the PV-band value is obtained by combining different dosages and focal lengths, simulating the main pattern to obtain a plurality of exposure simulation patterns (connours), and obtaining the PV-band value by using the difference between the largest exposure simulation pattern and the smallest exposure simulation pattern.
Further, the ring-like auxiliary pattern SRAF in the fourth step is a closed polygon.
Further, the ring-like auxiliary pattern SRAF at least comprises horizontal, vertical, 45-degree and 135-degree edges.
Further, the PV-band value obtained by performing simulation on the target graph after the inserted ring-like auxiliary graph SRAF can be reduced by about 15%.
The auxiliary graph for optimizing the process window of the through hole layer adopts the ring-like SRAF to surround the periphery of the through hole, thereby not only meeting the requirements of mask manufacturing process and manufacturing, but also improving the process window of the through hole layer. The optimized through hole layer process window adopts the ring-like SRAF auxiliary graph, can efficiently and quickly realize the optimization of the through hole layer process window, and the optimized PV-band value meets the upper limit MA of a manufacturing target and is reduced by 15% compared with the PV-band value of the conventional SRAF addition.
Drawings
Fig. 1 is a schematic diagram of a conventional auxiliary pattern.
FIG. 2 is an inversion lithography ILT producing a free-form layout pattern.
Fig. 3 is a schematic view of a ring-like SRAF provided by the present invention.
Fig. 4 is a schematic of a PV-band formed using conventional saf patterns.
FIG. 5 is a schematic of a PV-band formed using SARF patterns of the present invention.
Fig. 6 is a flow chart of a method of optimizing a via layer process window in accordance with the present invention.
Detailed Description
In order to make the contents of the present invention more clear and understandable, the contents of the present invention will be described in detail with reference to specific embodiments and drawings, but the technical contents of the present invention are not limited to the specific embodiments given.
The invention is described in further detail below with reference to the drawings and the specific examples. Advantages and features of the invention will become more apparent from the following description and from the claims. It is noted that the drawings are in a very simplified form and utilize non-precise ratios, and are intended to facilitate a convenient, clear, description of the embodiments of the invention.
As described in the background section, in the optical proximity correction process, the conventional auxiliary pattern (AF) of the via layer mainly includes a side AF (side AF) and an AF (corner AF) at the corner. For side AF, the main parameters are SBW (line width of AF), S2M (distance between AF and main pattern) and S2S (distance between AF and AF); for the burner AF, the main parameters are SBW (line width of AF) and S2M (distance between AF and main pattern). The invention provides a new SRAF pattern, as shown in figure 3, because the limit of the current mask plate manufacturing process can only manufacture SRAF of horizontal, vertical, 45 degrees and 135 degrees at present, the layout simplifying process is executed by a mask design system to generate a simplified layout pattern corresponding to the layout pattern generated by the ILT, in addition, along with the reduction of process nodes, the simple SRAF can not well improve the process window of a through hole, so the invention adopts the ring-like SRAF to surround the periphery of the through hole, thereby not only meeting the requirement of the mask plate manufacturing process, but also improving the process window of a through hole layer.
The SRAF pattern of the present invention adopts a ring-like structure, an embodiment of which is shown in fig. 3, wherein a central area is a main pattern, that is, a through hole, and a ring-like structure surrounding two layers is adopted, and the embodiment adopts an octagonal structure because the octagon meets the basic requirements of horizontal, vertical, 45 ° and 135 ° SRAF. The octagon adopts an inner layer and an outer layer, the line width of the octagon of the inner layer is SBW1, the distance between the octagon of the inner layer and the main pattern is S2M, the line width of the octagon of the outer layer is SBW2, and the distance between the octagon of the two layers is S2S.
Based on the SRAF provided by the invention, a method for optimizing the process window of the through hole layer can be performed.
Referring to the drawings, the method for improving the via process window in this embodiment includes:
step one: and inputting a layout graph. And loading the chip layout of the original design.
Step two: and performing optical proximity effect correction (OPC) correction based on rules on the layout pattern to obtain a new target pattern, and adding a traditional sub-resolution auxiliary pattern into the new target pattern.
The addition of the auxiliary graphics is performed according to the auxiliary graphics rule, which is a well-known technology known to those skilled in the art, and will not be described here.
Step three: and (3) simulating the target pattern formed in the second step, finding out the points with too small process windows, cutting out the bad points, and generating a free-form layout pattern through inversion lithography ILT.
Inversion lithography (Inverse Lithography Technology, ILT), also called reverse lithography, is an algorithm that inverts and computes the desired pattern on a reticle with the pattern to be implemented on a silicon wafer as a target.
The inverse photoetching technology, namely, the process of Optical Proximity Correction (OPC) or light source-mask interaction optimization (SMO) is regarded as a problem of inverse treatment, a target graph after photoetching is set as an ideal imaging result, and a mask image is calculated in an inversion mode according to a known imaging result and a transformation model of an imaging system space image.
Although the purposes of ILT and OPC are exactly the same, the patterns on the exposed wafer and the design pattern are identical, but the method has completely different ideas. It not only corrects the design pattern to obtain the desired pattern on the wafer, but also uses the pattern to be implemented on the wafer as the target inversion to calculate the desired pattern on the mask. Inversion lithography obtains an ideal mask pattern through complex mathematical calculations. Masks designed in this way provide relatively high pattern contrast upon exposure.
Inversion lithography is very complex, and is particularly computationally intensive for the entire chip. It is currently common practice to complete the processing of the mask data using a common model correction (opc+sraf) and then to find out the unsatisfactory parts thereof. And intercepting out the bad points, and locally performing ILT processing to obtain the optimal correction. And finally, pasting the ILT processed part back into the data. Such local ILT processing may save a significant amount of computation time.
Here, the width selection (SBW 1, SBW 2) and the position selection (S2M, S S) of the optimum SRAF are obtained through the layout pattern obtained by ILT.
Here, the standard of too small process window is that PV-band is more than or equal to 10% of line width, through combining different dosages and focal lengths, a plurality of exposure simulation patterns are obtained by simulation on the main pattern, and the minimum exposure simulation pattern is subtracted by the maximum exposure simulation pattern, namely the PV-band value. The larger the PV-band value, the more unstable the point, where we cut out the point where PV-band is 10% or more of the line width, and perform inversion lithography ILT to generate a free form layout pattern.
Step four: the layout pattern generated by the ILT is simplified, and ring-like SRAF is adopted to be inserted around the main graph.
In combination with the above, the present embodiment inserts octagonal SRAFs around the main pattern.
Step five: and (3) performing simulation again on the target graph subjected to the steps, and comparing the target graph with the graph obtained in the step (III).
According to the invention, firstly, a new target graph is obtained by performing rule-based OPC correction on a layout graph, firstly, a traditional sub-resolution auxiliary graph is added in the new target graph, then, a part with a too small process window is found out, the bad points are cut out, and inversion photoetching technology (Inverse Lithography Technology, ILT) is performed on the part to obtain an optimal layout pattern, and the width selection (SBW 1, SBW 2) and the position selection (S2M, S S) of the optimal SRAF are obtained.
As shown in the simulation results of FIG. 4 and FIG. 5, FIG. 4 is simulation data of a conventional sub-resolution SRAF pattern, FIG. 5 is simulation data of a ring-like SRAF pattern, and by comparison, the simulation PV-band value of the conventional sub-resolution SRAF pattern is 6.75, and the PV-band value of the ring-like SRAF pattern of the invention is 5.75, which proves that the PV-band value obtained by simulation of a target pattern inserted into the ring-like pattern is reduced by nearly 15% compared with the PV-band value obtained by conventional SRAF addition, and the process window of a through hole layer is improved.
The above are only preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and variations of the present invention will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. A method for optimizing a via layer process window, comprising: comprising:
step one: inputting a layout graph;
step two: performing rule-based optical proximity effect correction on the layout graph to obtain a new target graph, and adding a sub-resolution auxiliary graph SRAF into the new target graph;
step three: simulating the target pattern formed in the second step, finding out the points with too small process window, cutting out the points, and generating a free-form layout pattern by an inversion lithography technology;
step four: simplifying the layout pattern generated by the inversion photoetching technology, and inserting the ring-like auxiliary pattern SRAF around the main pattern;
step five: and (3) performing simulation again on the target graph subjected to the steps, and comparing the target graph with the graph obtained in the step (III).
2. The method of optimizing a via layer process window of claim 1, wherein: the layout graph in the first step is a chip layout.
3. The method of optimizing a via layer process window of claim 1, wherein: in the second step, the original pattern to be exposed on the semiconductor substrate is calculated and corrected by using computer and software to obtain a result pattern different from the original pattern, and the result pattern is input into the computer for archiving.
4. The method of optimizing a via layer process window of claim 1, wherein: in the third step, inversion lithography is to consider the process of optical proximity correction or light source-mask interaction optimization as a problem of reverse processing, set the target pattern after lithography as an ideal imaging result, and calculate the mask image in an inversion way according to the known imaging result and the transformation model of the imaging system space image.
5. The method of optimizing a via layer process window of claim 1, wherein: in the third step, the layout pattern obtained by inversion lithography is selected to obtain the width selection and the position selection of the optimal auxiliary pattern SRAF.
6. The method of optimizing a via layer process window of claim 1, wherein: in the third step, the point with the too small process window is the point with the PV-band value being more than or equal to 10% of the line width; the PV-band value is obtained by combining different dosages and focal lengths, and simulating the main pattern to obtain a plurality of exposure simulation patterns, wherein the difference value between the CD of the largest exposure simulation pattern and the CD of the smallest exposure simulation pattern is the PV-band value.
7. The method of optimizing a via layer process window of claim 1, wherein: and step four, the ring-like auxiliary graph SRAF is a closed polygon.
8. The method of optimizing a via layer process window of claim 7, wherein: the ring-like auxiliary graph SRAF at least comprises horizontal, vertical, 45-degree and 135-degree edges.
9. The method of optimizing a via layer process window of claim 1, wherein: the PV-band value obtained by performing simulation on the target graph after the inserted ring-like auxiliary graph SRAF can be reduced by about 15%.
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| CN110716387B (en) * | 2019-11-26 | 2022-10-21 | 上海华力集成电路制造有限公司 | Scattering strip adding method |
| CN111027272B (en) * | 2019-11-28 | 2024-12-31 | 中国科学院微电子研究所 | Method and device for generating through hole layer layout |
| CN113050366B (en) * | 2019-12-27 | 2024-05-17 | 中芯国际集成电路制造(上海)有限公司 | Optical proximity correction method and system, mask, equipment and storage medium |
| CN111258188B (en) * | 2020-03-23 | 2022-08-09 | 上海华力集成电路制造有限公司 | Method for selecting optimum photoetching deviation of anchor point in SMO technology |
| CN111766761A (en) * | 2020-07-20 | 2020-10-13 | 长江存储科技有限责任公司 | Photomask manufacturing method |
| WO2022083977A1 (en) * | 2020-10-23 | 2022-04-28 | Asml Netherlands B.V. | Method for generating mask pattern |
| CN112346294B (en) * | 2020-11-13 | 2023-11-14 | 上海华力集成电路制造有限公司 | Multi-pattern sub-resolution auxiliary pattern adding method |
| CN113325667A (en) * | 2021-01-26 | 2021-08-31 | 上海先进半导体制造有限公司 | Method, device, equipment and medium for adding sub-resolution graph |
| CN113097207B (en) * | 2021-04-07 | 2022-05-31 | 中国科学院微电子研究所 | Redundant local loop insertion method based on process window |
| CN114036888A (en) * | 2021-10-29 | 2022-02-11 | 上海华力集成电路制造有限公司 | Auxiliary graph construction method and device, storage medium and equipment |
| CN115268224A (en) * | 2022-07-19 | 2022-11-01 | 华虹半导体(无锡)有限公司 | OPC method for improving through hole process window |
| CN115657417A (en) * | 2022-10-31 | 2023-01-31 | 上海华力微电子有限公司 | Target layout optimization method |
| CN116203791A (en) * | 2023-04-28 | 2023-06-02 | 合肥晶合集成电路股份有限公司 | Mask structure of semiconductor chip and semiconductor device |
| CN119047409B (en) * | 2024-10-30 | 2025-02-07 | 华芯程(杭州)科技有限公司 | SRAF graphic generation method, device, storage medium and electronic device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6801313B1 (en) * | 1999-07-28 | 2004-10-05 | Nec Electronics Corporation | Overlay mark, method of measuring overlay accuracy, method of making alignment and semiconductor device therewith |
| CN102411259A (en) * | 2011-11-28 | 2012-04-11 | 上海华力微电子有限公司 | Method and device for performing optical proximity correction on photomask design layout |
| CN109085736A (en) * | 2018-09-10 | 2018-12-25 | 德淮半导体有限公司 | The production method of optical adjacent correction method and mask plate |
| CN109814332A (en) * | 2019-03-15 | 2019-05-28 | 云谷（固安）科技有限公司 | A kind of mask plate, preparation method and display panel |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20100011756A (en) * | 2008-07-25 | 2010-02-03 | 주식회사 하이닉스반도체 | Method for optical proximity correction of layout inserting assist pattern |
| JP6335735B2 (en) * | 2014-09-29 | 2018-05-30 | Hoya株式会社 | Photomask and display device manufacturing method |
| CN104898367A (en) * | 2015-05-15 | 2015-09-09 | 上海集成电路研发中心有限公司 | Optical proximity correction method for improving through-hole process window |
| TWI710649B (en) * | 2017-09-12 | 2020-11-21 | 日商Ｈｏｙａ股份有限公司 | Photomask and method of manufacturing a display device |
-
2019
- 2019-08-29 CN CN202310333927.6A patent/CN116360205A/en active Pending
- 2019-08-29 CN CN201910810196.3A patent/CN110456610B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6801313B1 (en) * | 1999-07-28 | 2004-10-05 | Nec Electronics Corporation | Overlay mark, method of measuring overlay accuracy, method of making alignment and semiconductor device therewith |
| CN102411259A (en) * | 2011-11-28 | 2012-04-11 | 上海华力微电子有限公司 | Method and device for performing optical proximity correction on photomask design layout |
| CN109085736A (en) * | 2018-09-10 | 2018-12-25 | 德淮半导体有限公司 | The production method of optical adjacent correction method and mask plate |
| CN109814332A (en) * | 2019-03-15 | 2019-05-28 | 云谷（固安）科技有限公司 | A kind of mask plate, preparation method and display panel |
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