CN110445573B

CN110445573B - NB-IoT terminal verification platform and clock synchronization method thereof

Info

Publication number: CN110445573B
Application number: CN201910768398.6A
Authority: CN
Inventors: 梁智斌
Original assignee: Guangzhou Particle Microelectronics Co ltd
Current assignee: Guangzhou Particle Microelectronics Co ltd
Priority date: 2019-08-20
Filing date: 2019-08-20
Publication date: 2020-09-25
Anticipated expiration: 2039-08-20
Also published as: CN110445573A

Abstract

The embodiment of the disclosure provides an NB-IoT terminal verification platform and a clock synchronization method thereof, wherein the method comprises the following steps: detecting the falling edge of a channel associated clock of the SDR radio frequency board by using a high-frequency clock; driving a counter using the high-frequency clock and resetting the counter using a falling edge of the associated clock to obtain an operating clock of the FPGA verification board, wherein a maximum value of the counter is determined by a frequency division ratio of the high-frequency clock to the operating clock; performing time-threshold sampling on a narrowband primary synchronization reference signal of the NB-IoT base station simulation equipment through the SDR radio frequency board to detect the narrowband primary synchronization reference signal and calculate a deviation value of frequency; and configuring a fine tuning value of the DCXO of the SDR radio frequency board according to the deviation value of the frequency so as to correspondingly change the reference clock frequency of the SDR radio frequency board. The method solves the problems that an additional clock driving circuit needs to be added and the use flexibility of the clock source is poor in the related technology.

Description

NB-IoT terminal verification platform and clock synchronization method thereof

Technical Field

The disclosure relates to the technical field of internet of things, in particular to an NB-IoT terminal verification platform and a clock synchronization method thereof.

Background

With the development of wireless technology, the internet of things is an important development direction. The Narrow-Band Internet Of Things (NB-IoT) system has obvious advantages in the application Of the Internet Of Things, and is widely applied to scenes such as intelligent meter reading, accurate farming, industrial automation, intelligent buildings, environment monitoring and the like. The development of NB-IoT terminal chips requires a suite of verification platforms to verify functional coverage of NB-IoT protocols.

However, the clock synchronization method in the prior art is complex, costly and has poor flexibility in system adaptation.

Disclosure of Invention

Therefore, an object of the embodiments of the present disclosure is to provide a solution for clock synchronization applied to an NB-IoT wireless terminal authentication platform, so as to solve the problems in the related art that an additional clock driving circuit needs to be added, and the flexibility of clock source usage is poor.

In a first aspect, a clock synchronization method applied to an NB-IoT terminal verification platform, where the NB-IoT terminal verification platform includes an NB-IoT base station simulation device, an SDR radio frequency board, and an FPGA verification board, includes:

detecting the falling edge of a channel associated clock of the SDR radio frequency board by using a high-frequency clock;

driving a counter using the high-frequency clock and resetting the counter using a falling edge of the associated clock to obtain an operating clock of the FPGA verification board, wherein a maximum value of the counter is determined by a frequency division ratio of the high-frequency clock to the operating clock;

performing time-threshold sampling on a narrowband primary synchronization reference signal of the NB-IoT base station simulation equipment to detect the narrowband primary synchronization reference signal, and calculating a deviation value of frequency; and

and configuring a fine tuning value of the DCXO of the SDR radio frequency board according to the deviation value of the frequency so as to correspondingly change the reference clock frequency of the SDR radio frequency board.

According to a specific implementation manner of the embodiment of the present disclosure, the method further includes:

performing time-threshold sampling on a narrowband primary synchronization reference signal of the NB-IoT base station simulation equipment to detect the narrowband primary synchronization reference signal, and calculating a time deviation value; and

and adjusting the initial position of the sampling data according to the time deviation value.

According to a specific implementation manner of the embodiment of the present disclosure, the detecting a falling edge of a channel associated clock of the SDR radio frequency board by using a high-frequency clock includes:

using a PLL (phase locked loop) built in the FPGA verification board to carry out frequency multiplication operation on a reference clock of the FPGA verification board so as to generate the high-frequency clock;

using the high-frequency clock to perform two-stage register sampling on a channel associated clock of the SDR radio frequency board; and

a falling edge of the sampled signal is detected.

According to a specific implementation manner of the embodiment of the present disclosure, the obtaining of the working clock of the FPGA verification board includes:

and when the frequency of the channel associated clock of the SDR radio frequency board is high enough, using the channel associated clock of the SDR radio frequency board as the working clock of the FPGA verification board.

and generating a working clock of the FPGA verification board according to the required duty ratio.

According to a specific implementation manner of the embodiment of the present disclosure, the time-threshold sampling, by the SDR rf board, a narrowband primary synchronization reference signal of the NB-IoT base station analog device to detect the narrowband primary synchronization reference signal includes:

performing down-conversion and analog-to-digital conversion on a narrowband primary synchronization reference signal of the NB-IoT base station analog device;

performing time domain sampling on the signals subjected to down-conversion and analog-to-digital conversion; and

carrying out correlation operation on the sampling signal and a pre-known ZC sequence;

and when the peak value of the correlation operation reaches a preset threshold value, determining that the narrowband primary synchronization reference signal is detected.

According to a specific implementation manner of the embodiment of the present disclosure, the calculating the time deviation value and the frequency deviation value includes:

and calculating the time deviation value and the frequency deviation value according to the correlation operation result.

According to a specific implementation manner of the embodiment of the disclosure, the narrowband master synchronization reference signal is continuously detected, and when the deviation value of the time and the deviation value of the frequency are smaller than a predetermined threshold, the clock synchronization of the NB-IoT terminal authentication platform is determined.

In a second aspect, an NB-IoT terminal authentication platform includes an NB-IoT base station simulation device, an SDR radio frequency board, and an FPGA authentication board, wherein the NB-IoT terminal authentication platform includes an NB-IoT base station simulation device, an SDR radio frequency board, and an FPGA authentication board

The NB-IoT base station simulation equipment outputs downlink radio frequency signals, and the downlink radio frequency signals output downlink baseband signals to the FPGA verification board through frequency mixing, filtering and digital-to-analog conversion of the SDR radio frequency board;

the SDR radio frequency board comprises a channel associated clock, an SPI interface register and a DCXO, and the FPGA verification board comprises an interface clock synchronization module, a main synchronization detection module, a frequency deviation and time deviation calculation module and an SPI interface module;

the interface clock synchronization module detects a falling edge of a channel associated clock of the SDR radio frequency board by using a high-frequency clock, drives a counter by using the high-frequency clock and resets the counter by using the falling edge of the channel associated clock to obtain a working clock of the FPGA verification board, wherein the maximum value of the counter is determined by the frequency dividing ratio of the high-frequency clock to the working clock;

a main synchronous detection module of the FPGA verification board performs time-threshold sampling on the downlink baseband signal to detect the downlink baseband signal, and a frequency deviation and time deviation calculation module calculates a frequency deviation value; and is

And the SPI interface module configures an SPI interface register of the SDR radio frequency board according to the deviation value of the frequency, and modifies the fine adjustment value of the DCXO so as to correspondingly change the reference clock frequency of the SDR radio frequency board.

According to a specific implementation manner of the embodiment of the disclosure, the downlink baseband signal is continuously detected by the primary synchronization detection module, and when the time deviation value and the frequency deviation value are smaller than a predetermined threshold value, the clock synchronization of the NB-IoT terminal authentication platform is determined.

The clock synchronization method applied to the NB-IoT terminal verification platform in the embodiment of the disclosure comprises the following steps: detecting the falling edge of a channel associated clock of the SDR radio frequency board by using a high-frequency clock; driving a counter using the high-frequency clock and resetting the counter using a falling edge of the associated clock to obtain an operating clock of the FPGA verification board, wherein a maximum value of the counter is determined by a frequency division ratio of the high-frequency clock to the operating clock; performing time-threshold sampling on a narrowband primary synchronization reference signal of the NB-IoT base station simulation equipment through the SDR radio frequency board to detect the narrowband primary synchronization reference signal and calculate a deviation value of frequency; and configuring a fine tuning value of the DCXO of the SDR radio frequency board according to the deviation value of the frequency so as to correspondingly change the reference clock frequency of the SDR radio frequency board. The method solves the problems that an additional clock driving circuit needs to be added and the use flexibility of the clock source is poor in the related technology.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a block diagram applied to an NB-IoT terminal authentication platform provided by an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a prior art clock synchronization method provided by an embodiment of the present disclosure;

fig. 3 is a flowchart of a clock synchronization method provided by an embodiment of the present disclosure;

fig. 4 is a flowchart for synchronizing clocks of the SDR rf board and the FPGA verification board according to the embodiment of the present disclosure; and is

Fig. 5 is an application example of an NB-IoT terminal authentication platform provided by an embodiment of the present disclosure.

Detailed Description

The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

The embodiments of the present disclosure are described below with specific examples, and other advantages and effects of the present disclosure will be readily apparent to those skilled in the art from the disclosure in the specification. It is to be understood that the described embodiments are merely illustrative of some, and not restrictive, of the embodiments of the disclosure. The disclosure may be embodied or carried out in various other specific embodiments, and various modifications and changes may be made in the details within the description without departing from the spirit of the disclosure. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.

It is noted that various aspects of the embodiments are described below within the scope of the appended claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the disclosure, one skilled in the art should appreciate that one aspect described herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number of the aspects set forth herein. Additionally, such an apparatus may be implemented and/or such a method may be practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.

It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present disclosure, and the drawings only show the components related to the present disclosure rather than the number, shape and size of the components in actual implementation, and the type, amount and ratio of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details.

Next, a clock synchronization method applied to an NB-IoT terminal authentication platform of the embodiments of the present disclosure is described with reference to the drawings. First, referring to fig. 1, a framework applied to an NB-IoT terminal authentication platform (hereinafter, abbreviated as NB-IoT terminal authentication platform) is described. As shown in fig. 1, NB-IoT terminal authentication platform 100 mainly includes NB-IoT base station simulation device 101, SDR radio board 102 and FPGA authentication board 103.

In the disclosed embodiments, the letter SDR indicates a software defined radio, FPGA indicates a field programmable gate array, and NB-IoT indicates a narrowband physical network. Further, SDR indicates a software defined radio, DCXO indicates a digitally controlled crystal oscillator, SPI indicates a serial peripheral interface, NB-IoT indicates a narrowband physical network, NPSS indicates a narrowband master sync signal, and ADC indicates an analog-to-digital converter. In the following description, alphabetic abbreviations or corresponding terms are used to indicate the same meaning.

In the NB-IoT terminal authentication platform 100, the NB-IoT base station simulation device 101 simulates processing of digital baseband signals and upper layer protocols on the base station side and transmits radio frequency signals to the SDR radio frequency board 102 or receives radio frequency signals from the SDR radio frequency board 102. The SDR rf board 102 realizes the transmission and reception of the terminal-side rf signal and the conversion of the digital baseband signal. The FPGA authentication board 103 implements processing of a digital baseband signal at the terminal side and processing of an upper layer protocol.

In practical application, a wireless terminal and a base station are connected through a wireless link to upload and download data. To ensure the communication quality, the clocks of the terminal and the base station are synchronized. On the NB-IoT terminal verification platform, clock synchronization of the NB-IoT base station simulation device 101, the SDR radio frequency board 102 and the FPGA verification board 103 needs to be realized.

In order to realize clock synchronization of the NB-IoT base station simulation device 101, the SDR rf board 102 and the FPGA verification board 103, the following two methods are mainly included in the prior art.

The first method is to make the NB-IoT base station simulation device 101 output the same clock source to the SDR rf board 102 and the FPGA verification board 103 to provide a reference clock, thereby ensuring the clock synchronization of the three.

The second method is to let the SDR rf board 102 and the FPGA verification board 103 use the same reference clock source, and use different reference clock sources with the NB-IoT base station simulation device 101. According to the specification of the NB-IoT protocol, NB-IoT base station simulation equipment 101 sends a narrowband master synchronization signal NPSS at each frame of fixed time slot, the sent narrowband master synchronization signal NPSS is processed by an SDR radio frequency board 102 and an FPGA verification board 103 to obtain the frequency deviation between a local reference clock source and a reference clock source of the NB-IoT base station simulation equipment 101, and the local reference clock source is compensated and adjusted to keep consistent with the reference clock source frequency of the NB-IoT base station simulation equipment 101, so that clock synchronization of the NB-IoT base station simulation equipment 101, the NB-IoT base station simulation equipment and the reference clock source is. Fig. 2 shows a schematic diagram of a second clock synchronization method.

As described above, the first method is to make the NB-IoT base station simulation device 101 output the same clock source, provide a reference clock for the SDR rf board 102 and the FPGA verification board 103, and ensure the clocks of the three boards to be synchronized. However, the following disadvantages exist with this approach:

1. since the reference clock input interfaces and levels of the SDR rf board 102 and the FPGA verification board 103 may not be consistent, additional clock driving circuitry is required to provide a reference clock to both, adding cost and complexity.

2. The NB-IoT base station simulation device 101 is required to output the reference clock, which limits the selection of the device model and also reduces the flexibility of system adaptation.

3. Under the condition that the three are completely synchronous, the baseband synchronization algorithm and the performance of the terminal equipment cannot be verified.

The second method is to let the SDR rf board 102 and the FPGA verification board 103 use the same reference clock source, and use different reference clock sources with the NB-IoT base station simulation device 101. The NB-IoT base station simulation equipment 101 sends a narrowband master synchronization signal NPSS, frequency deviation between a local reference clock source and a reference clock source of the NB-IoT base station simulation equipment 101 is obtained through processing of the SDR radio frequency board 102 and the FPGA verification board 103, and the local reference clock source is adjusted through compensation to keep consistent with the reference clock source frequency of the NB-IoT base station simulation equipment. However, this method also has the following disadvantages:

1. if the SDR radio frequency board 101 and the FPGA verification board 103 use the same reference clock source, there is also a possibility that the interfaces and levels of the reference clock inputs of the SDR radio frequency board 101 and the FPGA verification board 103 may be inconsistent, and an additional clock driving circuit needs to be used to provide the reference clock for the two.

2. If a high frequency reference clock is output from the SDR rf board 102 to the FPGA verification board 103, additional clock driving circuitry may also be required, increasing cost and complexity.

The prior art clock synchronization method is described above. Next, a clock synchronization method (hereinafter, simply referred to as a clock synchronization method) applied to an NB-IoT terminal authentication platform according to an embodiment of the present disclosure is described.

In the clock synchronization method of the embodiment of the present disclosure, three component devices (NB-IoT base station simulation device 101, SDR radio frequency board 102 and FPGA verification board 103) of the NB-IoT wireless terminal verification platform 100 adopt three independent clock sources, synchronize a working clock of the FPGA verification board 103 with a clock of the SDR radio frequency board 102 by a PLL (Phase Locked Loop or Phase Locked Loop) high-frequency clock synchronization technology, and synchronize clocks of the SDR radio frequency board 102 and the NB-IoT base station simulation device 101 by processing a narrowband master synchronization signal NPSS, thereby implementing clock synchronization of the entire system.

Next, a clock synchronization method 300 according to an embodiment of the present disclosure is described in detail with reference to fig. 3.

S301: and detecting the falling edge of the associated clock of the SDR radio frequency board by using a high-frequency clock.

The SDR rf board 102 contains a synchronous data interface and the synchronous data interface includes a channel associated clock which outputs a synchronous interface clock Y to the FPGA verification board 103. The frequency value of the interface clock Y is related to the sampling rate of the ADC (analog to digital converter) on the SDR rf board 2.

When the frequency value of the interface clock Y is high, it can be directly used as the working clock of the FPGA verification board 103, thus realizing the clock synchronization between the working clock of the FPGA verification board 103 and the clock of the SDR rf board 102.

Next, a method of synchronizing clocks of the SDR radio frequency board 102 and the FPGA verification board 103 is described with reference to fig. 4. As shown in fig. 4, when the frequency value of the interface clock Y is low (e.g. 3.84MHz in NB-IoT application), it cannot be directly used as the PLL input clock of the FPGA verification board 103 (generally, 20MHz or more is required). In this case, the reference clock (local clock) on the FPGA verification board 103 is set to S0. The FPGA verification board 103 generates a high-frequency clock S1 by frequency multiplication using a PLL built in the FPGA, with S0 as an input. The interface clock Y is two-stage register sampled using the high frequency clock S1 and a falling edge is detected.

S302: an n-bit counter is driven using the high-frequency clock S1 in step S301, and the counter is reset using the falling edge of the interface clock Y.

As shown in fig. 4, the high frequency clock S1 drives the counter to start counting from 0, and the maximum value of the count is determined by the frequency division ratio of the high frequency clock S1 to the operation clock S2 that needs to be obtained. And generates the required operating clock S2 according to the required duty cycle. The falling edge of the interface clock Y is used for resetting the counter, so that the working clock S2 generated by the counter and the interface clock Y are in a synchronous relation, and the clock synchronization of the SDR radio frequency board 102 and the FPGA verification board 103 is ensured.

S303: a narrowband primary synchronization reference signal NPSS is detected. According to the NB-IoT protocol, the base station side transmits a narrowband primary synchronization reference signal NPSS at a fixed location (subframe 5) per radio frame (10 ms). The OFDM symbol occupies 11 subcarriers in the frequency domain and the last 11 OFDM symbols in the time domain, and the formula is defined as:

wherein the mask sequence set corresponding to S (3) ·]。

In the initial search phase, the narrowband master synchronization reference signal NPSS is down-converted by the SDR rf board 102, analog-to-digital converted, and time-domain sampled at a sampling rate of 1.92 MHz.

The obtained sampling signal is correlated with a known ZC (Zadoff-Chu) sequence, and if the peak of the correlation reaches a threshold for detecting the narrowband primary synchronization reference signal NPSS, it is considered that the narrowband primary synchronization reference signal NPSS is detected, and a time offset value time _ offset and a frequency offset value frequency _ offset are obtained according to the calculation result.

S304: according to the calculated time deviation value, the initial position of the sampling data is adjusted, and according to the calculated frequency deviation value, the fine tuning value of the DCXO of the SDR radio frequency board 102 is configured through the SPI interface of the FPGA verification board 103, so that the reference clock frequency of the SDR board 102 is changed accordingly, thus achieving synchronization of the reference clock frequency of the SDR board 102 and the clock signal of the NB-IoT base station analog device 101.

S305: repeating S303 and S304, continuously detecting the narrowband master synchronization reference signal NPSS, and when the time and frequency deviation values are smaller than the expected threshold values, it can be considered that the clocks of the SDR radio frequency board 102, the FPGA verification board 103 and the NB-IoT base station simulation equipment 101 are synchronized.

The clock synchronization method according to the embodiments of the present disclosure has been described above with reference to the accompanying drawings. Next, an application example of an NB-IoT terminal authentication platform according to an embodiment of the present disclosure is described with reference to fig. 5.

NB-IoT base station simulation equipment 101 outputs downlink radio frequency signals, outputs downlink baseband signals to FPGA verification board 103 through frequency mixing, filtering and ADC digital-to-analog conversion of an SDR radio frequency chip, wherein an interface clock is 3.84MHz, a data sampling rate is 1.92Mbps, a high-frequency clock which is multiplied by PLL and is inside the FPGA is 900MHz, and generates a working clock which is close to 50% duty ratio and has a frequency of 30.72MHz through an interface clock synchronization module, and the working clock is synchronous with the interface clock. Inputting baseband signal data of the FPGA, detecting a master synchronization signal through a master synchronization detection module, calculating a frequency deviation value through a frequency deviation and time deviation calculation module when the master synchronization signal is detected, modifying a fine tuning value of a register DCXO of an SDR chip through an SPI interface module, changing the frequency of the DCXO, and completing clock synchronization of NB-IoT base station simulation equipment, an SDR radio frequency board and an FPGA verification board through cyclic iteration.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present disclosure should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A clock synchronization method applied to an NB-IoT terminal verification platform, wherein the NB-IoT terminal verification platform comprises NB-IoT base station simulation equipment, an SDR radio frequency board and an FPGA verification board, and the method comprises the following steps:

the FPGA verification board carries out time threshold sampling on the narrow-band main synchronous reference signal of the NB-IoT base station simulation equipment so as to detect the narrow-band main synchronous reference signal and calculate the deviation value of frequency; and

2. The method of claim 1, applied to a NB-IoT terminal authentication platform for clock synchronization, wherein the method further comprises:

3. The clock synchronization method applied to the NB-IoT terminal authentication platform as claimed in claim 1, wherein the detecting the falling edge of the associated clock of the SDR radio frequency board by using the high frequency clock comprises:

a falling edge of the sampled signal is detected.

4. The clock synchronization method applied to the NB-IoT terminal authentication platform as claimed in claim 1, wherein the obtaining the working clock of the FPGA authentication board comprises:

5. The clock synchronization method applied to the NB-IoT terminal authentication platform as claimed in claim 1, wherein the obtaining the working clock of the FPGA authentication board comprises:

6. The clock synchronization method applied to the NB-IoT terminal authentication platform according to claim 2, wherein the time-threshold sampling of the narrowband primary synchronization reference signal of the NB-IoT base station emulation device for detecting the narrowband primary synchronization reference signal comprises:

7. The clock synchronization method applied to the NB-IoT terminal authentication platform as claimed in claim 6, wherein the calculating the time offset value and the frequency offset value comprises:

8. The method of claim 7, wherein the narrowband master sync reference signal is continuously detected, and the NB-IoT terminal authentication platform clock synchronization is determined when the time offset value and the frequency offset value are less than a predetermined threshold.

9. The NB-IoT terminal verification platform is characterized by comprising NB-IoT base station simulation equipment, an SDR radio frequency board and an FPGA verification board, wherein the NB-IoT terminal verification platform comprises NB-IoT base station simulation equipment, an SDR radio frequency board and an FPGA verification board

10. The NB-IoT terminal authentication platform of claim 9, wherein the downlink baseband signal is continuously detected via the primary synchronization detection module, and wherein the NB-IoT terminal authentication platform is configured to determine clock synchronization when the time offset and the frequency offset are less than predetermined thresholds.