CN110444483A - Integrated circuit reroutes layer preparation method and semiconductor devices - Google Patents
Integrated circuit reroutes layer preparation method and semiconductor devices Download PDFInfo
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- CN110444483A CN110444483A CN201910678275.3A CN201910678275A CN110444483A CN 110444483 A CN110444483 A CN 110444483A CN 201910678275 A CN201910678275 A CN 201910678275A CN 110444483 A CN110444483 A CN 110444483A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02331—Multilayer structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02373—Layout of the redistribution layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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Abstract
The present invention provides a kind of integrated circuits to reroute layer preparation method and semiconductor devices, the described method includes: the active surface by 3D printing method in integrated circuit main body forms the first sublayer, first sublayer includes the first supporter being made of insulating materials and the first signal wire being constructed from a material that be electrically conducting, and the on one or more chips pad of each first signal wire and the active surface of integrated circuit main body is conductively connected.The present invention is laid out the pad locations of integrated circuit by the first sublayer formed by 3D printing method again, enormously simplifies the processing for rerouting layer, while can reduce and turn the increased thickness of foot.
Description
Technical field
The present invention relates to integrated antenna package fields, reroute layer preparation side more specifically to a kind of integrated circuit
Method and semiconductor devices.
Background technique
Modern product is particular about light and short, therefore many separate type circuits are all integrated into integrated circuit.Currently, integrated circuit
It has been widely used in personal computer, mobile phone, digital camera and other electronic equipments.In order to be provided to integrated circuit
One reliable and stable working environment, and mechanical or environmental protection effect is carried out to integrated circuit, so that integrated circuit is sent out
Normal function is waved, and guarantees that it, with high stability and reliability, need to be packaged integrated circuit.Currently, various integrated
It may be used in the encapsulating structure of circuit and reroute layer (Redistribution Layers, RDL), it, can by rerouting layer
The aluminium land positions of integrated circuit are laid out again, new welding zone is made to meet the requirement to solder ball minimum spacing, and are made new
Welding zone is according to array arrangement etc..
Common rewiring layer material is that electro-coppering (plated Cu) is aided with the titanium of bottoming, copper sputtering layer
(Sputtered Ti/Cu).In the prior art, the production of re-wiring layer structure usually requires coating two layers of polymers film.
As shown in Figure 1, it is coated with first layer thin polymer film 13 on the surface for being equipped with the integrated circuit main body 10 of chip bonding pad 12 first, with
The passivation layer for reinforcing integrated circuit main body 10, plays the role of stress buffer；It is then based on the production of first layer thin polymer film 13
Re-wiring layer 14；Then it is coated with second layer thin polymer film 15, make 10 surface planarisation of integrated circuit main body and is protected again
Wiring layer 14, and photoetching process is carried out to second layer thin polymer film 15, output the position of new welding zone；Again in new land positions system
Make Underbump metallization layer 16 (Under Bump Metalization, abbreviation UBM), the system of manufacture craft and re-wiring layer
It is roughly the same to make technique；It finally carries out planting ball on Underbump metallization layer 16 and carries out reflux technique, solder ball 17 melts through reflux
Change forms good infiltration with Underbump metallization layer and is combined.
The manufacturing process of above-mentioned re-wiring layer structure needs to carry out photoetching due to needing to make two layers of polymers film
And production Underbump metallization layer 16, not only complex process, but also increase manufacturing cost.
Summary of the invention
The technical problem to be solved in the present invention is that for said integrated circuit re-wiring layer complex manufacturing technology,
The problem of higher cost, provides a kind of integrated circuit and reroutes layer preparation method and semiconductor devices.
The technical solution that the present invention solves above-mentioned technical problem is to provide a kind of integrated circuit rewiring layer preparation method,
Include:
By 3D printing method integrated circuit main body active surface formed the first sublayer, first sublayer include by
The first supporter that insulating materials is constituted and at least one the first signal wires being constructed from a material that be electrically conducting, and each described first
The on one or more chips pad of signal wire and the active surface of integrated circuit main body is conductively connected.
Preferably, the method also includes: third sublayer is formed in first sublayer by 3D printing method, it is described
Third sublayer includes the third supporter being made of insulating materials and the external pads of one or more being constructed from a material that be electrically conducting,
Each external pad and first signal wire are conductively connected, each external pad by first signal wire with
One or more chip bonding pads are conductively connected.
Preferably, the method also includes: formed in first sublayer by 3D printing method it is one or more according to
Secondary the second sublayer being stacked, each second sublayer include the second supporter being made of insulating materials and by conductive material
At least one second signal line constituted, and each second signal line and the first signal wire of the first adjacent sublayer are conductive
Connection is conductively connected with the second signal line of the second adjacent sublayer.
Preferably, the method also includes: by 3D printing method be located at top the second sublayer on formed third son
Layer, the third sublayer include that the third supporter being made of insulating materials and the one or more being constructed from a material that be electrically conducting are outer
Pad is connect, each external pad and a second signal line are conductively connected, and each external pad passes through described first
Signal wire, second signal line and one or more chip bonding pads are conductively connected.
Preferably, the upper surface of the third supporter is protruded from the top of the external pad, and multiple described external
The part that pad protrudes from the upper surface of the third supporter is distributed in array or in wire frame shape.
Preferably, the insulating materials is insulation UV glue, and the conductive material is the conductive UV glue mixed with metal powder；Institute
State the first sublayer, third sublayer and each second sublayer pass through respectively repeatedly layering printing and ultraviolet light be sintered to be formed.
Preferably, in first sublayer and each second sublayer, at least the one of each second signal line
Part is staggeredly located with the first signal wire of conductive connection or at least part of of second signal line.
Preferably, first sublayer, each second sublayer and the integrated circuit main body active surface have
Identical shape and size.
Preferably, the height of first sublayer and each second sublayer is equal；In first sublayer, institute
State the first supporter and the first signal wire height having the same；In each second sublayer, second support
Body and the second signal line height having the same.
The present invention also provides a kind of semiconductor devices, including what is be prepared by described in any item preparation methods as above
First sublayer.
Integrated circuit of the invention reroutes layer preparation method and semiconductor devices, by formed by 3D printing method the
One sublayer is laid out the pad locations of integrated circuit again, enormously simplifies the processing technology for rerouting layer.Also, this hair
It is bright to carry out reinforcement structure intensity without additional glass fiber material, it greatly reduces and turns the increased thickness of foot.
Detailed description of the invention
Fig. 1 is the structural schematic diagram that existing integrated circuit reroutes layer；
Fig. 2 is the schematic diagram of the section structure of semiconductor devices provided in an embodiment of the present invention；
Fig. 3 is the structural schematic diagram of semiconductor devices provided in an embodiment of the present invention.
Specific embodiment
Following discloses provide many different embodiments or example of the different characteristic for implementing provided theme.With
The lower specific example for illustrating component, value, operation, material, arrangement etc. is to simplify the embodiment of the present invention.Certainly, these are only example
Without being intended for limiting.It is expected that there are other assemblies, value, operation, material, arrangements etc..For example, by the first spy in following explanation
Sign is formed in second feature " top " or second feature "upper" may include that wherein fisrt feature and second feature are formed directly
The embodiment of contact, and may also comprise can be wherein formed between fisrt feature and second feature supplementary features, so that
The embodiment that the fisrt feature and the second feature may be not directly contacted with.In addition, the embodiment of the present invention may be various
Ref. No. and/or letter are reused in example.This reuse be for succinct and clearly purpose, rather than itself
Indicate the relationship between discussed various embodiments and/or configuration.
In addition, be ease of explanation, may use herein for example " ... lower section (beneath) ", " below (below) ",
The spaces relativity term such as " (lower) of lower part ", " top (above) ", " (upper) on top " is shown in figure to illustrate
The relationship of one elements or features and another (other) elements or features.The space relativity term is intended to except depicted in figure
Orientation outside also include the different orientation of device in use or operation.Equipment can have other orientation (be rotated by 90 ° or other
Orientation), and space relativity used herein describes language and equally can correspondingly explain.
In addition, being ease of explanation, the usable such as terms such as " first ", " second " are shown in the drawings to illustrate herein
Similar or different elements or features, and these terms can be used interchangeably according to existing order or the context of explanation.
In conjunction with Fig. 2, integrated circuit provided in an embodiment of the present invention reroutes layer preparation method, in integrated circuit main body
Preparation reroutes layer on 20, which is used to carry out again the position of the chip bonding pad 201 in integrated circuit main body 20
Layout, and the rewiring layer preparation method cannot be only used for the encapsulation of single chip, can also be applied to wafer-level packaging (Wafer
Level Packaging, WLP), i.e., it after the completion of full wafer wafer production, is directly packaged on wafer, just cutting is made later
At single chip.Said integrated circuit main body 20 may include integrated circuit bare crystalline (die) and passivation layer, above-mentioned passivation layer covering
The active surface of bare crystalline, and passivation layer include it is one or more respectively with one or more metal gaskets of the active surface of bare crystalline
(pad) conductive column being conductively connected, the chip bonding pad 201 of integrated circuit main body 20 are exposed to the portion of passivation layer by above-mentioned conductive column
Divide and constitutes.Certainly, in practical applications, the active surface of integrated circuit main body 20 can also not have passivation layer, i.e. chip bonding pad
201 can be directly made of the metal gasket in integrated circuit bare crystalline.
The integrated circuit of the present embodiment reroutes layer preparation method and completes by 3D printing equipment, which includes
At least one nozzle group, and each nozzle group include at least two spray heads, two spray heads can phase same point blasting materials, and its
In a sprayable insulating materials of spray head, the sprayable conductive material of another spray head.Pass through the movement of control nozzle group and two
Insulating materials and conductive material are ejected into printing surface by the injection of spray head.The precision of above-mentioned 3D printing equipment reaches as high as
2880DPI (Dots Per Inch, dots per inch) can also select the 3D printing equipment of different accuracy certainly as needed.
The method of the present embodiment the following steps are included:
S1: by 3D printing method integrated circuit main body 20 the active surface surface of chip bonding pad 201 (i.e. with)
The first sublayer is formed, i.e. the lower surface of the first sublayer and the active surface of integrated circuit main body 20 is affixed.First sublayer includes
The first supporter 211 being made of insulating materials and at least one the first signal wires 212 being constructed from a material that be electrically conducting, and it is each
The on one or more chips pad 201 of first signal wire 212 and the active surface of integrated circuit main body 20 is conductively connected.
In general, in the first sublayer, the quantity of the first signal wire 212 can greater than, equal to or be less than integrated circuit main body 20
Active surface chip bonding pad 201 quantity.Above-mentioned first signal wire 212 can be used for transmitting signal, also may be implemented to shield
(such as reducing inter-signal interference), and the first supporter 211 can be realized and is dielectrically separated between the first signal wire 212.In
In concrete application, the segment chip pad 201 in integrated circuit main body 20 can not be connect with any first signal wire 212, can also
Multiple chip bonding pads 201 are connected to same first signal wire 212 simultaneously, specifically can be determine according to actual needs.
S2: forming one or more the second sublayers being successively stacked by 3D printing method in the first sublayer, and every 1 the
Two sublayers include the second supporter 221 being made of insulating materials and at least one second signal line being constructed from a material that be electrically conducting
222, and the first signal wire 212 of each second signal line 222 and the first adjacent sublayer is conductively connected or with adjacent second
The second signal line 222 of sublayer is conductively connected.
In every one second sublayer, the quantity of second signal line 222 is equal to the number of the first signal wire 212 in the first sublayer
Amount.Above-mentioned second signal line 222 can be used for transmitting signal, also may be implemented to shield, and each item in every one second sublayer
Pass through 221 mutually insulated of the second supporter between second signal line 222.Certainly, in practical applications, second signal line 222
Quantity be also greater than or less than the first signal wire 212 in the first sublayer quantity.
In practical applications, to improve 3D printing efficiency, it is used to prepare the 3D printing equipment of the first sublayer and the second sublayer
It may include the multiple of arrangement (length of the row is matched with the length or width of the active surface of integrated circuit main body 20) in a row
Nozzle group a, so that print line can be formed in primary injection.Alternatively, 3D printing equipment includes being arranged in rectangular array (to be somebody's turn to do
The shape and size of rectangular array are matched with the shape and size of the active surface of integrated circuit main body 20) multiple nozzle groups,
To which a printable layer can be formed when once spraying.
Said integrated circuit reroutes layer preparation method, passes through the first sublayer and the second sublayer formed by 3D printing method
Composition reroutes layer, can be laid out again to 201 position of chip bonding pad in integrated circuit main body 20, and weight cloth is enormously simplified
The processing technology of line layer.It, can be directly using the active surface of integrated circuit main body 20 as branch also, when preparation reroutes layer
Support turns foot increase to greatly reduce without increasing additional glass fiber material reinforcement structure intensity in integrated circuit main body 20
Thickness.
In another embodiment of the invention, it is above-mentioned in addition to including the steps that reroute layer preparation method for said integrated circuit
Outside S1, S2, it may also include that
S3: by 3D printing method be located at top the second sublayer on formed third sublayer, the third sublayer include by
The third supporter 231 that insulating materials is constituted and the external pad 232 of one or more being constructed from a material that be electrically conducting, it is each external
Pad 232 and a second signal line 222 are conductively connected, and each external pad 232 passes through the first signal wire 212, second signal
Line 222 and on one or more chips pad 201 are conductively connected.
Above-mentioned external pad 232 can be in the spherical shape of protrusion, i.e., the top of external pad 232 protrudes from third supporter
231 upper surface, and multiple external pad 232 protrudes from the part of the upper surface of third supporter 231 in array or in line
The distribution of frame shape, is connect with facilitating with other component.Certainly, external pad 232 can also be held with the upper surface of third supporter 231
It is flat, it can specifically be determined according to its use occasion.
Specifically, as shown in connection with fig. 3, said integrated circuit reroute layer preparation method can will be in integrated circuit main body 20
Multiple chip bonding pads 201 are converted to multiple external pads 232 for protruding from third supporter 231.For example, can be by integrated circuit master
Nine chip bonding pads 201 on body 20 are converted to six external pads 232 by 3 × 2 array distributions, can also be by integrated circuit master
Four chip bonding pads 201 on body 20 are converted to nine external pads etc. in 3 × 3 array distributions.
In addition, in practical applications, above-mentioned third sublayer can also process to be formed by other means, such as it is being in top layer
The second sublayer upper surface coated polymeric film, and to thin polymer film carry out photoetching process, output the position of external welding zone
It sets；Underbump metallization layer is made in external land positions again；It finally carries out planting ball on Underbump metallization layer and carries out reflux work
Skill makes solder ball (i.e. external pad) form good infiltration with Underbump metallization layer through reflux thawing and is combined.But the program is aobvious
So increase process complexity.
Certainly, in practical applications, rerouting layer can also be only made of the first sublayer, the first signal wire of the first sublayer
212 can directly be conductively connected with other component.In addition, third sublayer directly can also be formed in the upper surface of the first sublayer.
In another embodiment of the invention, in above-mentioned first sublayer and every one second sublayer, each second signal line
222 at least part and the first signal wire 212 of conductive connection or at least part of position phase of second signal line 222
It is wrong.First signal wire 212 and a second signal line 222 that are mutually conductively connected i.e. in adjacent layer or two second
Signal wire 222 is not overlapped in the orthographic projection of the active surface of integrated circuit main body 20, to be misplaced by this interlayer, will be collected
At the position transfer of the chip bonding pad 201 in circuit main body 20 to predetermined position, the layout again of pad is realized.
The above-mentioned insulating materials to form the first supporter 211, the second supporter 221 and third supporter 231 has
Body can be insulation UV glue, and be used to form the conduction material of the first signal wire 212, second signal line 222 and external pad 232
Material is then the conductive UV glue mixed with metal powder (such as silver powder)；Above-mentioned insulation UV glue and conduction UV glue can all be irradiated in ultraviolet light
Lower solidification rapidly.Also, the first sublayer, every one second sublayer, third sublayer pass through repeatedly layering printing and ultraviolet light respectively and burn
Knot is formed, i.e., simultaneously non-once prints to be formed above-mentioned each sublayer, but is stacked by multiple printable layers, and every completion one
Printable layer need to use ultraviolet radiator to be sintered printable layer, solidify printable layer, deformation is avoided to influence performance.Above-mentioned composition
Each printable layer pattern having the same (such as the distribution of signal wire is identical) in each sublayer.
Certainly, in practical applications, to form the first supporter 211, the second supporter 221 and third supporter
231 insulating materials is used to form the conductive material of the first signal wire 212, second signal line 222 and external pad 232
It can be made of other light-sensitive materials.
Particularly, the active table of above-mentioned first sublayer, every one second sublayer and third sublayer and integrated circuit main body 20
Face has the same shape and dimensions, i.e. the first sublayer, the edge of the second sublayer and third sublayer and integrated circuit main body 20
Neighboring maintain an equal level, so that volume will not be increased.
In one embodiment of the invention, in the first sublayer, the first supporter 211 has with the first signal wire 212
Identical height；Similarly, in every one second sublayer, the second supporter 221 has identical height with second signal line 222.
Also, the height of above-mentioned first sublayer and every one second sublayer is equal, specifically, the first sublayer and every one second sublayer
Height is 30-100 microns.
The present invention also provides a kind of semiconductor devices, which includes by described in any item preparation sides as above
First sublayer made of method preparation and one or more second sublayers.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto,
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by anyone skilled in the art,
It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with scope of protection of the claims
Subject to.
Claims (10)
1. a kind of integrated circuit reroutes layer preparation method characterized by comprising
Active surface by 3D printing method in integrated circuit main body forms the first sublayer, and first sublayer includes by insulating
The first supporter that material is constituted and at least one the first signal wires being constructed from a material that be electrically conducting, and each first signal
The on one or more chips pad of line and the active surface of integrated circuit main body is conductively connected.
2. integrated circuit according to claim 1 reroutes layer preparation method, which is characterized in that the method also includes:
Third sublayer is formed in first sublayer by 3D printing method, the third sublayer includes be made of insulating materials
Three supporters and the external pad of one or more being constructed from a material that be electrically conducting, each external pad and first signal
Line is conductively connected, and each external pad is connected by first signal wire and one or more chip bonding pad conductions
It connects.
3. integrated circuit according to claim 1 reroutes layer preparation method, which is characterized in that the method also includes:
One or more the second sublayers being successively stacked, each second son are formed in first sublayer by 3D printing method
Layer includes the second supporter being made of insulating materials and at least one second signal line being constructed from a material that be electrically conducting, and each
The second signal line and the first signal wire of the first adjacent sublayer are conductively connected or the second letter with the second adjacent sublayer
Number line is conductively connected.
4. integrated circuit according to claim 3 reroutes layer preparation method, which is characterized in that the method also includes:
Third sublayer is formed in the second sublayer for being located at top by 3D printing method, the third sublayer includes by insulating materials structure
At third supporter and the external pads of one or more that are constructed from a material that be electrically conducting, each external pad and one article the
Binary signal line is conductively connected, and each external pad passes through first signal wire, second signal line and one or more institutes
State chip bonding pad conductive connection.
5. integrated circuit according to claim 2 or 4 reroutes layer preparation method, which is characterized in that the external pad
Top protrude from the upper surface of the third supporter, and multiple external pads protrude from the upper of the third supporter
The part on surface is distributed in array or in wire frame shape.
6. integrated circuit according to claim 4 reroutes layer preparation method, which is characterized in that the insulating materials is exhausted
Edge UV glue, the conductive material are the conductive UV glue mixed with metal powder；First sublayer, third sublayer and each described
Second sublayer passes through repeatedly layering printing and ultraviolet light respectively and is sintered to be formed.
7. integrated circuit according to claim 4 reroutes layer preparation method, which is characterized in that first sublayer and
In each second sublayer, at least part of each second signal line and the first signal wire of conductive connection or second
At least part of of signal wire is staggeredly located.
8. integrated circuit according to claim 3 reroutes layer preparation method, which is characterized in that first sublayer, every
The active surface of one second sublayer and the integrated circuit main body has the same shape and dimensions.
9. integrated circuit according to claim 6 reroutes layer preparation method, which is characterized in that first sublayer and
The height of each second sublayer is equal；In first sublayer, first supporter and first signal wire have
There is identical height；In each second sublayer, second supporter and the second signal line height having the same
Degree.
10. a kind of semiconductor devices, which is characterized in that including passing through preparation method as claimed in any one of claims 1-9 wherein
The first sublayer being prepared.
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| CN201910678275.3A CN110444483A (en) | 2019-07-25 | 2019-07-25 | Integrated circuit reroutes layer preparation method and semiconductor devices |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113593774A (en) * | 2021-07-30 | 2021-11-02 | 长春捷翼汽车零部件有限公司 | Method for manufacturing wire harness and wire harness |
| CN114446838A (en) * | 2022-03-03 | 2022-05-06 | 芯体素(杭州)科技发展有限公司 | Ball mounting method and device based on 3D printing process, electronic equipment and storage medium |
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| CN114446838A (en) * | 2022-03-03 | 2022-05-06 | 芯体素(杭州)科技发展有限公司 | Ball mounting method and device based on 3D printing process, electronic equipment and storage medium |
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Application publication date: 20191112 |