CN110442365A - The upgrade method and device of programmable logic device - Google Patents
The upgrade method and device of programmable logic device Download PDFInfo
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- CN110442365A CN110442365A CN201910684015.7A CN201910684015A CN110442365A CN 110442365 A CN110442365 A CN 110442365A CN 201910684015 A CN201910684015 A CN 201910684015A CN 110442365 A CN110442365 A CN 110442365A
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Abstract
The invention discloses a kind of upgrade method of programmable logic device and devices, this method comprises: after the latch instruction that the CPU for receiving programmable logic device connection is sent, the current signal state for the selected port connecting in programmable logic device with selected device is latched, latch instruction is that CPU detects the upgrading configuration of programmable logic device, upgrading configuration is stored in the caching of programmable logic device connection and issued after detecting programmable logic device support latch function；After receiving the upgrade command that CPU is sent, upgrading configuration is obtained from caching, upgrade command is sent after CPU sends latch instruction；After loading upgrading configuration file, load is sent to CPU and completes notice, so that CPU sends unlock instruction；After receiving unlock instruction, the current signal state based on selected port runs upgrading configuration.The program can avoid the service disconnection that selected device is carrying out.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a method and an apparatus for upgrading a programmable logic device.
Background
Internet Data Centers (IDCs) are rapidly developed along with the continuous development of Internet technologies, and become an important link in the Internet industry, providing large-scale, high-quality, continuous, safe and reliable professional server hosting, space renting, network wholesale bandwidth and other services for network content providers (ICP), enterprises, media and various websites. Because the IDC has high requirements on the continuity and stability of data transmission, network equipment in the IDC is required to work strictly and uninterruptedly even in the upgrading process, and seamless upgrading is achieved.
The structure of the network device in the IDC is shown in fig. 1, and mainly includes a Central Processing Unit (CPU), a programmable logic device, a cache, a photoelectric forwarding device, and a switching chip, where the CPU is connected to an Inter-Integrated Circuit (I2C) port of the photoelectric conversion device for data communication, and manages the switching chip and the programmable logic device; the exchange chip is in data communication with the photoelectric conversion device; the programmable logic device is a novel high-performance programmable chip with high integration level, the internal circuit function of the programmable logic device is programmable, extremely complex circuit functions can be flexibly realized in the programmable logic device through a Hardware Description Language (HDL) and a special design tool, the programmable logic device is suitable for the field of high-speed and high-density high-end digital logic circuit design, and the programmable logic device realizes control logics such as enabling, resetting, power-on and power-off control and the like of a photoelectric conversion device through high-level signals during operation; the photoelectric conversion device is a photoelectronic device for performing photoelectric and electro-optical conversion, and is widely used in network equipment such as switches, routers and the like; the cache may store the program for the programmable logic device as a default program for the programmable logic device to execute after each power-up of the device.
Many devices in the network device need to be upgraded, and the method for upgrading the programmable logic device is described as follows: after detecting the upgrade configuration file of the programmable logic device, the CPU stores the upgrade configuration file in a cache connected with the programmable logic device and sends an upgrade instruction to the programmable logic device; the programmable logic device receives the upgrading instruction, acquires an upgrading configuration file from a cache, loads the upgrading configuration file, updates the current signal state of a port connected with the photoelectric conversion device in the programmable logic device to be a default signal state, updates the default signal state of the port in the programmable logic device to be the default state stored in the upgrading configuration file after the upgrading configuration file is loaded, and then operates the upgrading configuration file. In the process of upgrading the programmable logic device, the method needs to change the signal state of the port of the programmable logic device for multiple times, which causes the interruption of the service being executed by the photoelectric conversion device, thereby causing the interruption of the service of the network equipment, failing to realize the seamless upgrading of the programmable logic device and further failing to realize the seamless upgrading of the network equipment.
Disclosure of Invention
The embodiment of the invention provides an upgrading method and device of a programmable logic device, which are used for solving the problems that seamless upgrading of the programmable logic device cannot be realized and further seamless upgrading of network equipment cannot be realized in the prior art.
According to an embodiment of the present invention, there is provided a method for upgrading a programmable logic device, which is applied to the programmable logic device, the method including:
after receiving a latch instruction sent by a CPU (central processing unit) connected with the programmable logic device, latching the current signal state of a selected port connected with the selected device in the programmable logic device, wherein the latch instruction is sent after the CPU detects an upgrade configuration file of the programmable logic device, stores the upgrade configuration file in a cache connected with the programmable logic device and detects that the programmable logic device supports a latch function;
after an upgrading instruction sent by the CPU is received, the upgrading configuration file is obtained from the cache, and the upgrading instruction is sent after the CPU sends the latching instruction;
after the upgrade configuration file is loaded, sending a loading completion notice to the CPU so that the CPU sends an unlocking instruction;
and after receiving the unlocking instruction, unlocking the current signal state of the selected port, and operating the upgrading configuration file based on the current signal state of the selected port.
Specifically, the running the upgrade configuration file based on the current signal state of the selected port specifically includes:
reading the current signal state of the selected port;
and after the default signal state of the selected port in the upgrading configuration file is replaced by the current signal state of the selected port, operating the upgrading configuration file.
According to an embodiment of the present invention, there is also provided a method for upgrading a programmable logic device, which is applied to a CPU connected to the programmable logic device, the method including:
after detecting the upgrade configuration file of the programmable logic device, storing the upgrade configuration file in a cache connected with the programmable logic device;
detecting whether the programmable logic device supports a latch function;
if the programmable logic device is detected to support the latching function, a latching instruction is sent to the programmable logic device, so that the programmable logic device latches the current signal state of a selected port connected with a selected device in the programmable logic device after receiving the latching instruction;
sending an upgrade instruction to the programmable logic device, so that the programmable logic device obtains the upgrade configuration file from the cache after receiving the upgrade instruction, loads the upgrade configuration file, and sends a loading completion notification to the CPU;
and after receiving the loading completion notice, sending an unlocking instruction to the programmable logic device, so that the programmable logic device unlocks the current signal state of the selected port after receiving the unlocking instruction, and operating the upgrade configuration file based on the current signal state of the selected port.
Specifically, detecting the upgrade configuration file of the programmable logic device specifically includes:
detecting an upgrade configuration file of the programmable logic device stored by a user; or,
and detecting prompt information of the upgrade configuration file of the programmable logic device provided by a third party.
Specifically, detecting whether the programmable logic device supports a latch function specifically includes:
acquiring attribute information of the programmable logic device;
determining from the attribute information of the programmable logic device whether the programmable logic device supports a latching function.
According to an embodiment of the present invention, there is also provided an upgrade apparatus for a programmable logic device, which is applied to the programmable logic device, the apparatus including:
the latch module is used for latching the current signal state of a selected port connected with a selected device in the programmable logic device after receiving a latch instruction sent by a Central Processing Unit (CPU) connected with the programmable logic device, wherein the latch instruction is sent after the CPU detects an upgrade configuration file of the programmable logic device, stores the upgrade configuration file in a cache connected with the programmable logic device and detects that the programmable logic device supports a latch function;
the obtaining module is used for obtaining the upgrading configuration file from the cache after receiving an upgrading instruction sent by the CPU, wherein the upgrading instruction is sent after the CPU sends the latching instruction;
the loading module is used for sending a loading completion notice to the CPU after the upgrading configuration file is loaded so as to enable the CPU to send an unlocking instruction;
and the unlocking module is used for unlocking and latching the current signal state of the selected port after receiving the unlocking instruction, and operating the upgrading configuration file based on the current signal state of the selected port.
Specifically, the unlocking module is configured to run the upgrade configuration file based on the current signal state of the selected port, and specifically configured to:
reading the current signal state of the selected port;
and after the default signal state of the selected port in the upgrading configuration file is replaced by the current signal state of the selected port, operating the upgrading configuration file.
According to an embodiment of the present invention, there is also provided an upgrade apparatus for a programmable logic device, which is applied to a CPU connected to the programmable logic device, the apparatus including:
the storage module is used for storing the upgrading configuration file in a cache connected with the programmable logic device after detecting the upgrading configuration file of the programmable logic device;
the detection module is used for detecting whether the programmable logic device supports a latch function or not;
the first sending module is used for sending a latch instruction to the programmable logic device if the programmable logic device is detected to support the latch function, so that the programmable logic device latches the current signal state of a selected port connected with a selected device in the programmable logic device after receiving the latch instruction;
a second sending module, configured to send an upgrade instruction to the programmable logic device, so that after the programmable logic device receives the upgrade instruction, the programmable logic device obtains the upgrade configuration file from the cache, loads the upgrade configuration file, and sends a load completion notification to the CPU;
and the transceiver module is used for sending an unlocking instruction to the programmable logic device after receiving the loading completion notification, so that the programmable logic device unlocks the current signal state of the selected port after receiving the unlocking instruction, and runs the upgrade configuration file based on the current signal state of the selected port.
Specifically, the saving module is configured to detect an upgrade configuration file of the programmable logic device, and specifically configured to:
detecting an upgrade configuration file of the programmable logic device stored by a user; or,
and detecting prompt information of the upgrade configuration file of the programmable logic device provided by a third party.
Specifically, the detection module is configured to detect whether the programmable logic device supports a latch function, and specifically configured to:
acquiring attribute information of the programmable logic device;
determining from the attribute information of the programmable logic device whether the programmable logic device supports a latching function.
The invention has the following beneficial effects:
the embodiment of the invention provides an upgrading method and a device of a programmable logic device, which are characterized in that after a latch instruction sent by a CPU (central processing unit) connected with the programmable logic device is received, the current signal state of a selected port connected with the selected device in the programmable logic device is latched, wherein the latch instruction is sent after the CPU detects an upgrading configuration file of the programmable logic device, stores the upgrading configuration file in a cache connected with the programmable logic device and detects that the programmable logic device supports a latch function; after an upgrading instruction sent by the CPU is received, the upgrading configuration file is obtained from the cache, and the upgrading instruction is sent after the CPU sends the latching instruction; after the upgrade configuration file is loaded, sending a loading completion notice to the CPU so that the CPU sends an unlocking instruction; and after the unlocking instruction is received, operating the upgrading configuration file based on the current signal state of the selected port. The scheme can not change the signal state of the selected port for many times in the upgrading process of the programmable logic device, and can keep the current signal state of the selected port all the time, thereby avoiding the interruption of the service being executed by the selected device, avoiding the service interruption of the network equipment, realizing the seamless upgrading of the programmable logic device and further ensuring the realization of the seamless upgrading of the network equipment.
Drawings
Fig. 1 is a schematic structural diagram of a network device in the prior art;
fig. 2 is a flowchart of an upgrade method for a programmable logic device with a programmable logic device as an execution subject according to an embodiment of the present invention;
FIG. 3 is a flowchart of a method for upgrading a programmable logic device with a CPU as an execution subject according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an upgrading apparatus of a programmable logic device corresponding to fig. 2 in an embodiment of the present invention;
fig. 5 is a schematic structural diagram of an upgrading apparatus of a programmable logic device corresponding to fig. 3 in an embodiment of the present invention.
Detailed Description
Aiming at the problem that seamless upgrade of a programmable logic device cannot be realized and further seamless upgrade of network equipment cannot be realized in the prior art, the embodiment of the invention provides an upgrade method of a programmable logic device, which is applied to the network equipment shown in fig. 1, and the upgrade method of the programmable logic device is introduced below by taking a programmable logic device and a CPU as execution main bodies respectively.
Firstly, a method for upgrading a programmable logic device with the programmable logic device as an execution main body is introduced, and the flow of the method is shown in fig. 2, and the execution steps are as follows:
s21: after receiving a latch instruction sent by a CPU connected with the programmable logic device, latching the current signal state of a selected port connected with the selected device in the programmable logic device, wherein the latch instruction is sent after the CPU detects an upgrade configuration file of the programmable logic device, stores the upgrade configuration file in a cache connected with the programmable logic device and detects that the programmable logic device supports a latch function.
The Programmable Logic Device may be, but not limited to, a Field-Programmable Gate Array (FPGA), a Complex Programmable Logic Device (CPLD), and the like, and a port of the Programmable Logic Device connected to a selected Device may be defined as a selected port; the selected device may be, but is not limited to, a photoelectric conversion device, which is described below as an example; the latch command may be, but is not limited to, setting a control signal of the hold _ output port to a high level.
When the programmable logic device operates, the control logics of enabling, resetting, power-on and power-off control and the like of the photoelectric conversion device are realized, and control signals are input to corresponding ports of the photoelectric conversion device at high and low levels. After the CPU detects the upgrade configuration file of the programmable logic device and stores the upgrade configuration file in a cache connected with the programmable logic device, the CPU does not immediately send an upgrade instruction, but firstly sends a latch instruction after detecting that the programmable logic device supports a latch function, and the programmable logic device can latch the current signal state of a selected port connected with the selected device in the programmable logic device after receiving the latch instruction, namely, the current signal state of control signals of enabling, resetting, power-on and power-off control and the like output to the photoelectric conversion device by the programmable logic device is locked.
S22: and after receiving an upgrading instruction sent by the CPU, acquiring an upgrading configuration file from a cache, wherein the upgrading instruction is sent after the CPU sends a latching instruction.
The CPU sends the upgrade instruction after sending the latch instruction, and a current configuration file stored in a Static Random-Access Memory (SRAM) in the programmable logic device is lost after power failure, so that the upgrade configuration file is obtained from a cache and stored in the SRAM during upgrading.
The upgrade instruction may be issued through, but not limited to, a Joint Test Action Group (JTAG) interface.
S23: and after the upgrade configuration file is loaded, sending a loading completion notice to the CPU so that the CPU sends an unlocking instruction.
The upgrade configuration file can be loaded from the SRAM when being loaded, and the CPU is informed after the loading is completed, so that the CPU sends an unlocking instruction to release the current signal state of the selected port latched before.
The unlocking command may be, but is not limited to, setting a control signal of the hold _ output port to a low level.
S24: and after receiving the unlocking instruction, unlocking and locking the current signal state of the selected port, and operating the upgrading configuration file based on the current signal state of the selected port.
After the current signal state of the selected port is latched, the current signal state of the selected port cannot be changed by any instruction, and the upgrade configuration file is continuously operated after upgrading, so that the current signal state of the selected port is firstly released from latching before a new configuration file works, and the upgrade configuration file is operated by taking the current signal state as the initial state of the selected port, thereby completing the upgrade process of the programmable logic device.
The scheme can not change the signal state of the selected port for many times in the upgrading process of the programmable logic device, and can keep the current signal state of the selected port all the time, thereby avoiding the interruption of the service being executed by the selected device, avoiding the service interruption of the network equipment, realizing the seamless upgrading of the programmable logic device and further ensuring the realization of the seamless upgrading of the network equipment.
Specifically, the running of the upgrade configuration file based on the current signal state of the selected port in S24 specifically includes:
reading the current signal state of the selected port;
and after the default signal state of the selected port in the upgrading configuration file is replaced by the current signal state of the selected port, the upgrading configuration file is operated.
The current signal state of the selected port is latched before, the current signal state of the selected port can be used as the initial state for running the upgrade configuration file after the latch is released, and the signal state of the selected port in the upgrade configuration file can be defined as the default signal state.
The upgrading method of the programmable logic device taking the programmable logic device as the execution subject is introduced above, and the upgrading method of the programmable logic device taking the CPU as the execution subject is introduced below; the flow of the method, as shown in fig. 3, is executed as follows:
s31: and after detecting the upgrade configuration file of the programmable logic device, storing the upgrade configuration file in a cache connected with the programmable logic device.
S32: it is detected whether the programmable logic device supports a latching function.
S33: and if the programmable logic device is detected to support the latch function, sending a latch instruction to the programmable logic device so that the programmable logic device latches the current signal state of a selected port connected with the selected device in the programmable logic device after receiving the latch instruction.
S34: and sending an upgrading instruction to the programmable logic device so that the programmable logic device acquires an upgrading configuration file from the cache after receiving the upgrading instruction, loads the upgrading configuration file and sends a loading completion notice to the CPU.
S35: and after receiving the loading completion notice, sending an unlocking instruction to the programmable logic device, so that the programmable logic device unlocks the current signal state of the selected port after receiving the unlocking instruction, and running the upgrade configuration file based on the current signal state of the selected port.
The scheme can not change the signal state of the selected port for many times in the upgrading process of the programmable logic device, and can keep the current signal state of the selected port all the time, thereby avoiding the interruption of the service being executed by the selected device, avoiding the service interruption of the network equipment, realizing the seamless upgrading of the programmable logic device and further ensuring the realization of the seamless upgrading of the network equipment.
Specifically, the step of detecting the upgrade configuration file of the programmable logic device in S31 includes:
detecting an upgrade configuration file of a programmable logic device stored by a user; or,
and detecting prompt information of the upgrade configuration file of the programmable logic device provided by a third party.
Two ways of detecting the upgrade configuration file of the programmable logic device are listed above, but there are many other ways that can be detected, and they are not described one by one here.
Specifically, the detecting whether the programmable logic device supports the latch function in S32 specifically includes:
acquiring attribute information of a programmable logic device;
whether the programmable logic device supports the latch function is determined from the attribute information of the programmable logic device.
In general, attribute information of all devices is stored in the network device, so that the CPU can acquire the attribute information of the programmable logic device and then determine whether the programmable logic device supports the latch function based on the attribute information.
Based on the same inventive concept, an upgrade apparatus for a programmable logic device according to an embodiment of the present invention is applied to a CPU connected to the programmable logic device, as compared with the method shown in fig. 2, and the structure of the upgrade apparatus is shown in fig. 4, and includes:
the latch module 41 is configured to latch a current signal state of a selected port in the programmable logic device, which is connected to a selected device, after receiving a latch instruction sent by a CPU connected to the programmable logic device, where the latch instruction is sent after the CPU detects an upgrade configuration file of the programmable logic device, stores the upgrade configuration file in a cache connected to the programmable logic device, and detects that the programmable logic device supports a latch function;
the obtaining module 42 is configured to obtain an upgrade configuration file from a cache after receiving an upgrade instruction sent by the CPU, where the upgrade instruction is sent after the CPU sends a latch instruction;
the loading module 43 is configured to send a loading completion notification to the CPU after the upgrade configuration file is loaded, so that the CPU sends an unlocking instruction;
and the unlocking module 44 is used for unlocking the current signal state of the selected port after receiving the unlocking instruction, and running the upgrade configuration file based on the current signal state of the selected port.
The scheme can not change the signal state of the selected port for many times in the upgrading process of the programmable logic device, and can keep the current signal state of the selected port all the time, thereby avoiding the interruption of the service being executed by the selected device, avoiding the service interruption of the network equipment, realizing the seamless upgrading of the programmable logic device and further ensuring the realization of the seamless upgrading of the network equipment.
Specifically, the unlocking module 44 is configured to run an upgrade configuration file based on the current signal state of the selected port, and specifically configured to:
reading the current signal state of the selected port;
and after the default signal state of the selected port in the upgrading configuration file is replaced by the current signal state of the selected port, the upgrading configuration file is operated.
Based on the same inventive concept, an upgrade apparatus for a programmable logic device according to an embodiment of the present invention is applied to a CPU connected to a programmable logic device, as compared with the method shown in fig. 3, and the structure of the upgrade apparatus is shown in fig. 5, and includes:
the saving module 51 is configured to, after detecting an upgrade configuration file of the programmable logic device, save the upgrade configuration file in a cache connected to the programmable logic device;
a detection module 52, configured to detect whether the programmable logic device supports a latch function;
the first sending module 53 is configured to send a latch instruction to the programmable logic device if it is detected that the programmable logic device supports the latch function, so that the programmable logic device latches a current signal state of a selected port connected to the selected device in the programmable logic device after receiving the latch instruction;
a second sending module 54, configured to send an upgrade instruction to the programmable logic device, so that after the programmable logic device receives the upgrade instruction, the programmable logic device obtains the upgrade configuration file from the cache, loads the upgrade configuration file, and sends a loading completion notification to the CPU;
and the transceiver module 55 is configured to send an unlocking instruction to the programmable logic device after receiving the load completion notification, so that the programmable logic device unlocks the current signal state of the selected port after receiving the unlocking instruction, and runs the upgrade configuration file based on the current signal state of the selected port.
The scheme can not change the signal state of the selected port for many times in the upgrading process of the programmable logic device, and can keep the current signal state of the selected port all the time, thereby avoiding the interruption of the service being executed by the selected device, avoiding the service interruption of the network equipment, realizing the seamless upgrading of the programmable logic device and further ensuring the realization of the seamless upgrading of the network equipment.
Specifically, the saving module 51 is configured to detect an upgrade configuration file of the programmable logic device, and specifically configured to:
detecting an upgrade configuration file of a programmable logic device stored by a user; or,
and detecting prompt information of the upgrade configuration file of the programmable logic device provided by a third party.
Specifically, the detecting module 52 is configured to detect whether the programmable logic device supports the latch function, and specifically configured to:
acquiring attribute information of a programmable logic device;
whether the programmable logic device supports the latch function is determined from the attribute information of the programmable logic device.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While alternative embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following appended claims be interpreted as including alternative embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made in the embodiments of the present invention without departing from the spirit or scope of the embodiments of the invention. Thus, if such modifications and variations of the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to encompass such modifications and variations.
Claims (10)
1. A method for upgrading a programmable logic device is applied to the programmable logic device, and is characterized by comprising the following steps:
after receiving a latch instruction sent by a Central Processing Unit (CPU) connected with the programmable logic device, latching the current signal state of a selected port connected with the selected device in the programmable logic device, wherein the latch instruction is sent after the CPU detects an upgrade configuration file of the programmable logic device, stores the upgrade configuration file in a cache connected with the programmable logic device and detects that the programmable logic device supports a latch function;
after an upgrading instruction sent by the CPU is received, the upgrading configuration file is obtained from the cache, and the upgrading instruction is sent after the CPU sends the latching instruction;
after the upgrade configuration file is loaded, sending a loading completion notice to the CPU so that the CPU sends an unlocking instruction;
and after receiving the unlocking instruction, unlocking the current signal state of the selected port, and operating the upgrading configuration file based on the current signal state of the selected port.
2. The method of claim 1, wherein running the upgrade configuration file based on the current signal state of the selected port comprises:
reading the current signal state of the selected port;
and after the default signal state of the selected port in the upgrading configuration file is replaced by the current signal state of the selected port, operating the upgrading configuration file.
3. A method for upgrading a programmable logic device is applied to a CPU connected with the programmable logic device, and is characterized by comprising the following steps:
after detecting the upgrade configuration file of the programmable logic device, storing the upgrade configuration file in a cache connected with the programmable logic device;
detecting whether the programmable logic device supports a latch function;
if the programmable logic device is detected to support the latching function, a latching instruction is sent to the programmable logic device, so that the programmable logic device latches the current signal state of a selected port connected with a selected device in the programmable logic device after receiving the latching instruction;
sending an upgrade instruction to the programmable logic device, so that the programmable logic device obtains the upgrade configuration file from the cache after receiving the upgrade instruction, loads the upgrade configuration file, and sends a loading completion notification to the CPU;
and after receiving the loading completion notice, sending an unlocking instruction to the programmable logic device, so that the programmable logic device unlocks the current signal state of the selected port after receiving the unlocking instruction, and operating the upgrade configuration file based on the current signal state of the selected port.
4. The method of claim 3, wherein detecting the upgrade configuration file for the programmable logic device specifically comprises:
detecting an upgrade configuration file of the programmable logic device stored by a user; or,
and detecting prompt information of the upgrade configuration file of the programmable logic device provided by a third party.
5. The method of claim 3 or 4, wherein detecting whether the programmable logic device supports a latching function comprises:
acquiring attribute information of the programmable logic device;
determining from the attribute information of the programmable logic device whether the programmable logic device supports a latching function.
6. An upgrade apparatus for a programmable logic device, applied to the programmable logic device, the apparatus comprising:
the latch module is used for latching the current signal state of a selected port connected with a selected device in the programmable logic device after receiving a latch instruction sent by a Central Processing Unit (CPU) connected with the programmable logic device, wherein the latch instruction is sent after the CPU detects an upgrade configuration file of the programmable logic device, stores the upgrade configuration file in a cache connected with the programmable logic device and detects that the programmable logic device supports a latch function;
the obtaining module is used for obtaining the upgrading configuration file from the cache after receiving an upgrading instruction sent by the CPU, wherein the upgrading instruction is sent after the CPU sends the latching instruction;
the loading module is used for sending a loading completion notice to the CPU after the upgrading configuration file is loaded so as to enable the CPU to send an unlocking instruction;
and the unlocking module is used for unlocking and latching the current signal state of the selected port after receiving the unlocking instruction, and operating the upgrading configuration file based on the current signal state of the selected port.
7. The apparatus of claim 6, wherein the unlocking module is configured to run the upgrade configuration file based on a current signal state of the selected port, and is specifically configured to:
reading the current signal state of the selected port;
and after the default signal state of the selected port in the upgrading configuration file is replaced by the current signal state of the selected port, operating the upgrading configuration file.
8. An upgrade apparatus for a programmable logic device, which is applied to a CPU connected to the programmable logic device, the apparatus comprising:
the storage module is used for storing the upgrading configuration file in a cache connected with the programmable logic device after detecting the upgrading configuration file of the programmable logic device;
the detection module is used for detecting whether the programmable logic device supports a latch function or not;
the first sending module is used for sending a latch instruction to the programmable logic device if the programmable logic device is detected to support the latch function, so that the programmable logic device latches the current signal state of a selected port connected with a selected device in the programmable logic device after receiving the latch instruction;
a second sending module, configured to send an upgrade instruction to the programmable logic device, so that after the programmable logic device receives the upgrade instruction, the programmable logic device obtains the upgrade configuration file from the cache, loads the upgrade configuration file, and sends a load completion notification to the CPU;
and the transceiver module is used for sending an unlocking instruction to the programmable logic device after receiving the loading completion notification, so that the programmable logic device unlocks the current signal state of the selected port after receiving the unlocking instruction, and runs the upgrade configuration file based on the current signal state of the selected port.
9. The apparatus of claim 8, wherein the saving module is configured to detect an upgrade configuration file of the programmable logic device, and specifically to:
detecting an upgrade configuration file of the programmable logic device stored by a user; or,
and detecting prompt information of the upgrade configuration file of the programmable logic device provided by a third party.
10. The apparatus according to claim 8 or 9, wherein the detection module is configured to detect whether the programmable logic device supports a latch function, and is specifically configured to:
acquiring attribute information of the programmable logic device;
determining from the attribute information of the programmable logic device whether the programmable logic device supports a latching function.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113821240A (en) * | 2021-09-03 | 2021-12-21 | 锐捷网络股份有限公司 | Firmware upgrading method, electronic equipment, storage medium and signal latch circuit |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1512336A (en) * | 2002-12-28 | 2004-07-14 | 深圳市中兴通讯股份有限公司 | 8051 monolithic system upgrading method and monitoring circuit |
| CN101420328A (en) * | 2008-12-03 | 2009-04-29 | 杭州华三通信技术有限公司 | System, interface card and method for remote upgrading field programmable gate array |
| CN101853172A (en) * | 2010-05-24 | 2010-10-06 | 中兴通讯股份有限公司 | Device and method for dynamically upgrading complex programmable logic device (CPLD) |
| CN101894029A (en) * | 2010-06-21 | 2010-11-24 | 中兴通讯股份有限公司 | Method and device for upgrading complex programmable logic device on line |
| US20100325404A1 (en) * | 2009-06-17 | 2010-12-23 | International Business Machines Corproation | Updating Programmable Logic Devices |
| CN102662701A (en) * | 2012-03-28 | 2012-09-12 | 中兴通讯股份有限公司 | Online CPLD (Complex Programmable Logic Devices) upgrading method, device and business veneer |
| CN204537117U (en) * | 2015-04-23 | 2015-08-05 | 绵阳灵通电讯设备有限公司 | A kind of FPGA remote online upgrade-system based on microprocessor |
| CN105094876A (en) * | 2014-05-20 | 2015-11-25 | 华为技术有限公司 | CPLD (Complex Programmable Logic Device) upgrading processing method, apparatus and system |
| CN105468387A (en) * | 2014-09-03 | 2016-04-06 | 华为技术有限公司 | Upgrade processing method, device and system |
| CN105843120A (en) * | 2016-04-06 | 2016-08-10 | 清华大学 | Dynamic programmable signal detection circuit and method |
| CN106201590A (en) * | 2016-06-29 | 2016-12-07 | 瑞斯康达科技发展股份有限公司 | A kind of FPGA configuration file loading method and system |
| WO2017041567A1 (en) * | 2015-09-07 | 2017-03-16 | 武汉精测电子技术股份有限公司 | Fpga multi-mirror upgrade loading method and device based on soft core processor |
-
2019
- 2019-07-26 CN CN201910684015.7A patent/CN110442365A/en not_active Withdrawn
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1512336A (en) * | 2002-12-28 | 2004-07-14 | 深圳市中兴通讯股份有限公司 | 8051 monolithic system upgrading method and monitoring circuit |
| CN101420328A (en) * | 2008-12-03 | 2009-04-29 | 杭州华三通信技术有限公司 | System, interface card and method for remote upgrading field programmable gate array |
| US20100325404A1 (en) * | 2009-06-17 | 2010-12-23 | International Business Machines Corproation | Updating Programmable Logic Devices |
| CN101853172A (en) * | 2010-05-24 | 2010-10-06 | 中兴通讯股份有限公司 | Device and method for dynamically upgrading complex programmable logic device (CPLD) |
| CN101894029A (en) * | 2010-06-21 | 2010-11-24 | 中兴通讯股份有限公司 | Method and device for upgrading complex programmable logic device on line |
| CN102662701A (en) * | 2012-03-28 | 2012-09-12 | 中兴通讯股份有限公司 | Online CPLD (Complex Programmable Logic Devices) upgrading method, device and business veneer |
| CN105094876A (en) * | 2014-05-20 | 2015-11-25 | 华为技术有限公司 | CPLD (Complex Programmable Logic Device) upgrading processing method, apparatus and system |
| CN105468387A (en) * | 2014-09-03 | 2016-04-06 | 华为技术有限公司 | Upgrade processing method, device and system |
| CN204537117U (en) * | 2015-04-23 | 2015-08-05 | 绵阳灵通电讯设备有限公司 | A kind of FPGA remote online upgrade-system based on microprocessor |
| WO2017041567A1 (en) * | 2015-09-07 | 2017-03-16 | 武汉精测电子技术股份有限公司 | Fpga multi-mirror upgrade loading method and device based on soft core processor |
| KR20180077163A (en) * | 2015-09-07 | 2018-07-06 | 우한 징세 일렉트로닉 그룹 컴퍼니 리미티드 | FPGA multi-mirror upgrade loading method and device based on soft-core processor |
| CN105843120A (en) * | 2016-04-06 | 2016-08-10 | 清华大学 | Dynamic programmable signal detection circuit and method |
| CN106201590A (en) * | 2016-06-29 | 2016-12-07 | 瑞斯康达科技发展股份有限公司 | A kind of FPGA configuration file loading method and system |
Non-Patent Citations (2)
| Title |
|---|
| 周琼等: "单核FPGA系统的可靠性远程升级设计", 《中国新通信》 * |
| 李学华等: "换体DMA高速数据采集电路的CPLD实现", 《电子技术应用》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113821240A (en) * | 2021-09-03 | 2021-12-21 | 锐捷网络股份有限公司 | Firmware upgrading method, electronic equipment, storage medium and signal latch circuit |
| CN113821240B (en) * | 2021-09-03 | 2023-11-17 | 锐捷网络股份有限公司 | Firmware upgrading method, electronic device, storage medium and signal latch circuit |
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Application publication date: 20191112 |