CN110427089B - Power-on reset system and method applicable to LED display screen chip - Google Patents
Power-on reset system and method applicable to LED display screen chip Download PDFInfo
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- CN110427089B CN110427089B CN201910859756.4A CN201910859756A CN110427089B CN 110427089 B CN110427089 B CN 110427089B CN 201910859756 A CN201910859756 A CN 201910859756A CN 110427089 B CN110427089 B CN 110427089B
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- 238000000034 method Methods 0.000 title claims description 13
- 230000000087 stabilizing effect Effects 0.000 claims abstract description 115
- 238000001514 detection method Methods 0.000 claims abstract description 38
- 230000005669 field effect Effects 0.000 claims description 81
- 230000002159 abnormal effect Effects 0.000 claims description 25
- 238000012544 monitoring process Methods 0.000 claims description 6
- 238000007599 discharging Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 7
- 230000001105 regulatory effect Effects 0.000 description 6
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- 239000003381 stabilizer Substances 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
- H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/28—Modifications for introducing a time delay before switching
- H03K17/284—Modifications for introducing a time delay before switching in field effect transistor switches
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Abstract
The invention provides a power-on reset system suitable for an LED display screen chip, which comprises an LED driving circuit, a voltage stabilizing source, a digital control and storage circuit, a power-on reset circuit and a low-voltage detection circuit; the LED driving circuit, the low-voltage detection circuit and the voltage stabilizing source work in an external input power supply VIN, the voltage stabilizing source outputs an internal voltage stabilizing source VLDO, and the digital control and storage circuit and the power-on reset circuit work in the internal voltage stabilizing source VLDO; the output end of the low-voltage detection circuit is connected to the voltage stabilizing source, the output end of the power-on reset circuit is connected to the input end of the digital control and storage circuit, and the output end of the digital control and storage circuit is connected to the LED driving circuit. The power-on reset system can monitor the external input power source VIN and the internal voltage stabilizing source VLDO simultaneously, and avoids display disorder of the LED display screen.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a power-on reset system and method suitable for an LED display screen chip.
Background
The Power-On Reset circuit (POR) is an important component module of the integrated circuit system, and is mainly used for providing a Reset signal for the integrated circuit system, and when the Power supply voltage is lower than a certain voltage value, the Reset signal is generated to the digital control and storage circuit so as to ensure that each logic state has a definite value in the initial stage of Power-On of the system.
The existing power-on reset system of the LED display screen chip generally has two implementation schemes, one implementation scheme is shown in fig. 1, an LED driving circuit, a voltage stabilizing source and a power-on reset circuit work in an external input power source VIN domain, a digital control and storage circuit works in an internal voltage stabilizing source VLDO domain, and the implementation scheme has the advantages that the power-on reset circuit can monitor the change of the external input power source in real time, and then a power-on reset signal Por is sent to the digital control and storage circuit. The disadvantage of this implementation is that abnormal fluctuations of the regulated voltage source cannot be monitored, which may lead to disturbances in the digital control system or loss of data in the memory circuit. Thereby causing the display disorder of the LED display screen controlled by the LED display driving circuit and the abnormal phenomena such as 'screen display' and the like.
In another implementation scheme, as shown in fig. 2, the LED driving circuit and the voltage stabilizing source operate in an external input power source VIN domain, and the power-on reset circuit and the digital control and storage circuit operate in an internal voltage stabilizing source VLDO domain.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a power-on reset system and a power-on reset method suitable for an LED display screen chip, which can monitor an external input power source VIN and an internal voltage stabilizing source VLDO simultaneously and avoid display disorder of the LED display screen.
In a first aspect, a power-on reset system suitable for use in an LED display screen chip includes an LED driving circuit, a voltage stabilizing source, a digital control and storage circuit, and a power-on reset circuit; the low-voltage detection circuit is also included;
The LED driving circuit, the low-voltage detection circuit and the voltage stabilizing source work in an external input power supply VIN, the voltage stabilizing source outputs an internal voltage stabilizing source VLDO, and the digital control and storage circuit and the power-on reset circuit work in the internal voltage stabilizing source VLDO;
the output end of the low-voltage detection circuit is connected to the voltage stabilizing source, the output end of the power-on reset circuit is connected to the input end of the digital control and storage circuit, and the output end of the digital control and storage circuit is connected to the LED driving circuit.
Preferably, the power-on reset circuit comprises a field effect tube PM0, a field effect tube PM1, a field effect tube PM2, a field effect tube NM0, a Schmitt trigger and a first single-side delay circuit;
The drain electrode of the field effect tube PM0 is grounded through a resistor R4, the grid electrode of the field effect tube PM0 is connected with the drain electrode of the field effect tube PM0, the grid electrode of the field effect tube PM0 is also connected with the grid electrode of the field effect tube PM1, and the source electrode of the field effect tube PM0 is connected with the internal voltage stabilizing source VLDO; the source electrode of the field effect tube PM1 is connected with the internal voltage stabilizing source VLDO, the drain electrode of the field effect tube PM1 is connected with the grid electrode of the field effect tube NM0, the source electrode of the field effect tube NM0 is grounded, and the drain electrode of the field effect tube NM0 is connected with the source electrode of the field effect tube NM 0; the grid electrode and the source electrode of the field effect tube PM2 are connected with the internal voltage stabilizing source VLDO, the drain electrode of the field effect tube PM2 is connected with the input end of the Schmitt trigger, and the intermediate node between the drain electrode of the field effect tube PM1 and the grid electrode of the field effect tube NM0 is connected with the input end of the Schmitt trigger;
The output end of the Schmitt trigger is connected to the input end of the digital control and storage circuit through the first unilateral delay circuit.
Preferably, the first unilateral delay circuit comprises a first delay unit and a first AND gate;
The output end of the schmitt trigger is connected to the input end of the digital control and storage circuit through the first unilateral delay circuit, and the output end of the schmitt trigger specifically comprises:
The output end of the Schmitt trigger is connected with one input end of the first AND gate through the first delay unit in series, the output end of the Schmitt trigger is also connected with the other input end of the first AND gate, and the output end of the first AND gate is connected with the input end of the digital control and storage circuit.
Preferably, the field effect tube PM0, the field effect tube PM1 and the field effect tube PM2 are PNP field effect tubes; the field effect transistor NM0 is an NPN field effect transistor.
Preferably, the low voltage detection circuit comprises a selector, a comparator, a first inverter, a second inverter and a second unilateral delay circuit;
The input end of the alternative selector is connected with an external input power supply VIN through a resistor voltage dividing circuit, the output end of the alternative selector is connected with the positive input end of the comparator, the negative input end of the comparator is connected with a reference power supply, the output end of the comparator is connected with the voltage stabilizing source through a first inverter, a second inverter and a second unilateral delay circuit which are sequentially connected in series, and the middle node of the first inverter and the second inverter is connected with the control end of the alternative selector.
Preferably, the resistor divider circuit includes a resistor R1, a resistor R2, and a resistor R3;
The input terminal of the alternative selector is connected to an external input power source VIN through a resistor divider circuit, and specifically includes:
one input end of the two-way selector is connected with an external input power supply VIN through a resistor R1, the other input end of the two-way selector is grounded through a resistor R3, and a resistor R2 is further connected between the two input ends of the two-way selector.
Preferably, the second unilateral delay circuit comprises a second delay unit and a first or gate;
The output end of the comparator is connected to the voltage stabilizing source through a first inverter, a second inverter and a second unilateral delay circuit which are sequentially connected in series, and the voltage stabilizing source specifically comprises:
The output end of the comparator is connected with the input end of the second delay unit through a first inverter and a second inverter which are sequentially connected in series, the output end of the second delay unit is connected with one input end of the first OR gate, the output end of the second inverter is connected with the other input end of the first OR gate, and the output end of the first OR gate is connected to the voltage stabilizing source.
In a second aspect, a power-on reset method suitable for use in an LED display screen chip, running on the power-on reset system of the first aspect, includes the steps of:
the low-voltage detection circuit is used for monitoring an external input power supply VIN in real time, and pulling down an internal voltage-stabilizing source VLDO output by the voltage-stabilizing source when the external input power supply VIN is abnormal;
The power-on reset circuit is used for monitoring the internal voltage stabilizing source VLDO in real time, and resetting the digital control and storage circuit when the internal voltage stabilizing source VLDO is detected to be abnormal, and closing the LED display screen.
Preferably, the low voltage detection circuit is configured to monitor the external input power source VIN in real time, and when the external input power source VIN is abnormal, pull down the internal regulated power source VLDO output by the regulated power source specifically includes:
When the low-voltage detection circuit detects that the external input power supply VIN is higher than or equal to the reference power supply, the voltage stabilizing source is controlled to normally output an internal voltage stabilizing source VLDO;
when the low voltage detection circuit detects that the external input power source VIN is lower than the reference power source, the internal voltage stabilizing source VLDO output by the voltage stabilizing source is pulled down.
Preferably, the power-on reset circuit is configured to monitor the internal voltage stabilizing source VLDO in real time, and reset the digital control and storage circuit when detecting that the internal voltage stabilizing source VLDO is abnormal, and closing the LED display screen specifically includes:
When detecting that an internal voltage stabilizing source VLDO output by the voltage stabilizing source is normal, the power-on reset circuit generates a starting instruction and sends the starting instruction to the digital control and storage circuit, so that the digital control and storage circuit controls the LED driving circuit to work normally and drives the LED display screen to light;
When detecting that the internal voltage stabilizing source VLDO output by the voltage stabilizing source is low, the power-on reset circuit generates a reset instruction and sends the reset instruction to the digital control and storage circuit, so that the digital control and storage circuit controls the LED driving circuit to reset and drives the LED display screen to be closed.
According to the technical scheme, the power-on reset system and the power-on reset method suitable for the LED display screen chip can monitor the external input power source VIN and the internal voltage stabilizing source VLDO simultaneously, and can respond in time if the external input power source VIN or the internal voltage stabilizing source VLDO is abnormal, send a low-level reset signal to the digital control and storage circuit, further control the LED driving circuit to close the display function of the LED display screen, and avoid abnormal phenomena such as 'screen display' and the like.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. Like elements or portions are generally identified by like reference numerals throughout the several figures. In the drawings, elements or portions thereof are not necessarily drawn to scale.
FIG. 1 is a block diagram of a power-on reset system according to the background of the invention.
FIG. 2 is a block diagram of another power-on-reset system according to the background of the invention.
Fig. 3 is a schematic block diagram of a power-on reset system according to an embodiment of the invention.
Fig. 4 is a circuit diagram of a power-on reset circuit according to an embodiment of the invention.
Fig. 5 is a circuit diagram of a low voltage detection circuit according to an embodiment of the invention.
FIG. 6 is a timing diagram of a power-on-reset system according to the present invention.
Detailed Description
Embodiments of the technical scheme of the present application will be described in detail below with reference to the accompanying drawings. The following examples are only for more clearly illustrating the technical aspects of the present application, and thus are merely examples, and are not intended to limit the scope of the present application. It is noted that unless otherwise indicated, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs.
It should be understood that the terms "comprises" and "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
As used in this specification and the appended claims, the term "if" may be interpreted as "when..once" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if a determination" or "if a [ described condition or event ] is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a [ described condition or event ]" or "in response to detection of a [ described condition or event ]".
Embodiment one:
a power-on reset system suitable for use in an LED display screen chip, see fig. 3, includes an LED driving circuit, a voltage stabilizing source, a digital control and storage circuit, and a power-on reset circuit; the low-voltage detection circuit is also included;
The LED driving circuit, the low-voltage detection circuit and the voltage stabilizing source work in an external input power supply VIN, the voltage stabilizing source outputs an internal voltage stabilizing source VLDO, and the digital control and storage circuit and the power-on reset circuit work in the internal voltage stabilizing source VLDO;
the output end of the low-voltage detection circuit is connected to the voltage stabilizing source, the output end of the power-on reset circuit is connected to the input end of the digital control and storage circuit, and the output end of the digital control and storage circuit is connected to the LED driving circuit.
Specifically, the output end of the LED driving circuit is connected with the LED display screen to control the LED display screen to be turned on or turned off. The power-on reset system can monitor the external input power source VIN and the internal voltage stabilizing source VLDO simultaneously, and can respond in time if the external input power source VIN or the internal voltage stabilizing source VLDO is abnormal, and send a low-level reset signal to the digital control and storage circuit, so as to control the LED drive circuit to close the display function of the LED display screen, avoid the display disorder of the LED display screen and the abnormal phenomena such as 'screen pattern', and the like.
Referring to fig. 4, the power-on reset circuit includes a field effect transistor PM0, a field effect transistor PM1, a field effect transistor PM2, a field effect transistor NM0, a schmitt trigger, a first delay unit, and a first and gate;
The drain electrode of the field effect tube PM0 is grounded through a resistor R4, the grid electrode of the field effect tube PM0 is connected with the drain electrode of the field effect tube PM0, the grid electrode of the field effect tube PM0 is also connected with the grid electrode of the field effect tube PM1, and the source electrode of the field effect tube PM0 is connected with the internal voltage stabilizing source VLDO; the source electrode of the field effect tube PM1 is connected with the internal voltage stabilizing source VLDO, the drain electrode of the field effect tube PM1 is connected with the grid electrode of the field effect tube NM0, the source electrode of the field effect tube NM0 is grounded, and the drain electrode of the field effect tube NM0 is connected with the source electrode of the field effect tube NM 0; the grid electrode and the source electrode of the field effect tube PM2 are connected with the internal voltage stabilizing source VLDO, the drain electrode of the field effect tube PM2 is connected with the input end of the Schmitt trigger, and the intermediate node between the drain electrode of the field effect tube PM1 and the grid electrode of the field effect tube NM0 is connected with the input end of the Schmitt trigger;
The output end of the Schmitt trigger is connected with one input end of the first AND gate through the first delay unit in series, the output end of the Schmitt trigger is also connected with the other input end of the first AND gate, and the output end of the first AND gate is connected with the input end of the digital control and storage circuit.
Specifically, the fet PM0, the fet PM1, and the resistor R4 are used to generate the bias current Ictrl, the fet NM0 is connected in a capacitance form, and the fet PM2 is used as a discharge path for discharging. When the internal voltage stabilizing source VLDO rises, a bias current is generated to charge NM0, and when the voltage at the point A is higher than the turnover threshold value of the Schmitt trigger, the output por_i of the Schmitt trigger is in a high level; when the voltage of the internal voltage stabilizing source VLDO drops, the voltage at point a is discharged to the internal voltage stabilizing source VLDO through the field effect transistor PM2, so that the voltage at point a drops.
The delay unit and the AND gate realize a unilateral delay function, and when the por_i signal rises to a high level, the Por rises to the high level after the delay of the delay unit is needed; conversely, when the por_i signal falls to a low level, the Por signal immediately falls to a low level. The delay is increased in the power-on process of the voltage stabilizing source, the reliability reset of the digital circuit is facilitated, and the immediate reset can enhance the timely treatment of abnormal conditions when the power is turned off.
Preferably, the field effect tube PM0, the field effect tube PM1 and the field effect tube PM2 are PNP field effect tubes; the field effect transistor NM0 is an NPN field effect transistor.
Referring to fig. 5, the low voltage detection circuit includes a selector, a comparator, a first inverter, a second delay unit and a first or gate;
the output end of the two-way selector is connected with the positive input end of the comparator, the negative input end of the comparator is connected with the reference power supply, and the output end of the comparator is connected to the input end of the second delay unit through a first inverter and a second inverter which are sequentially connected in series; the intermediate node of the first inverter and the second inverter is connected with the control end of the alternative selector, the output end of the second delay unit is connected with one input end of the first OR gate, the output end of the second inverter is connected with the other input end of the first OR gate, and the output end of the first OR gate is connected to the voltage stabilizing source.
Specifically, the resistors R1, R2, R3 form a resistor divider circuit, when the control terminal (i.e., the s terminal) of the alternative selector MUX2-1 is at a low level, the MUX2-1 outputs a signal at the in1 terminal, and when the s terminal is at a high level, the MUX2-1 outputs a signal at the in2 terminal. The external input power supply VIN is divided by resistors R1, R2 and R3 to generate voltages V1 and V2, wherein R2 is a small resistor and is used for generating comparison hysteresis and improving the anti-interference capability. The voltages V1 and V2 are calculated as follows:
vref is a reference power supply, and is input to the negative input end of the comparator, when the external input power supply VIN is lower, the voltages of V1 and V2 are lower, vdet is smaller than Vref through the alternative selector, the output out_p of the comparator is low level, and the output out_n of the comparator is high level through the first inverter inv_1.
The delay unit and the OR gate realize a unilateral delay function, when the pdr_i signal rises to a high level, the Pdr signal immediately rises to a high level, otherwise, when the pdr_i signal falls to a low level, the Pdr signal is required to fall to a low level after delay of the delay unit. When the external input power source VIN is larger than the reference power source, the Pdr is immediately released to be high level, so that the voltage stabilizing source can be started quickly, delay is increased when power is turned off, false overturning caused by disturbance of the external power source is facilitated, and anti-interference capability is improved.
Embodiment two:
a power-on reset method suitable for an LED display screen chip is operated on the power-on reset system in the first embodiment, and comprises the following steps:
the low-voltage detection circuit is used for monitoring an external input power supply VIN in real time, and pulling down an internal voltage-stabilizing source VLDO output by the voltage-stabilizing source when the external input power supply VIN is abnormal;
The power-on reset circuit is used for monitoring the internal voltage stabilizing source VLDO in real time, and resetting the digital control and storage circuit when the internal voltage stabilizing source VLDO is detected to be abnormal, and closing the LED display screen.
Preferably, the low voltage detection circuit is configured to monitor the external input power source VIN in real time, and when the external input power source VIN is abnormal, pull down the internal regulated power source VLDO output by the regulated power source specifically includes:
When the low-voltage detection circuit detects that the external input power supply VIN is higher than or equal to the reference power supply, the voltage stabilizing source is controlled to normally output an internal voltage stabilizing source VLDO;
when the low voltage detection circuit detects that the external input power source VIN is lower than the reference power source, the internal voltage stabilizing source VLDO output by the voltage stabilizing source is pulled down.
Preferably, the power-on reset circuit is configured to monitor the internal voltage stabilizing source VLDO in real time, and reset the digital control and storage circuit when detecting that the internal voltage stabilizing source VLDO is abnormal, and closing the LED display screen specifically includes:
When detecting that an internal voltage stabilizing source VLDO output by the voltage stabilizing source is normal, the power-on reset circuit generates a starting instruction and sends the starting instruction to the digital control and storage circuit, so that the digital control and storage circuit controls the LED driving circuit to work normally and drives the LED display screen to light;
When detecting that the internal voltage stabilizing source VLDO output by the voltage stabilizing source is low, the power-on reset circuit generates a reset instruction and sends the reset instruction to the digital control and storage circuit, so that the digital control and storage circuit controls the LED driving circuit to reset and drives the LED display screen to be closed.
Specifically, when the external input power VIN is normally powered up to a voltage higher than a certain voltage value (i.e., a reference power), the regulated power supply starts to operate. After the voltage stabilizing source stably outputs and delays for a period of time, the power-on reset circuit sends out a reset completion signal Por, and the digital control and storage circuit starts to control the LED driving circuit to normally work, so that the LED driving circuit drives the LED display screen to normally light.
When the external input power source VIN is lower than the reference power source, the low-voltage detection circuit sends a low-level signal Pdr to the voltage stabilizing source, so that the voltage of the internal voltage stabilizing source VLDO output by the voltage stabilizer is pulled down to a low potential, at the moment, the power-on reset circuit monitors that the voltage stabilizing source outputs the internal voltage stabilizing source VLDO to be low, and then sends a low-level reset signal Por to the digital control and storage circuit, and further controls the LED driving circuit to close the LED display screen.
The method can monitor the external input power supply VIN and the internal voltage stabilizing source VLDO simultaneously, and can respond in time if the external input power supply VIN or the internal voltage stabilizing source VLDO is abnormal, and send a low-level reset signal to the digital control and storage circuit, so as to control the LED drive circuit to close the display function of the LED display screen, and avoid abnormal phenomena such as 'screen display' and the like.
FIG. 6 is a timing diagram of a power-on-reset system according to the present invention, and the timing is described as follows:
At the moment A, the external input power source VIN starts to be electrified;
at the moment B, when the external input power supply VIN is electrified to be higher than the reference power supply, the low-voltage detection circuit sends out a high-level Pdr signal, and the voltage stabilizing source starts to work;
at the moment C, the voltage stabilizing source outputs an internal voltage stabilizing source VLDO to rise to an expected voltage value;
at the moment D, after the voltage stabilizing source normally outputs and delays for a period of time, the power-on reset circuit sends out a high-level reset completion signal;
at the moment E, the external input power supply VIN is abnormal and falls below a reference power supply;
At the moment F, if the low-voltage detection circuit detects that VIN is abnormal for a period of time, the external input power supply is considered to be abnormal, the low-voltage detection circuit sends a low-level signal, and the internal voltage stabilizing source VLDO of the voltage stabilizing source is pulled down to a low level;
At the moment G, when the external input power supply VIN is recovered to be higher than the reference power supply, the low-voltage detection circuit sends out a high-level Pdr signal, and the voltage stabilizing source starts to work;
At time H, after the voltage stabilizing source outputs normally and delays for a period of time, the power-on reset circuit sends out a high-level reset completion signal.
For a brief description of the method provided by the embodiments of the present invention, reference may be made to the corresponding content in the foregoing system embodiments where the description of the embodiments is not mentioned.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention, and are intended to be included within the scope of the appended claims and description.
Claims (10)
1. A power-on reset system suitable for an LED display screen chip comprises an LED driving circuit, a voltage stabilizing source, a digital control and storage circuit and a power-on reset circuit; the low-voltage detection circuit is characterized by also comprising a low-voltage detection circuit;
The LED driving circuit, the low-voltage detection circuit and the voltage stabilizing source work in an external input power supply VIN, the voltage stabilizing source outputs an internal voltage stabilizing source VLDO, and the digital control and storage circuit and the power-on reset circuit work in the internal voltage stabilizing source VLDO;
the output end of the low-voltage detection circuit is connected to the voltage stabilizing source, the output end of the power-on reset circuit is connected to the input end of the digital control and storage circuit, and the output end of the digital control and storage circuit is connected to the LED drive circuit;
The power-on reset system monitors an external input power supply VIN and an internal voltage stabilizing source VLDO at the same time, and if the external input power supply VIN or the internal voltage stabilizing source VLDO is abnormal, a low-level reset signal is sent to the digital control and storage circuit to control the LED drive circuit to turn off the LED display screen;
The power-on reset circuit comprises a field effect transistor PM2 and a field effect transistor NM0; the power-on reset circuit is used for generating bias current to charge the field effect transistor NM0 when the internal voltage stabilizing source VLDO rises, and discharging the bias current to the internal voltage stabilizing source VLDO through the field effect transistor PM2 when the voltage of the internal voltage stabilizing source VLDO drops;
The low voltage detection circuit comprises a two-out selector, wherein when the control end of the two-out selector is at a low level, the two-out selector outputs a signal at the in1 end, and when the control end of the two-out selector is at a high level, the two-out selector outputs a signal at the in2 end.
2.A power-on-reset system suitable for use in an LED display chip as recited in claim 1, wherein,
The power-on reset circuit comprises a field effect tube PM0, a field effect tube PM1, a Schmidt trigger and a first unilateral delay circuit;
The drain electrode of the field effect tube PM0 is grounded through a resistor R4, the grid electrode of the field effect tube PM0 is connected with the drain electrode of the field effect tube PM0, the grid electrode of the field effect tube PM0 is also connected with the grid electrode of the field effect tube PM1, and the source electrode of the field effect tube PM0 is connected with the internal voltage stabilizing source VLDO; the source electrode of the field effect tube PM1 is connected with the internal voltage stabilizing source VLDO, the drain electrode of the field effect tube PM1 is connected with the grid electrode of the field effect tube NM0, the source electrode of the field effect tube NM0 is grounded, and the drain electrode of the field effect tube NM0 is connected with the source electrode of the field effect tube NM 0; the grid electrode and the source electrode of the field effect tube PM2 are connected with the internal voltage stabilizing source VLDO, the drain electrode of the field effect tube PM2 is connected with the input end of the Schmitt trigger, and the intermediate node between the drain electrode of the field effect tube PM1 and the grid electrode of the field effect tube NM0 is connected with the input end of the Schmitt trigger;
The output end of the Schmitt trigger is connected to the input end of the digital control and storage circuit through the first unilateral delay circuit.
3. A power-on-reset system suitable for use in an LED display chip as recited in claim 2, wherein,
The first unilateral delay circuit comprises a first delay unit and a first AND gate;
The output end of the schmitt trigger is connected to the input end of the digital control and storage circuit through the first unilateral delay circuit, and the output end of the schmitt trigger specifically comprises:
The output end of the Schmitt trigger is connected with one input end of the first AND gate through the first delay unit in series, the output end of the Schmitt trigger is also connected with the other input end of the first AND gate, and the output end of the first AND gate is connected with the input end of the digital control and storage circuit.
4. A power-on-reset system suitable for use in an LED display chip as recited in claim 2, wherein,
The field effect tube PM0, the field effect tube PM1 and the field effect tube PM2 are PNP field effect tubes; the field effect transistor NM0 is an NPN field effect transistor.
5. A power-on-reset system suitable for use in an LED display chip as recited in claim 1, wherein,
The low-voltage detection circuit comprises a comparator, a first inverter, a second inverter and a second unilateral delay circuit;
The input end of the alternative selector is connected with an external input power supply VIN through a resistor voltage dividing circuit, the output end of the alternative selector is connected with the positive input end of the comparator, the negative input end of the comparator is connected with a reference power supply, the output end of the comparator is connected with the voltage stabilizing source through a first inverter, a second inverter and a second unilateral delay circuit which are sequentially connected in series, and the middle node of the first inverter and the second inverter is connected with the control end of the alternative selector.
6. A power-on-reset system suitable for use in an LED display chip as recited in claim 5, wherein,
The resistor divider circuit comprises a resistor R1, a resistor R2 and a resistor R3;
The input terminal of the alternative selector is connected to an external input power source VIN through a resistor divider circuit, and specifically includes:
one input end of the two-way selector is connected with an external input power supply VIN through a resistor R1, the other input end of the two-way selector is grounded through a resistor R3, and a resistor R2 is further connected between the two input ends of the two-way selector.
7. A power-on-reset system suitable for use in an LED display chip as recited in claim 5, wherein,
The second unilateral delay circuit comprises a second delay unit and a first OR gate;
The output end of the comparator is connected to the voltage stabilizing source through a first inverter, a second inverter and a second unilateral delay circuit which are sequentially connected in series, and the voltage stabilizing source specifically comprises:
The output end of the comparator is connected with the input end of the second delay unit through a first inverter and a second inverter which are sequentially connected in series, the output end of the second delay unit is connected with one input end of the first OR gate, the output end of the second inverter is connected with the other input end of the first OR gate, and the output end of the first OR gate is connected to the voltage stabilizing source.
8. A power-on-reset method suitable for use in an LED display screen chip, characterized by running on a power-on-reset system according to any one of claims 1-7, comprising the steps of:
the low-voltage detection circuit is used for monitoring an external input power supply VIN in real time, and pulling down an internal voltage-stabilizing source VLDO output by the voltage-stabilizing source when the external input power supply VIN is abnormal;
The power-on reset circuit is used for monitoring the internal voltage stabilizing source VLDO in real time, and resetting the digital control and storage circuit when the internal voltage stabilizing source VLDO is detected to be abnormal, and closing the LED display screen.
9. The power-on reset method of claim 8, wherein the low voltage detection circuit is configured to monitor the external input power source VIN in real time, and when the external input power source VIN is abnormal, the internal voltage stabilizing source VLDO for pulling down the output of the voltage stabilizing source specifically comprises:
When the low-voltage detection circuit detects that the external input power supply VIN is higher than or equal to the reference power supply, the voltage stabilizing source is controlled to normally output an internal voltage stabilizing source VLDO;
when the low voltage detection circuit detects that the external input power source VIN is lower than the reference power source, the internal voltage stabilizing source VLDO output by the voltage stabilizing source is pulled down.
10. The power-on reset method of claim 9, wherein the power-on reset circuit is configured to monitor the internal voltage stabilizing source VLDO in real time, and reset the digital control and storage circuit when detecting that the internal voltage stabilizing source VLDO is abnormal, and closing the LED display specifically comprises:
When detecting that an internal voltage stabilizing source VLDO output by the voltage stabilizing source is normal, the power-on reset circuit generates a starting instruction and sends the starting instruction to the digital control and storage circuit, so that the digital control and storage circuit controls the LED driving circuit to work normally and drives the LED display screen to light;
When detecting that the internal voltage stabilizing source VLDO output by the voltage stabilizing source is low, the power-on reset circuit generates a reset instruction and sends the reset instruction to the digital control and storage circuit, so that the digital control and storage circuit controls the LED driving circuit to reset and drives the LED display screen to be closed.
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| CN116800238A (en) * | 2022-03-17 | 2023-09-22 | 合肥市芯海电子科技有限公司 | Power supply detection reset circuit, integrated circuit and electronic equipment |
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