CN110401805A - Receiver and related signal processing method - Google Patents

Abstract

The present invention relates to a receiver and a related signal processing method. The receiver comprises a decoder, a processing circuit and an interface circuit, wherein the decoder is used to decode a received signal to generate a first group of baseband packets and a second group of baseband packets, wherein the first group and the second group of baseband packets correspond to a first physical layer channel and a second physical layer channel respectively; the processing circuit is used to process the first group and the second group of baseband packets respectively to generate a first group and a second group of data packets, wherein the first group of data packets includes a specific data packet; the interface circuit transmits the first group and the second group of data packets to a back-end circuit in the form of a data stream, wherein a part of the specific data packet is located before the second group of data packets in the data stream, and another part is located after the second group of data packets.

Description

Receiver and related signal processing method

technical field

The present invention relates to receivers, and more particularly to a receiver supporting Advanced Television Systems Committee (ATSC) standards.

Background technique

In the ATSC 3.0 specification proposed by the Advanced Television Systems Committee, an Advanced Television Systems Committee Link Layer Protocol (ATSC Link-Layer Protocol, ALP) packet is defined, wherein the ALP packet has a variable-length header (header ) and variable-length payload (payload), as shown in Figure 1, four consecutive ALP packets (1)-(4) all have different data lengths; on the other hand, ATSC 3.0 specifications also point out these ALP packets can be transmitted through multiple physical layer pipes (Physical Layer Pipe, PLP). However, in order to process ALP packets with different lengths from multiple physical layer channels, the design of the receiver requires a higher-capacity buffer circuit, thereby increasing the manufacturing cost of the receiver.

Contents of the invention

Therefore, one of the objectives of the present invention is to provide a receiver which requires only a small-capacity buffer circuit, so as to solve the problems in the background art.

In one embodiment of the present invention, a receiver is disclosed, which includes a decoder, a processing circuit and an interface circuit, wherein the decoder is used to decode a received signal to generate a first set of baseband packets and a second set of baseband packets. Two groups of baseband packets, wherein the first group and the second group of baseband packets are respectively corresponding to a first physical layer channel and a second physical layer channel; the processing circuit is used for the first group and the second group respectively The baseband packet is processed to generate a first group and a second group of data packets, wherein the first group of data packets contains a specific data packet; and the interface circuit converts the first group and the second group of data packets into a data string stream to a backend circuit, wherein, in the data stream, a portion of the particular data packet precedes the second set of data packets and another portion of the particular data packet follows the second set of data packets .

In another embodiment of the present invention, a signal processing method is disclosed, which includes the following steps: decoding a received signal to generate a first group of baseband packets and a second group of baseband packets, wherein the first The first group and the second group of baseband packets respectively correspond to a first physical layer channel and a second physical layer channel; the first group and the second group of baseband packets are respectively processed to generate the first group and the second group of data packets, wherein the first group of data packets contains a specific data packet; and the first group and the second group of data packets are transmitted to a backend circuit in a data stream, wherein, in the data stream , a part of the specific data packet is located before the second group of data packets, and another part of the specific data packet is located after the second group of data packets.

Description of drawings

FIG. 1 is a schematic diagram of ALP packets with different data lengths.

FIG. 2 is a schematic diagram of a receiver according to an embodiment of the invention.

FIG. 3A is a schematic diagram of the relationship between a baseband packet and a data packet according to an embodiment of the present invention.

FIG. 3B is a schematic diagram of a data stream output by the multiplexer shown in FIG. 1 .

FIG. 4 is a schematic diagram of a receiver according to another embodiment of the present invention.

FIG. 5 is a flowchart of a signal processing method according to an embodiment of the present invention.

Symbol Description

200, 400 Receiver

210, 410 decoder

220, 420 processing circuit

230, 430 multiplexer

402 front-end circuit

440 interface circuit

470 chips

480 demultiplexer

Vin receiving signal

B1～B4 Fundamental frequency signal

D1～D4 data signal

Vout data stream

BP1-1, BP1-2, BP1-3, BP2-1, BP2-2, BP2-3 Baseband packets

ALP11～ALP17, ALP21～ALP27 data packet

Segments of ALP13-1, ALP13-2 data packets

Valid valid signal

SYNC synchronization signal

CLK clock signal

Detailed ways

FIG. 2 is a schematic diagram of a receiver 200 according to an embodiment of the invention. As shown in FIG. 2 , the receiver 200 includes a decoder 210 , a processing circuit 220 and a multiplexer 230 . In this embodiment, the receiver 200 supports the ATSC 3.0 specification, and is set in a TV or a TV set top box.

In the receiver 200, the decoder 210 is used to decode a received signal Vin to generate a plurality of baseband signals (eg, B1-B4), wherein each baseband signal includes one or more baseband packets. The processing circuit 220 is used to process each baseband signal respectively to generate corresponding data signals (eg, D1 - D4 ), wherein each data signal includes one or more data packets (eg, ALP packets). The multiplexer 230 is used to convert multiple data signals into a single data stream Vout, and transmit it to the back-end circuit for subsequent processing. In this embodiment, the baseband signals B1 - B4 generated by the decoder 210 are respectively corresponding to different physical layer channels, and are transmitted to the processing circuit 220 through different physical paths. However, in another embodiment, when the decoder 210 processes and outputs the four baseband signals B1 - B4 in time division, the same physical path may also be used to transmit the four baseband signals B1 - B4 to the processing circuit 220 . And in another embodiment, when the processing circuit 220 time-divisionally processes the baseband signals B1-B2 to output the data signals D1-D2, when outputting multiple data packets, they can be directly output sequentially to form a single data stream Vout, Therefore, the multiplexer 230 can also be omitted. In addition, although four baseband signals B1 - B4 are taken as an example in this embodiment, this is not a limitation of the present invention.

FIG. 3A is a schematic diagram illustrating the relationship between a baseband packet in a baseband signal and a data packet in a data signal according to an embodiment of the present invention. In the embodiment of FIG. 3A , two baseband signals B1 - B2 and two data signals D1 - D2 are taken as an example for subsequent description, but this is not a limitation of the present invention. Specifically, the decoder 210 decodes the received signal Vin to generate baseband signals B1-B2. The baseband signal B1 corresponds to the first physical layer channel, and contains baseband packets BP1-1, BP1-2, BP1-3, etc., and the baseband signal B2 corresponds to the second physical layer channel , and includes baseband packets BP2-1, BP2-2, BP2-3...etc. The baseband packet BP1-1 includes the complete data packets ALP11, ALP12, and the initial segment of the data packet ALP13; the baseband packet BP1-2 includes the second half of the data packet ALP13, the complete data packet ALP14, and The initial section of the data packet ALP15; the baseband packet BP2-1 includes the complete data packet ALP21 and the initial section of the data packet ALP22; the baseband packet BP2-2 includes the second half section of the data packet ALP22, Complete data packets ALP23, ALP24, and the start segment of data packet ALP25. After receiving the baseband packet, the processing circuit 220 processes the received baseband packet. First, the processing circuit 220 will distinguish each baseband packet according to the baseband file header (not shown) of each baseband packet. Please refer to FIG. The baseband packet header extracts the complete data packets ALP11, ALP12, the initial segment ALP13-1 of the data packet ALP13, the complete data packet ALP21, and the initial segment ALP22- of the data packet ALP22 from each baseband packet. 1. The second half section ALP13-2 of the data packet ALP13, the complete data packet ALP14... are sent to the multiplexer 230, and are converted into a single data stream Vout by the multiplexer 230, and then sent to the back-end circuit for processing.

When the processing circuit 220 processes the baseband signal to generate a corresponding data signal, as mentioned above, each baseband packet can decode one or more data packets, but since the length of the data packet is not fixed, so The last data packet generated from a baseband packet may not be complete; in other words, a complete data packet may result from the last incomplete data packet in a baseband packet (eg, BP1-1) (for example, the initial section of the data packet ALP13) and the first incomplete data packet (for example, the second half section of the data packet ALP13) in the next baseband packet (for example, BP1-2). In view of the aforementioned problems, when the multiplexer 230 is to convert multiple data signals into a single data stream Vout, a method in the prior art is to use a buffer circuit to temporarily store these incomplete data packets, for example, the data packet ALP13 first The initial section is stored in the buffer circuit, and then waits for the decoding of the back-end section of the data packet ALP13 to complete, and then transmits the complete data packet, but this will increase the cost of a lot of hardware and reduce the efficiency of signal processing . However, in this embodiment, the processing circuit 220 may allow the data packet to be transmitted in segments, that is, after the processing circuit 220 processes each baseband packet, even if the generated data packet is not complete (for example, only complete data The first half of the packet), the processing circuit 220 can still pass the incomplete data packet directly through the multiplexer 230 to the back-end circuit. As mentioned above, since the present embodiment allows data packets to be transmitted in segments, there is no need to set redundant buffer circuits in the receiver 200 to temporarily store incomplete data packets, so as to save hardware cost. The details of how to complete the segmented transmission of the data packet will be described below with an example.

In order for the backend circuit to clearly identify which data packet or which physical layer channel the received data belongs to, please refer again to the schematic diagrams of the data stream output by the multiplexer 230 shown in FIGS. 3A and 3B , before sending the data packet or a section of the data packet to the multiplexer 230, the processing circuit 220 will add a header (header) in front of the data packet or each section to provide relevant information for the backend circuit identification. Specifically, each header includes the identification code of the corresponding physical layer channel, and whether the corresponding segment is the initial segment of the data packet. For example, the processing circuit 220 may set the header of the data packet ALP11 to indicate that it belongs to the first physical layer path and is the initial segment of the data packet, and set the header of the segment ALP13-1 to indicate that it belongs to The first physical layer channel is the initial segment of the data packet, and the header of the segment ALP13-2 is set to indicate whether it belongs to the first physical layer channel and is the initial segment of the data packet.

As mentioned above, since the processing circuit 220 can transmit the deciphered data packet or a section of the data packet to the multiplexer 230 for output, it can indeed reduce the demand of the internal buffer circuit. In addition, by adding a specific header in front of each data packet or segment transmitted, the back-end circuit can reassemble each segment to obtain a complete data packet, so as to facilitate the smooth operation of the circuit.

It should be noted that the above embodiments in FIGS. 3A and 3B only describe two physical layer channels, and the data packet is only divided into two segments for transmission, but this is not a limitation of the present invention. In other embodiments of the present invention, the baseband packets processed by the processing circuit 220 of the present invention may correspond to more than two physical layer channels, and the data packets may also be divided into more than two sections for transmission.

FIG. 4 is a schematic diagram of a receiver 400 according to another embodiment of the present invention. As shown in FIG. 4 , the receiver 400 includes a front-end circuit 402 , a decoder 410 , a processing circuit 420 , a multiplexer 430 and an interface circuit 440 . In this embodiment, the receiver 400 is disposed in a chip and connected to another chip 470 through a plurality of data transmission lines.

In the operation of the receiver 400, first, the front-end circuit 402 can receive a radio frequency signal from an antenna, and perform operations such as frequency reduction and equalization on the radio frequency signal to generate a received signal Vin; then, the decoder 410, the processing circuit 420 and the multiplexer 430 process the received signal Vin to generate a single data stream Vout to the interface circuit 440, wherein the operations of the decoder 410, the processing circuit 420 and the multiplexer 430 have been described in the first to third embodiments A clear description, so the details will not be repeated here. The interface circuit 440 then transmits the data stream Vout to the chip 470 . In one embodiment, the data stream Vout can be converted into multiple data streams (for example, eight), and through multiple pins (for example, eight) to increase the transmission rate (for example, one bit at a time) Tuple (byte). In addition, the interface circuit 440 can additionally transmit a valid signal Valid, a synchronous signal SYNC and a clock signal CLK to the chip 470, wherein the valid signal Valid is used to indicate whether the current receiver 400 has a transmission data stream Vout is to the chip 470, and the synchronization signal SYNC is used to indicate/align the first byte of each data packet or the header of each sector.

After the chip 470 receives the data stream Vout, the effective signal Valid, the synchronization signal SYNC, and the clock signal CLK, the demultiplexer 480 therein will perform a demultiplexing operation on the data stream Vout to generate multiple The data signals are sent to the back-end processing circuit. In this embodiment, the demultiplexer 480 generates four data signals D1 - D4 corresponding to different physical layer channels, similar to the output of the processing circuit 420 .

FIG. 5 is a flowchart of a signal processing method according to an embodiment of the present invention. With reference to the content described in the embodiments of FIGS. 1 to 4 above, the flow of the signal processing method in FIG. 5 is as follows:

Step 500: The process starts.

Step 502: Decode a received signal to generate a plurality of baseband packets, wherein the plurality of baseband packets correspond to at least two different physical layer channels.

Step 504: Process the multiple baseband packets to generate multiple data packets, wherein the multiple data packets include a specific data packet divided into multiple sections, wherein the multiple sections are respectively composed of different Baseband packets are generated.

Step 506: add a header to the plurality of data packets and the plurality of sections of the specific data packet, wherein the header at least describes which physical layer channel the data packet or the section belongs to and the Whether the segment is the starting segment.

Step 508: Convert the multiple data packets into a single data stream and send it to the backend circuit for processing.

To briefly summarize the present invention, in the receiver and related signal processing method of the present invention, the receiver is allowed to divide the data packet into a plurality of sections for transmission, and its internal processing circuit is generating the data packet or data A section of the packet is then directly transmitted to the back-end circuit through the multiplexer for processing, and since there is no need to wait for the complete data packet before transmission, it can indeed reduce the demand for internal buffer circuits. In addition, by adding an identifiable header to each segment of the data packet, the back-end circuit can smoothly combine multiple segments of the received data packet into a complete data packet to Benefit follow-up processing.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

Claims (16)

1. a kind of receiver, includes:

One decoder, to be decoded a reception signal to generate first group of fundamental frequency package and second group of fundamental frequency package, In this first group, second group of fundamental frequency package respectively correspond to a first instance layer channel and a second instance layer channel；

One processing circuit, respectively to be handled this first group, second group of fundamental frequency package to generate first group, second group of number It wherein include a specific data package in first group of data packet according to package；And

One interface circuit, this first group, second group of data packet are transmitted to rear end electricity in a manner of a data stream Road, wherein in the data stream, a part of the specific data package is located at before second group of data packet, and should Another part of specific data package is located at after second group of data packet.

2. receiver as described in claim 1, which is characterized in that advanced television system committee's mark is helped in receiver support Standard, and each data packet is that an advanced television system committee links layer protocol package.

3. receiver as described in claim 1, which is characterized in that multiple section of the specific data package is corresponding identical It physical layer channel but is different produced by fundamental frequency package, and the processing circuit just directly should after generating each section Section is sent to the back-end circuit.

4. receiver as claimed in claim 3, which is characterized in that the receiver be not provided with for keep in multiple section with into The combined buffer circuit of row.

5. receiver as described in claim 1, which is characterized in that multiple area of the processing circuit to the specific data package Section is respectively provided with a header, and each header has included at least the identification in physical layer channel corresponding to the specific data package Code.

6. receiver as claimed in claim 5, which is characterized in that each header has additionally comprised a preliminary sectors identification code, For indicate the section whether be the specific data package preliminary sectors.

7. receiver as described in claim 1, which is characterized in that the receiver is arranged in a chip, and the back-end circuit It is located in another chip.

8. receiver as claimed in claim 7, which is characterized in that the interface circuit is effectively to believe the data stream, one Number, a synchronization signal, a clock signal and be sent to another chip, wherein the useful signal is used to indicate the current reception Whether device has the transmission data stream to another chip and the synchronization signal to be used to refer to/be aligned each data packet Or the header of each section of the specific data package.

9. a kind of signal processing method, includes:

One reception signal is decoded to generate first group of fundamental frequency package and second group of fundamental frequency package, wherein this first group, the Two groups of fundamental frequency packages are respectively corresponded to a first instance layer channel and a second instance layer channel；And

This first group, second group of fundamental frequency package are handled to generate first group, second group of data packet respectively, wherein this It include a specific data package in one group of data packet；And

This first group, second group of data packet are transmitted to a back-end circuit in a manner of a data stream, wherein in the data In crossfire, before a part of the specific data package is located at second group of data packet and the specific data package it is another A part is located at after second group of data packet.

10. signal processing method as claimed in claim 9, which is characterized in that the signal processing method is by a receiver institute It executes, which is to support advanced television system committee's standard, and each data packet is an advanced television system committee Member can link layer protocol package.

11. signal processing method as claimed in claim 9, which is characterized in that multiple section of the specific data package by With identical physical layer channel but produced by being different fundamental frequency package, each section is just delivered directly to after a birth The back-end circuit.

12. signal processing method as claimed in claim 11, which is characterized in that the signal processing method is by a receiver institute It executes, and the receiver is not provided with for keeping in multiple section the buffer circuit to merge.

13. signal processing method as claimed in claim 9, which is characterized in that also include:

One header is respectively provided with to multiple section of the specific data package, and each header has included at least the specific data The identification code in physical layer channel corresponding to package.

14. signal processing method as claimed in claim 13, which is characterized in that each header further comprises preliminary sectors knowledge Other code, be used to indicate the section whether be the specific data package preliminary sectors.

15. signal processing method as claimed in claim 9, which is characterized in that the signal processing method is by a receiver institute It executes, which is to be arranged in a chip, and the back-end circuit is located in another chip.

16. signal processing method as claimed in claim 15, which is characterized in that also include:

By the data stream, a useful signal, a synchronization signal, a clock signal and it is sent to another chip, wherein should Useful signal is used to indicate whether the current receiver has and transmits the data stream to another chip and synchronization signal use Come indicate/be aligned each data packet or the specific data package each section header.